DesignCon Pavel Zivny, Tektronix, Inc. (503)

DesignCon 2009 New methods of measuring the performance of equalized serial data links and correlation of performance measures across the design flow, from simulation to measurement, and final BER tests Pavel Zivny, Tektronix, Inc. pavel.zivny@tek.com (503) 627-4755 Steven McKinney, Mentor Graphics steven_mckinney@mentor.com (512) 425-3030 Maria Agoston, Tektronix, Inc. maria.agoston@tek.com (503) 627-2997 John Carlson, Tektronix, Inc. john.e.carlson@tek.com (503) 627-3809

Vladimir Dmitriev-Zdorov, Mentor Graphics Vladimir_Dmitriev-Zdorov@mentor.com (720) 494-1196 Abstract For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper we take a high performance equalizing serial data link and compare the performance predicted by simulation and measured by different measurement. We compare the differences between simulation and measurements and comment on a path to better correlation between the three. Authors Biography Pavel Zivny is a Product Engineer with the sampling oscilloscopes group of Tektronix. He holds an MSEE and has been with Tektronix for 23 years, working in test, design, and marketing of both real time and sampling oscilloscopes. Pavel was granted two oscilloscope related patents, authored several industry articles and papers, represents Tektronix to high-speed Serial Data standards committees, and sits on DesignCon jitter panel. Steve McKinney is a technical marketing engineer for Mentor Graphics Corporation. He is responsible for supporting Mentor s signal integrity and EMC solutions and providing technical expertise to Mentor s customers and application engineers. Steve received his BSEE and MSEE with emphasis on microwave circuit design from North Carolina State University. Maria Agoston is Principal Engineer with Tektronix. Her contributions to Tektronix instruments have been in area of digital signal processing, and most recently has been working on the e-serial jitter and noise analysis techniques. She holds a MS in Computer Engineering from Oregon State University and a MSEE from University Politechnica of Bucharest. Maria has been awarded two patents in area of waveform processing, and has authored papers on high speed serial link analysis. John Carlson is a Principal Engineer with Tektronix. As a hardware engineer he has been responsible for the design of the high bandwidth sampling modules. He holds a masters degree in Electronic Science from the Oregon Graduate Center and a BS in Electrical Engineering from Oregon State University. John has been awarded 5 patents related to sampling oscilloscope design. Vladimir Dmitriev-Zdorov is a Principal Engineer with Mentor Graphics Corporation's System Design Division. Vladimir has developed a number of advanced models and

novel simulation methods used in the company s products. He received Ph.D. and D.Sc. degrees based on his work on methods for circuit and system simulation. The results of his work have been published in numerous papers, conference proceedings and a monograph. Table of content 1. Introduction... 3 2. Role of Simulation and Measurement Based Emulation for HSS Links... 4 3. Simulation... 6 4. Physical Device Measurements... 17 5. Serial Data Link Emulation... 18 6. Comparison of Results... 19 7. Conclusions... 21 References... 22 Appendix A. Impact of Channel Asymmetry on eye diagram... 22 1. Introduction Successful design of high speed serial interconnect requires thorough simulation of the link, and consequent measurement verification and characterization of the implemented design. A lossy channel can have more than 30 db of loss at the 1 st harmonic, and have an eye diagram that is well past complete closure at the receiver end of the link. For signaling over these lossy channels, designs today are using equalization in both the transmitter and in the receiver. Older, simple measurement methods, such as horizontal eye opening at bit error rate (BER), or a mask test completely fail on closed eyes and do not provide any performance metric. Because of the issues with traditional eye measurements, new methods for evaluation of channel performance were developed. These methods share origins with the first standard-ratified measurement method for heavily equalized links, the IEEE 802.3aq 10GBASE-LRM. This method for evaluation of the transmitter performance, the TWDP, Transmitter Waveform Dispersion Penalty, uses channel simulation, equalizer simulation, and finally measures a form of Signal-to-Noise ratio on the correlated data. TWDP started in the optical domain, and the method uses three corner cases of how a multimode fiber can impact the signal, with the so-called pre-cursor, symmetrical, and postcursor response. The development of new measurement methods is tracked by both simulation and measurement tools that support equalization and channel insertion. Beginning at design and simulation and finishing with verification, this paper will walk through the steps of implementing a high performance equalizing serial data link and comparing the performance predicted by simulation, by measurement at the transmitter with channel emulation, and by measurement at the receiver end. Comparison of methods focuses on correlated eye closure that is, eye closure by the ISI (Inter-Symbol Interference) of the channel.

2. Role of Simulation and Measurement Based Emulation for HSS Links As serial data communication links are targeting higher data rates by moving into second and third generations, complementing jitter, noise and BER analysis tools with models of transmitter, channel and receiver elements provides user with tools that will help answer questions like: Will the legacy link remain compliant as data rates climb from 3 Gbps to 6 Gbps? Will the system still meet compliance when cable length growth from 6m to 10m? Measurement based Emulation tools provide means for the serial data link analysis. They help answer questions by providing means of emulating the full communication link with configurable elements that allow for adding or removing transmitter emphasis, probe deembedding, channel emulation, and equalization tools for testing the receiver capabilities. A system level work flow model describes the design and deployment phases for components of high speed serial links, from SERDES chips to cables, backplanes, etc. Figure 1 shows the role of the Simulation tools in the Design phase of devices, followed by migration to Prototype turn-on, Verification, Characterization and finally manufacturing phases which are measurement based stages of analysis. Between Characterization and commitment to a Manufacturing process, there is the Certification or Compliance Test step. Figure 1 Design and Deployment Work Flow The points this paper is proposing to show are: Given a high-performance equalized 6.25 G b/s serial data link (a) This serial data link can be simulated with Mentor Graphics simulation tools.

(b) The implemented design can be verified and characterized with Tektronix measurement tools. (c) Simulation tools can predict the worst case pattern behavior. (d) The flow above will exhibit a good match between performance expected by simulation, measured with emulation, and simply measured.. (e) The flow above allows for fast experimentation and can help answer what-if questions. System configuration Illustrations below show the three link configurations. Figure 2 shows a fully simulated link. Figure 3 illustrates measurements performed with the oscilloscope either at Transmitter or Receiver side, and finally, Figure 4 shows a setup that allows for measurements at the transmitter, and by emulating a Channel and an Equalizer estimate the BER at the receiver side. VTP0 TP1 TP2 TP3 TP4 VTP4 Transmitter IC Channel Receiver IC Tx (FPGA) Tx board TxE q SMA SMA Rx Eq (FFE/DFE/Lin) (FPGA) Rx board Rx Link Underlined test points are of primary concern of this paper Figure 2 Link Setup. This Whole Setup is simulated TP2 TP3 VTP4 Transmitter IC Receiver IC Tx (FPGA) Tx board TxE q SMA SMA Rx Eq (FFE/DFE/Lin) (FPGA) Rx board Rx Dashed block: virtual; dashed test point: virtual probing (equalizer emulated). Channel network parameters also measured (not show). Figure 3 Oscilloscope Measurements Done on the Link (Tektronix)

VTP4 Transmitter IC Receiver IC Tx (FPGA) Tx board TxE q SMA SMA Rx Eq (FFE/DFE/Lin) (FPGA) Rx board Rx Figure 4 BER Measurements of the Link are done by the BER estimation of the SDLA (Tektronix) 3. Simulation Toolset used for simulation: the system outlined above was simulated with Mentor Graphics HyperLynx software. We used the FastEye feature to perform worst case, statistical, and time domain simulation of the system and analysis of the result. The first set of experiments was made by assuming that transmitter (Tx) signal was an ideal piece-wise-linear trapezoid with a 30ps rising and falling time measured at 10-90% levels. The differential input voltage optionally underwent equalization which was then applied to the Tx package, channel, and receiver (Rx) package models connected to each other. The output was measured differentially at the die of Rx package. For the channel, we used linear models of packages provided by Xilinx for their Virtex 5 GTX device, the PCB trace model was measured on Tektronix 80E10 TDR modules, and all 4-port S- parameters were calculated by Tek s IConnect application. The S-parameters are shown in Figure 16 on page 18. Second, we attached the more detailed Tx model from Xilinx, with already equalized output to the same chain of packages and channel model. In the first experiment, our attempt was to find optimal set of equalization parameters (with Mentor s FastEye) and determine the worst case eye opening. In the second case we also investigated the worst case solution but given the fact that the actual input is not ideally symmetric, i.e. rising and falling waveform behavior on the Tx buffers were slightly different, we also considered the possible impact from an induced common mode component.

3.1. Simplified Symmetric Trapezoidal Input 1.1 Without equalization, the Rx eye is completely closed. Fig.5 illustrates the output from FastEye when applying a relatively short (about 4500 bit) worst case unconstrained bit pattern. The eye remains practically closed even with an 8b10b protocol worst case sequence (Fig.6). In part, the worst case pattern approach was described in [1, 2]. In this work we use an extended version of this worst-case bit sequence technology. The unique pattern is automatically created for each combination of channel S-parameters, equalization, bit interval, possible transition asymmetry (duty cycle distortion) and encoding protocol. Below, we will consider more details regarding this approach. 0.3 0.2 0.1 0-0.1-0.2-0.3-0.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 5 Eye Closed without Equalization

Figure 6 Closed Eyes with 8b 10b Input Given the channel s parameters and bit rate we synthesize optimal tap values for the TX equalization using optimization algorithms in FastEye. First, we selected a second order equalization and got TX equalizer tap coefficients equal to a gain of 1 for the primary tap and -0.48 for the secondary tap. As expected, the added equalization positively affected the channel s pulse response, eye diagram, while also generating a new worst case pattern for the new channel response. The diagram we got from worst case unconstrained analysis indicates that the eye is open, but ISI still significantly reduces the size of the eye opening. Fig.7 below demonstrates a typical output from the worst case input. If we applied a randomly generated PRBS, the eye body, composed from many fragmented waveforms, would remain solid and have a bigger opening in the middle than we see here. A few trajectories in the middle that affect the eye opening most are those deliberately produced by several worst case sub patterns in the worst case sequence. There are approximately 10 pairs of these sub patterns reducing the vertical size of the eye at different timing and voltage positions.

Figure 7 Two-tap Equalization, Unconstrained Worst Case Pattern Applied We achieve a similar output when applying the worst case 8b10b pattern, although the eye is left with slightly more voltage margin. This indicates that the encoding achieves its goal of reducing ISI; however the overall effect is not dramatic. Figure 8 Two-tap Equalization, 8b 10b Worst Case Pattern Applied

Rerunning the simulation analysis and adding an additional pre-cursor tap, resulting in a 3-tap TX equalizer, we were able to get even better results. The FastEye algorithms found the optimal gain values of the pre-cursor to be -0.15, the main cursor to be a gain of 1 and the post cursor to have a gain of -0.45. Similar to the previous case, the eye diagram using an unconstrained worst pattern is closed more than the eye of an 8b10b pattern (Figure 9 and 10 respectively), but it was still only slightly affected. Figure 9 3-taps Equalization, Unconstrained Worst Case

Figure 10 3-taps Equalization, 8b 10b Worst Pattern Bathtub and the worst case eye diagram There is an important relation to consider between the size of the eye built from the worst case pattern (without input random Gaussian or periodic jitter), and the bathtub curve built under the same conditions. Since the worst case eye has the smallest horizontal and vertical dimensions, it also sets the bounds for the corresponding width of the bathtub curve, where the slopes become strictly vertical. For example, the worst case eye in Fig. 11a has a horizontal size 89.7ps; for a 6.25GBs signal, this means we have 0.56UI of an eye width. This eye width is exactly the same as the opening of the horizontal bathtub of Fig.11b built with a zero voltage offset (the widest part of the eye). Although it is true that in absence of random jitter the bathtub should have vertical slopes, it often happens that the walls become vertical only at a very low probability, much lower than practically important for BER margin. In other words, at a typical level of interest (e.g. between 1e-12 and 1e-15) we have to consider the bathtub profile created by many partial probability density functions (PDFs) that ultimately depend on the response s cursors and their statistical dependency that is affected by encoding. Unfortunately, no assumption about Gaussian-like distribution is valid here. Even if we add random jitter, the resulting bathtub cannot be considered as being purely Gaussian, even at low probabilities. If we make such assumptions, we run the risk of getting a wrong BER estimate.

With the worst case pattern we are able to find the narrowest bounds on a random-jitter-less bathtub curve and can correctly predict the low probability errors, be it with or without random jitter. Figure 11a Eye diagram built from the worst case pattern

Figure 11b Bathtub built for the same channel Actual Tx Model Connected to the Channel The second set of experiments was made with a Xilinx Spice model of the driver connected to the same channel. This time 3-tap DFE equalization in the receiver was used. Our task was to investigate its worst case performance (from a practicall sense, for 8b10b patterns only) and also find out how large eye distortions can result from rising/falling asymmetry because of the common mode propagation (Appendix A). First, we measured the rising and falling transition waveforms at the receiver. Using this data, we then loaded this information into FastEye and produced the worst case 8b10b pattern and the corresponding eye diagram for the channel, as shown in Fig.12a. Fig. 12b shows the corresponding statistical contour for this same channel. The different contour lines going from outside, inward correspond to probabilities of having an error for 1e-3, 1e-6, etc, with 1e-30 being the inner most eye contour.

0.15 0.1 0.05 0-0.05-0.1-0.15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 12a Worst Case Eye Diagram for the Tx and Channel Simulated 0.08 0.06 0.04 0.02 0-0.02-0.04-0.06-0.08 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Figure 12b BER contours Found by FastEye for signal in Figure 12a At this point, it is interesting to take a closer look at the worst case solution. As stated before, the worst case eye diagram shows certain outstanding transition edges well

inside non-worst case bits in the sequence, clearly collapsing the eye. This is a powerful feature of the worst case solution. Instead of simulating millions or billions of bits at a considerable expense in time, we can only apply a short worst case pattern and achieve reliable results regarding our channels ISI performance quickly. Since the sequence s bit length is short, it can also be applied to other simulators (e.g. SPICE transient simulation) or to the actual device hardware to stress the channel. To demonstrate the effect of the worst case bit sequence on channel performance, in Figure 13 we can see the eye diagram from a very long, 100,000,000 bit simulation with 8b10b-encoded pseudo random (non-periodical) input on the example channel used in the analysis. Comparing this to the results seen with the worst case bit sequence in Figure 12a, we can clearly see that the eye is significantly wider in Figure 13. It is not possible to stress the channel with 100 Million bits as much as we are able to stress it with approximately 4,000 worst case bits. Figure 13 Eye Diagram from Long Random Sequence Let s review some of the detailed information regarding the worst case pattern. A short 8b10b fragment as in the example below 101110011001000011010101101110001000101111100110100110110010 000100111101101100001110011100000110100111100110000110011001 101111001010100100011101110010000110010110010011011110100010 100100111100011010110110010110010100101101010010011010101010 1010101010101010101010101010101010101010101

yields the two symmetric blue waveforms closest to the eye center in Figure 14 on page 16. These waveforms were found to minimize the vertical eye opening in mid-ui for this channel. Some other short fragments minimize the eye size at other timing positions, so together they create the eye shown in Fig.12a. For comparison, in Figure 14, with red lines we show the eye extremes from the above-mentioned random 100 million bit simulation compared to this worst case fragment. 0.1 0.05 0-0.05-0.1-0.15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 14 Response to a Short Fragment of the Worst Case Input (inner-most blue contour) compared to the eye extremes of an 100 Mb random, 8b/10b coded sequence (red, purple)

4. Physical Device Measurements The physical serial link is comprised of a BERT (Advantest 3681) transmitter driving 17 of differential FR4 PCB line on a backplane. At this stage no TX equalization was used. In place of the receiver, at TP3 in Figure 3, is a Tektronix DSA8200 sampling oscilloscope, with a 50 GHz module 80E10 triggered directly from the BERT. Acquired signal was analyzed with Tek application software 80SJNB Advanced, V2.1, running on the oscilloscope. See [3], [4] for 80SJNB SW algorithms. All measurements were performed with same 6.25Gbps differential NRZ signal as above. Both PRBS9 and PRBS15 patterns were used. Figure 15 Serial Link Analysis of a Transmitter connected to Physical Channel: measured (top left), with 3-tap DFE emulation in Tek 80SJNB (remaining graphs) Resulting eye diagram for PRBS15 is in Figure 15, top left. Compared to the simulation the result is closed similarly as the 8b/10b coded pattern shown in Figure 6 (page 8), but less than the worst case pattern in shown in Figure 5. A 3-tap DFE equalizer was inserted in the oscilloscope application software (Tek 80SJNB) in the signal path at the virtual comparator test point VTP4 (Figure 4 on page 6)Figure 3. The equalizer was trained for maximum vertical eye opening at mid-ui. Result is shown as the eye diagram before DFE in Figure 15, top left; and after, top right. Also after DFE are the horizontal bathtub, bottom left; and a BER eye, bottom right.

5. Serial Data Link Emulation Just like for simulation, the backplane used as the physical device was measured and the differential S-parameters, Sdd21 were used to emulate the Channel, as shown in Figure 16. Figure 16 Emulated Channel S-parameters

Figure 17 Serial Link Analysis of a Transmitter connected to an Emulated no equalization (top left), with 3-tap DFE emulation in Tek 80SJNB (remaining graphs) The output of emulated channel is equalized with a 3-tap DFE, just as in measured case. Graphs and numerical results in Figure 17 show a good match to Figure 15. 6. Comparison of Results 6.1. Bathtub Curves comparison We ve selected horizontal and vertical eye opening at BER=10-12 as the measure by which to compare results between physical measurement, emulation (physical transmitter through emulated channel), and simulation. Our results are in Table 1; corresponding images are in Figure 18 and Figure 19. All results are with 3-tap DFE equalization. Comparision of results, Eye opening at BER=10-12 Horizontal result type tool Vertical opening opening opening [UI] [ps] [of ampl.] 53.2% 85.2 "measured" Tek sampler 80E10, 80SJNB meas. 36.4% 56.2% 89.9 "emulated" Tek sampler 80E10, 80SJNB meas.&emul. 39.8% 58.1% 93.0 "simulated" Mentor HyperLynx Fast-Eye simulation 40.8% Table 1 Comparison of results between measured, emulated, and simulated

Figure 18 Correlation of Bathtub Curves: Horizontal Bathtub Figure 19 Correlation of Bathtub Curves: Vertical bathtub 6.2. BER Contours Comparison Reasonable comparison of BER contours was not done beyond of that of the bathtubs above. Simple observation and comparison of Figure 20 (PRBS9) and Figure 12b (long

pattern) suggests that while the opening is well matched the overall shape is different, perhaps because of the difference in the length of patterns. Figure 20 BER contours based on measurement and emulation (Tek 80E10 and 80SJNB), PRBS9 pattern. 6.3. Comparison of results to the BER of a practical link Our goal of comparing the calculated BERs to a complete link s BER (inclusive of RX) was not met; this remains to be done. 7. Conclusions We simulated a high speed serial link of transmitter and channel running at 6.25 Gb/s, with a 3-tap DFE equalizer. We measured such link at the transmitter with channel emulated, and measured at the receiver end. The three results were compared for vertical and horizontal eye opening and found to correlate well (4.9% for horizontal, 3.6% for vertical eye opening).

References [1] Bryan K. Casper, Matthew Haycock, Randy Mooney. - Circuit Research, Intel Labs, Hillsboro Oregon, An accurateand efficient analysis method for multi-gbs chip-to-chip signaling schemes. VLSI Circuits Digest of Technical Papers, June 13, 2002, pages 54-57. [2] Andy Turudic, Steven McKinney, Vladimir Dmitriev-Zdorov, Vince Duperron Karen Stoke, Pre-Emphasis and Equalization Parameter Optimization with Fast, Worst- Case/Multibillion-Bit Verification, DesignCon 2007 [3] Pavel Zivny, Tektronix TDS/CSA8200 Jitter Analysis Application: Jitter and Noise Analysis, BER Estimation Descriptions, Tektronix application note 61W-18921-0 [4] Pavel Zivny, Maria Agoston, John Carlson, Klaus Engenhardt, Method of BER Analysis of High Speed Serial Data Transmission in Presence of Jitter and Noise. DesignCon 2007 Appendix A. Impact of Channel Asymmetry on eye diagram Investigation of channel asymmetry was not compared between tools; only results of simulation are presented here. To answer the question of how much channel asymmetry impacts the eye opening common mode component of the signal. As we notice from Figure 12, the eye diagrams are only slightly asymmetric relative to horizontal axis. For an ideally symmetrical channel, the signal would have no common-to-differential mode conversion of energy. Even if the input contains high frequency common mode, it will not propagate to the differential output. However, because of differential skew, any realistic channel has the ability to partially convert common mode input component into differential output component that potentially may cause problems. As we see from the plot show in the HyperLynx Touchstone Viewer, common-to differential conversion (Sdc21) remains smaller than differential to differential (Sdd12) up to approximately 10GHz (Figure 21).

Figure 21 S21 Differential to Differential (red) and Common to Differential (Mode Conversion; blue) To experiment with the impact of common mode conversion, we will increase the common mode conversion by approximately 4X. The result of this increase is seen in Figure 22 a and b. The worst case 8B/10B bit sequence found for the asymmetrical transitions still remains open, but the maximum eye opening has been further reduced. Compared to the previous case, we may need to correct both the sampling threshold and the timing position in order to optimize the BER.

0.2 0.15 0.1 0.05 0-0.05-0.1-0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 22 a Worst Case Eye Diagram with 4x Increase of the Common Mode Propagation 0.1 0.05 0-0.05-0.1 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 Figure 16b Statistical Eye with 4x Common Mode Propagation (Contour lines Show Probabilities from 1e-3 to 1e-30) If we further increase the amount of common mode energy propagation to extremely large amount of 8X the original content, the eye becomes completely closed. This is

visible in both the time domain waveforms and the statistical eye contours seen in Figures 17a and b. 0.25 0.2 0.15 0.1 0.05 0-0.05-0.1-0.15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 17a Worst Case Eye with 8x Common Mode 0.1 0.08 0.06 0.04 0.02 0-0.02-0.04 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Figure 23b Statistical Contours with 8x Common Mode -end.