EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main Unit), Module KL-33001 Connecting patch chords, Jumpers THEORY: The basic logic gates are the building blocks of more complex logic circuits. These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. Figure below shows the circuit symbol, Boolean function, and truth. It is seen from the Figure that each gate has one or two binary inputs, A and B, and one binary output, C. The small circle on the output of the circuit symbols designates the logic complement. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs.
CONNECTION DIAGRAM (Module Diagram) CONNECTION DIAGRAM (Module Diagram-KL-33001 Block-d)
BASIC GATES Figure-1: Symbols and Truth table of Basic Gates PROCEDURE: 1) AND Gate a) Use U1a and U1b of the Module KL-33001 Block-d, Insert connection (clips) jumpers as per the Connection diagram. b) Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. c) Connect inputs A1, A2 to the Data Switch SW0, SW1 TTL level and output F3 to the logic indicator L0. d) Follow the input sequences below and record the outputs.
OUTPUT: Truth Table State Input Output A2 0 0 0 1 0 1 2 1 0 3 1 1 A1 F3 2) OR Gate a) Use U2a and U2b of the Module KL-33001 Block-d, Insert connection (clips) jumpers as per the Connection diagram. b) Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. c) Connect inputs A3,A4 to the Data Switch SW0,SW1 TTL level and output F3 to the logic indicator L1. d) Follow the input sequences below and record the outputs.
OUTPUT: Truth Table State Input Output A4 A3 F4 0 0 0 1 0 1 2 1 0 3 1 1 3) NOT Gate (Inverter Gate) a) Use U3c of the module KL-33001 Block-d. b) Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. c) Connect inputs C1 to the Data Switch SW0 TTL level and output F6 to the logic indicator L1. d) Follow the input sequences below and record the outputs. Input C1 0 1 Output F6
4) XOR Gate a. U4a of Module KL-33001 Block-d used in this section b. Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. c. Connect inputs C4,C5 to the Data Switch SW0,SW1 TTL level and output F9 to the logic indicator L1. d. Follow the input sequences below and record the outputs. OUTPUT: Truth Table State Input Output C3 C4 F9 0 0 0 1 0 1 2 1 0 3 1 1
UNIVERSAL GATES Figure-2: Symbols and Truth table of Basic Gates 5) NAND Gate a. U1a of the Module KL-33001 Block-d to be used in this section Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. b. Connect inputs A1, A2 to the Data Switch SW0, SW1 TTL level and output F1 to the logic indicator L1. c. Follow the input sequences below and record the outputs. OUTPUT: Truth Table State Input Output A2 A1 F1 0 0 0 1 0 1 2 1 0 3 1 1
6) NOR Gate a. U2a of the Module KL-33001Block-d used in this section. Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. b. Connect inputs A3,A4 to the Data Switch SW0,SW1 TTL level and output F2 to the logic indicator L1. c. Follow the input sequences below and record the outputs. OUTPUT: Truth Table State Input Output A4 A3 F2 0 0 0 1 0 1 2 1 0 3 1 1 Comments:
EXPERIMENT: 2- Half Adder and Full Adder Circuit AIM: To realize half adder and full adder Circuit. LEARNING OBJECTIVE: To realize the half adder and full adder circuits using basic gates. Understanding the characteristics of half adder and full adder. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main Unit), Module KL-33003/KL-33004 Connecting patch chords, Jumpers THEORY: Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S and the other is the carry bit, C. The Boolean functions describing the half-adder are: Sum Carry Full-Adder: The half-adder does not take the carry bit from its previous stage into account. This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing the full-adder are:
Connection Diagram for Half Adder and Full Adder CONNECTION DIAGRAM (Module Diagram-KL-33004 Block-a)
Truth Table Input Output SW1(B) SW0(A) F1 F2 0 0 0 1 1 0 1 1 PROCEDURE 1) Constructing Half adder with Basic Logic Gate a) Use U2a and U3a of the Module KL-33004 Block-a, Insert connection (clips) jumpers as per the Connection diagram (a). b) Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. c) Connect inputs A, B to the Data Switch SW0, SW1 and outputs F1 and F2 to the logic indicator L1 and L2. d) Follow the input sequences below and record the output states. e) Determine which output is sum and carry
Truth Table Input Output SW3(C) SW1(B) SW0(A) F3 F5 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
PROCEDURE 2) Constructing Full adder with Basic Logic Gate a) Use U2a and U3a of the Module KL-33004 Block-a, Insert connection (clips) jumpers as per the Connection diagram. b) Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. c) Connect inputs A, B,C to the Data Switch SW0, SW1 and SW2. A and B are augends while C is the previous carry. d) Connect F3 to L1, F5 to L2 e) Follow the input sequences below and record the output states. f) Determine which output is sum and carry Comments:
EXPERIMENT: 3- Constructing a 4-to-2 Encoder and Decoder using basic gates AIM: To constructing a 4-to-2 Encoder and 2-to-4 Decoder using basic gates. LEARNING OBJECTIVE: To constructing a 4-to-2 Encoder and 2-to-4 Decoder using basic gates. Understanding the operating principles of encoder and decoder circuit. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main Unit), Module KL-33005/KL-33006 Connecting patch chords, Jumpers THEORY: ENCODER CIRCUIT: Encoder is a combinational logic circuit that accept one or multiple inputs and generates a specific output code. Only one input is triggered at a time. And encoder with 2 n -bit inputs and n-bit output is shown in figure. When one of the input is triggered there will be a n-bit output code at the outputs. 2 n -inputs - n-outputs
PROCEDURE a) Constructing a 4-to-2 Encoder with Basic gates 1. Use KL-33005 module for this experiment. Insert connection clips according to the connection diagram-1 between A & A1, B & B1, C & C1 as shown. 2. Connect V CC to +5 Volts. 3. Connect inputs A,B,C,D to data switch SW0-SW3 respectively amd outputs F8 and F9 to logic indicator L0 and L1. 4. Follow the input sequences for D, C, B, A in the table-1 and record the output states. CONNECTION DIAGRAM-1
Table-1 Output D C B A F8 F9 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
DECODER CIRCUIT: Decoder is a combinational logic circuit that will detect the presence of the binary input number or word. The input to the decoder is a parallel binary number and the output is a binary signal that indicates the presence or absence of that specific number. b) Constructing a 2-to-4 Decoder with Basic gates 1. Block c of the module KL-33005 will be used in this section. Use connection diagram-3 2. Connect V CC to +5 Volts. 3. Connect inputs A,B to Data Switch SW0 and SW1. 4. Connect output F1, F2,F3,F4 to the logic indicator L0, L1,L2,L3 respectively. 5. Follow the input sequences for A and B in table-3 and record the output states. Table-3 Outputs B A F1 F2 F3 F4 0 0 0 1 1 0 1 1
CONNECTION DIAGRAM-2 COMMENTS
EXPERIMENT: 4- Constructing a 2-to-1 Multiplexer and 2 output Demultiplexer using basic gates AIM: To Constructing a 2-to-1 Multiplexer and 2 output Demultiplexer using basic gates LEARNING OBJECTIVE: To constructing a 2-to-1 Encoder and demultiplexer using basic gates. Understanding the operating principles of multiplexer and demultiplexer circuit. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main Unit), Module KL -33006 Connecting patch chords, Jumpers THEORY: Multiplexer: Multiplexers are very useful components in digital systems. They transfer a large number of information units over a smaller number of channels, (usually one channel) under the control of selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one output. By using control signals (select lines) we can select any input to the output. Multiplexer is also called as data selector because the output bit depends on the input data bit that is selected. The general multiplexer circuit has 2 n input signals, n control/select signals and 1 output signal.
PROCEDURE Constructing a 2-to-1 Multiplexer with Basic gates 1. Use KL-33006 module (Block e) for this experiment according to the connection diagram-1 2. Connect V CC to +5 Volts. 3. Connect inputs A,B,C to data switch SW0, SW1, SW2 respectively amd outputs F3 to logic indicator L0. 4. Follow the input sequences for C, B, A in the table-1 and record the output states.
TRUTH TABLE (Multiplexe) C Select B A F3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 CONNECTION DIAGRAM-1
DEMULTIPLEXER: De-multiplexers perform the opposite function of multiplexers. They transfer a small number of information units (usually one unit) over a larger number of channels under the control of selection signals. The general demultiplexer circuit has 1 input signal, n control/select signals and 2 n output signals. De-multiplexer circuit can also be realized using a decoder circuit with enable. Constructing a 1-to-2 Demultiplexer with Basic gates 1. Use KL-33006 module (Block e) for this experiment. Insert connection clips according to the connection diagram-2 2. Connect V CC to +5 Volts. 3. Connect inputs A to data switch SW0; C to SW3 respectively amd outputs F1 and F2 to logic indicator L0 and L1. 4. Set c to 0 and change the data, 5. Follow the input sequences for C, A in the table-2 and record the output states.
TRUTH TABLE (De-Multiplexer) C Select A Data F1 F2 0 0 0 A=0 0 1 0 A=1 1 0 A=0 0 1 1 A=1 0 CONNECTION DIAGRAM-1
Demultiplexer
EXPERIMENT: 5- Truth Table Verification of Flip Flops AIM: Truth Table verification of 1) RS Flip Flop 2) D type Flip Flop. 3) JK Flip Flop. LEARNING OBJECTIVE: To verify the truth table using basic logic gates. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main Unit), Module KL -33008 Connecting patch chords, Jumpers THEORY: In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the simple ones are commonly called latches.[1] The word latch is mainly used for storage elements, while clocked devices are described as flip-flops.[2] A latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge. Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"[11]), T ("toggle"), and JK types are the common ones. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, Qnext in terms of the input signal(s) and/or the current output,. 1-Constructing a R-S Flip-Flop with Basic Gates PROCEDURE : 1. Connect inputs A3, A4 to the pulser Switch SWA- A, SWA- B, output. 2. Connect output F6 and F7 to the logic indicators L1, L2 3. Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. 4. Follow the input sequence in the table and observe and record F6 and F7
CONNECTION DIAGRAM-1
Truth Table for R-S Flip-Flop State Input Output A4 A3 F6 F7 0 0 0 1 0 1 2 1 0 3 1 1 2-Constructing a D- Flip-Flop with R-S Flip-Flop PROCEDURE : 1. Insert connection clips accoding to the connection diagram-2 2. Connect inputs A1 the Switch SW1 and CK-2 to SW2. 3. Connect output F6 to the logic indicators L1 4. Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. 5. Follow the input sequence in the table and observe and record F6 and F7
Truth Table for R-S Flip-Flop Clock Input CK-2 A1 F6 0 0 0 1 1 0 1 1
CONNECTION DIAGRAM-2
3-Constructing a J-K- Flip-Flop with D- Flip-Flop PROCEDURE : 1. Insert connection clips accoding to the connection diagram-3 2. Connect CK-2 to SWB B. 3. Connect inputs A1 the Switch SW1 and A5 to SW0 4. Connect output F6 and F7 to the logic indicators L1 and L0. 5. Connect +5 V and Ground (GND) from the DC power supply from the main unit to the module. 6. Follow the input sequence in the table and observe and record F6 and F7 Truth Table for R-S Flip-Flop Clock Input Output CK-2 A5 A1 F6 1 0 0 1 0 1 1 1 0 1 1 1
CONNECTION DIAGRAM-3