CSE140L: Components and Design Techniques for Digital Systems Lab CPU design and PLDs Tajana Simunic Rosing Source: Vahid, Katz 1
Lab #3 due Lab #4 CPU design Today: CPU design - lab overview PLDs Updates & Outline 2
CSE140L: Components and Design Techniques for Digital Systems Lab Lab #4 CPU design Tajana Simunic Rosing Source: Vahid, Katz 3
Simple in-order processor Objectives: Implementing a real processor on FPGA (challenging but fun!) Challenges: Design and implement the processor data path Design and implement the processor control units Make the whole thing work
Processor overview Control unit PC Address Instruction Memory Register File ALU 7-bit instruction
Instruction format Each Instruction has a size of 7 bits Instruction format 3-bit OP code 4-bit data Determines the instruction (i.e 100 = add)
Instruction set R3 = R1 + R2
Holds the whole program instructions Implemented as a ROM Can hold up to 16 instructions Instruction memory module instruction_rom(addr, inst); input [3:0] addr; output [6:0] inst; wire [6:0] memory [15:0]; assign memory[0] = 7'b0000000; assign memory[1] = 7'b0010001; assign memory[2] = 7'b0100010; assign memory[3] = 7'b1000000; assign memory[4] = 7'b0110000; assign memory[5] = 7'b0100100; assign memory[6] = 7'b1100000; assign memory[7] = 7'b1110011; assign memory[8] = 7'b0000000; assign memory[9] = 7'b0000000; assign memory[10] = 7'b0000000; assign memory[11] = 7'b0000000; assign memory[12] = 7'b0000000; assign memory[13] = 7'b0000000; assign memory[14] = 7'b0000000; assign memory[15] = 7'b0000000; assign inst = memory[addr]; endmodule Address Instruction Memory 7-bit instruction
Program counter Generate the next instruction address For non-control flow instructions PC = PC + 1 (Enable signal = 1) clk enable reset load For control flow instructions Branch address PC = Branch address (load signal = 1) PC Address to memory Think about how to implement this unit
Instruction decoder Decodes the instruction by reading the 3-bit OP code bits from the memory Generate the control signals to the rest of the processor (i.e. tells the ALU to add when there is an ADD instruction) Instruction 3bit OP Control unit Data path control signals Think about how to implement this unit
Register file Contains THREE 4-bit registers and the Flag bit Each register is made up of D-FF Control signals Challenge: Determine the appropriate interfacing with the rest of you processor Instruction (bit0-bit3) Register File ALU Compare flag ALU output
ALU Control Performs Addition, Multiplication and comparison Two input 4-bit operands Outputs: 4-bit results and 1-bit Compare Implement it! Input operands ALU Results Interfacing
Sample code
Test your design Testing phase is essential to ensure that your design is a bug free Here are some tips Generate test cases for all the instructions Generate test cases with various input conditions Generate test cases for some interesting combinations of instructions (e.g. control flow with non-control flow instructions) Good luck and have FUN!
CSE140L: Components and Design Techniques for Digital Systems Lab PLDs (cont.) Tajana Simunic Rosing Source: Xilinx 15
Programmable Logic Devices (PLD) PLDs combine PLA/PAL with memory and other advanced structures Similar to PLA/PAL, hence Field-Programmable Gate Arrays Types: Antifuse PLDs EPLD & EEPLD FPGAs with RAMs FPGA with processing Digital Signal Processing General purpose CPU 16
Field-Programmable Gate Arrays Logic blocks To implement combinational and sequential logic Interconnect Wires to connect inputs and outputs to logic blocks I/O blocks Special logic blocks at periphery of device for external connections Key questions: How to make logic blocks programmable? How to connect the wires? After the chip has been manufactured
Actel s Axcelerator Family Antifuse PLDs Antifuse: open when not programmed Low resistance when programmed 18
Actel s Axcelerator C-Cell C-Cell Basic multiplexer logic plus more inputs and support for fast carry calculation Carry connections are direct and do not require propagation through the programmable interconnect
Actel s Accelerator R-Cell R-Cell Core is D flip-flop Muxes for altering the clock and selecting an input Feed back path for current value of the flip-flop for simple hold Direct connection from one C-cell output of logic module to an R-cell input; Eliminates need to use the programmable interconnect Interconnection Fabric Partitioned wires Special long wires
Altera s EEPLD Altera s MAX 7k Block Diagram Global Routing: Programmable Interconnect Array Logic Array Blocks 21
EEPLD Altera s MAX 7k Logic Block 22
SRAM based PLD Altera s Flex 10k Block Diagram 23
SRAM based PLD Altera s Flex 10k Logic Array Block (LAB) 24
SRAM based PLD Altera s Flex 10k Logic Element (LE) 25
Slew Rate Control Passive Pull-Up, Pull-Down Vcc CLB CLB Switch Matrix D Q Output Buffer Pad CLB CLB Q D Delay Input Buffer Programmable Interconnect I/O Blocks (IOBs) C1 C2 C3 C4 H1 DIN S/R EC S/R Control G4 G3 G2 G1 F4 F3 F2 F1 G Func. Gen. F Func. Gen. H Func. Gen. DIN F' G' H' G' H' DIN F' G' H' 1 S/R Control SD D Q EC RD SD D Q Y Configurable Logic Blocks (CLBs) EC K H' F' 1 RD X
FPGA with DSP Altera s Stratix II: Block Diagram 28
FPGA with DSP Altera s Stratix II: DSP Detail 29
FPGA with General Purpose CPU & Analog Actel s Fusion Family Diagram FPGA with ARM 7 CPU and Analog Components 30
Discrete Gates Packaged Logic PLAs Programmable Logic Summary Ever more general architectures of programmable combinational + sequential logic and interconnect Altera Actel Xilinx