Lecture 2: Basic FPGA Fabric. James C. Hoe Department of ECE Carnegie Mellon University
|
|
- James Houston
- 5 years ago
- Views:
Transcription
1 Lecture 2: Basic FPGA Fabric James. Hoe Department of EE arnegie Mellon University F17 L02 S1, James. Hoe, MU/EE/ALM, 2017
2 Housekeeping Your goal today: know enough to build a basic FPGA (even if not a very good one) Notices omplete survey on Blackboard, due noon, 9/5 Handout #2: lab 0, due noon, 9/8 Make friends, make teams, due noon, 9/8 Readings h 1, Reconfigurable omputing skim h 13&14 if interested skim databooks referenced for more details F17 L02 S2, James. Hoe, MU/EE/ALM, 2017
3 Before FPGA there was GA (AB) (X+Y) V GND F17 L02 S3, James. Hoe, MU/EE/ALM, 2017 A B X Y
4 Idea behind Gate Arrays Mass produce identical gate array wafers Finish into any design by custom metal layers (2) so called Mask Programmable GA (MPGA) reduced design effort (more automation, no layout) reduced mask and fab cost faster fab turn around Proliferation of ASI design starts don t need volume for economy of scale small design team could keep up with Moore s law F17 L02 S4, James. Hoe, MU/EE/ALM, 2017 Of course, not as efficient as full custom or standard cell designs
5 How about no mask, no fab? i.e., field programmable Again, mass produce identical devices but this time fully finalized Then what can be changed? SRAM EPROM (anti)fuse bits {1,0} {1,0} {1,0} connections pass gate mux {1,0} diode {1,0} A B F17 L02 S5, James. Hoe, MU/EE/ALM, 2017 A B A B programmable vs reprogrammable
6 F17 L02 S6, James. Hoe, MU/EE/ALM, 2017 Reconfigurable Logic Arbitrary logic (combinational and sequential) can be formed by wiring up enough NANDs or muxes Lookup table as universal logic primitive arbitrary n input function from 2 n entry table this is 8 by 1 bit memory f(,0, ) f(,1, ) f(0,0,0) f(0,0,1) f(1,1,0) f(1,1,1) X 0 f(,x, ) 1 Shannon expansion AB f(a,b,)
7 Size of Lookup Tables (aka LUTs) n input function from 2 n entry LUT ount only the 6T SRAM cells, an n LUT has 6 2 n T Some points of reference 2 input NAND = 4T 3 input NAND =6T 3 input full adder (a, b, c in ) s = a b c in = 8T c out = bc in +ac in +ab =18T 10 input 5 bit adder = 130T M.S. flip flop=16t (compare to 2 LUTs per latch) F17 L02 S7, James. Hoe, MU/EE/ALM, 2017 n LUT T count
8 hoosing LUT Granularity Small LUTs + fast propagation delay a given fxn consumes many LUTs (comes with wiring cost and delay) high interpretation overhead if too small Big LUTs slower propagation delay + a given fxn consumes fewer LUTs high interpretation overhead if too large (and fxn has exploitable structure) wastage if not all input are used in a LUT Where is the sweetspot? F17 L02 S8, James. Hoe, MU/EE/ALM, 2017
9 1980 s Xilinx LUT based onfigurable Logic Block (in a sketch) D A B 3 LUT 3 LUT X g(a,b,) {2,1,0} Y h(a,b,,d) {2,1,0} FF f(a,b,) {1,0} (also latch mode) 2 fxns (f & g) of 3 inputs OR 1 fxn (h) of 4 inputs hardwired FFs (too expensive to fake with LUTs) Just 10s of these in the earliest FPGAs F17 L02 S9, James. Hoe, MU/EE/ALM, 2017
10 ontemporary Xilinx LB Architecture each 6LUT is two 5LUTs LUTs can also be used as small SRAMs or shift register special paths for addition and multiplexer 2 slices per LB Largest devices (many $K each) have several 100K slices [Figure 2 3: 7 Series FPGAs LB User Guide] F17 L02 S10, James. Hoe, MU/EE/ALM, 2017
11 Even oarser Logic Blocks? So called oarse Grain Reconfigurable Arrays (GRAs) based on complete adders or ALUs native arithmetic units have low interpretation overhead if you are doing arithmetic poor fit if you are working with narrow data or bitlevel manipulations Even coarser is to use many tiny processors still a spatial computing paradigm not programmed with RTLs converging with software multicores F17 L02 S11, James. Hoe, MU/EE/ALM, 2017 More on this later in term
12 Mapping Logic To LUTs Start from primary output and input to registers, cover logic graph with cuts of less than K input edges K cuts corresponding to K LUT realizable functions [Figure 13.1: Reconfigurable omputing: The Theory and Practice of FPGA Based omputation ] F17 L02 S12, James. Hoe, MU/EE/ALM, 2017
13 Placement F17 L02 S13, James. Hoe, MU/EE/ALM, 2017 [Vivado Implementation Screenshot]
14 and Route F17 L02 S14, James. Hoe, MU/EE/ALM, 2017 [Vivado Implementation Screenshot]
15 PLA style onfigurable Routing AND OR?????? I 0 I 1 I n 1 O 0 O 1 O m F17 L02 S15, James. Hoe, MU/EE/ALM, 2017
16 Island Style Routing Architecture LB islands in sea of interconnects Flexible routing to support ASI style netlists Note regularity in structure F17 L02 S16, James. Hoe, MU/EE/ALM, 2017
17 Switch Block onfigurable Routing (1980s Xilinx simplified) B LB onnection Block F17 L02 S17, James. Hoe, MU/EE/ALM, 2017
18 Reconfigurable Routing is Expensive! Routing resource area is on par with logic Each configurable connection is area of configuration bit area of configurable connection And don t forget propagation delay Too much: cost for everyone who doesn t need it Too little: congestion leaves unreachable LBs unused worse for larger arrays/designs (why?) buy a $10K FPGA and only get to use 70%? F17 L02 S18, James. Hoe, MU/EE/ALM, 2017
19 Rent s Rule T g p T = number of inputs and outputs g = number of internal components p typically between 0.5 (regular) and 0.8 (random) In a square, perimeter=4 area 0.5 unless regular, I/O signals grow faster than available routes exiting a design area Need hierarchy of progressively longer additional routing resources long routes also reduce delay when going far F17 L02 S19, James. Hoe, MU/EE/ALM, 2017
20 Virtex II Routing Architecture 8 internal fast connects from LUT to LUT within a LB Switch Matrix connects to 1 LB 16 Direct onnections to 8 nearest switches Double Lines to 1 st or 2 nd switch (40 track) Hex lines to 3 rd or 6 th switch (120 per track) Long lines spanning device (24 per track) Later architectures extended in reach and in diagonals F17 L02 S20, James. Hoe, MU/EE/ALM, 2017 Separate, dedicated clock trees
21 Virtex II Routing Architecture [Figure 48: Virtex II Platform FPGAs: omplete Data Sheet] F17 L02 S21, James. Hoe, MU/EE/ALM, 2017
22 Virtex II Routing Architecture [Figure 49: Virtex II Platform FPGAs: omplete Data Sheet] F17 L02 S22, James. Hoe, MU/EE/ALM, 2017
23 Latest in Routing Hierarchy Virtex7 Stacked Silicon Interconnect (SSI), 2011 Longest routes go across dies carried on interposer No change to design tool and abstraction [Figure 1, Stacked & Loaded: Xilinx SSI, 28 Gbps I/O Yield Amazing FPGAs, Xcell, Q1 2011] F17 L02 S23, James. Hoe, MU/EE/ALM, 2017
24 F17 L02 S24, James. Hoe, MU/EE/ALM, 2017 Altera Stratix X HyperFlex Long routes need buffered repeaters; very long routes need pipelining Add (bypassable) pipeline registers throughout RTL designs have to be pipelined explicitly to benefit; high level synthesized designs leverage directly a high freq strategy e.g., 0.5xlogic at 2xfreq for perf. parity [Figure 2: Understanding How the New HyperFlex Architecture Enables Next Generation High Performance Systems]
25 Don t Forget onfigurable I/O In/Out Dout {1,0} {1,0} {1,0} {fast,slow} {1,0} FF PAD Din {1,0} F17 L02 S25, James. Hoe, MU/EE/ALM, 2017 I/O Block real devices more complicated modern devices support special signaling and protocols
26 Putting it all together: An Universal ASI programmable routing I programmable lookup tables (LUT) and flip flops (FF) aka soft logic or fabric I/O pins Interconnect LUT FF F17 L02 S26, James. Hoe, MU/EE/ALM, 2017
27 Bitstream defines the chip After power up, SRAM FPGA loads bitstream from somewhere before becoming the chip a bonus feature for sensitive devices that need to forget what it does Many built in loading options Non trivial amount of time; must control reset timing and sequence with the rest of the system Reverse engineering concerns ameliorated by encryption proprietary knowledge F17 L02 S27, James. Hoe, MU/EE/ALM, 2017
28 Setting onfiguration Bits Behind the scene infrastructure doesn t need to be fast (usually offline) simpler/cheaper the better (at least used to be) ould organize bits into addressable SRAM or EPROM array very basic technology serial external interface to save on I/O pins row F17 L02 S28, James. Hoe, MU/EE/ALM, 2017 column
29 Serial Scan SRAM based config. bits can be setup as one or many scan chains on very slow config. clock φ 1 no addressing overhead all minimum sized devices φ 1 φ 1 φ 1 φ 1 At power up config manager handshake externally (various options, serial, parallel ROM, PI E,...) F17 L02 S29, James. Hoe, MU/EE/ALM, 2017 φ 1 φ 1 Full fledged config. architecture in modern devices to support scale and features φ 1
30 Modern onfiguration Architecture e.g., Stratix 10 Secure Device Manager triple redundant secure processor each sector managed by its own processor [Figure 2: Intel Stratix 10 Secure Device Manager Provides Best in lass FPGA and So Security ] F17 L02 S30, James. Hoe, MU/EE/ALM, 2017
31 Parting Thoughts Today, you can use an FPGA without knowing any of this stuff Basing this lecture on Xilinx vs Altera wouldn t change the big picture You can find a lot of specific details on line (databooks and research papers) So far still just the basic fabric more next time Also didn t say anything about design tools F17 L02 S31, James. Hoe, MU/EE/ALM, 2017
L11/12: Reconfigurable Logic Architectures
L11/12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley,
More informationL12: Reconfigurable Logic Architectures
L12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Frank Honore Prof. Randy Katz (Unified Microelectronics
More informationWhy FPGAs? FPGA Overview. Why FPGAs?
Transistor-level Logic Circuits Positive Level-sensitive EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 28, 2003 John Wawrzynek Transistor Level clk clk clk Positive
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. CPU design and PLDs. Tajana Simunic Rosing. Source: Vahid, Katz
CSE140L: Components and Design Techniques for Digital Systems Lab CPU design and PLDs Tajana Simunic Rosing Source: Vahid, Katz 1 Lab #3 due Lab #4 CPU design Today: CPU design - lab overview PLDs Updates
More informationField Programmable Gate Arrays (FPGAs)
Field Programmable Gate Arrays (FPGAs) Introduction Simulations and prototyping have been a very important part of the electronics industry since a very long time now. Before heading in for the actual
More informationReconfigurable Architectures. Greg Stitt ECE Department University of Florida
Reconfigurable Architectures Greg Stitt ECE Department University of Florida How can hardware be reconfigurable? Problem: Can t change fabricated chip ASICs are fixed Solution: Create components that can
More informationMarch 13, :36 vra80334_appe Sheet number 1 Page number 893 black. appendix. Commercial Devices
March 13, 2007 14:36 vra80334_appe Sheet number 1 Page number 893 black appendix E Commercial Devices In Chapter 3 we described the three main types of programmable logic devices (PLDs): simple PLDs, complex
More informationHigh Performance Carry Chains for FPGAs
High Performance Carry Chains for FPGAs Matthew M. Hosler Department of Electrical and Computer Engineering Northwestern University Abstract Carry chains are an important consideration for most computations,
More informationCDA 4253 FPGA System Design FPGA Architectures. Hao Zheng Dept of Comp Sci & Eng U of South Florida
CDA 4253 FPGA System Design FPGA Architectures Hao Zheng Dept of Comp Sci & Eng U of South Florida FPGAs Generic Architecture Also include common fixed logic blocks for higher performance: On-chip mem.
More informationIntroduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX Power Dissipation
Outline CPE 528: Session #12 Department of Electrical and Computer Engineering University of Alabama in Huntsville Introduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX Power Dissipation
More informationRELATED WORK Integrated circuits and programmable devices
Chapter 2 RELATED WORK 2.1. Integrated circuits and programmable devices 2.1.1. Introduction By the late 1940s the first transistor was created as a point-contact device formed from germanium. Such an
More informationEECS150 - Digital Design Lecture 3 Synchronous Digital Systems Review. Announcements
EECS150 - Digital Design Lecture 3 Synchronous Digital Systems Review September 1, 2011 Elad Alon Electrical Engineering and Computer Sciences University of California, Berkeley http://www-inst.eecs.berkeley.edu/~cs150
More informationDIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
More informationFPGA Design with VHDL
FPGA Design with VHDL Justus-Liebig-Universität Gießen, II. Physikalisches Institut Ming Liu Dr. Sören Lange Prof. Dr. Wolfgang Kühn ming.liu@physik.uni-giessen.de Lecture Digital design basics Basic logic
More informationEECS150 - Digital Design Lecture 18 - Circuit Timing (2) In General...
EECS150 - Digital Design Lecture 18 - Circuit Timing (2) March 17, 2010 John Wawrzynek Spring 2010 EECS150 - Lec18-timing(2) Page 1 In General... For correct operation: T τ clk Q + τ CL + τ setup for all
More informationEN2911X: Reconfigurable Computing Topic 01: Programmable Logic. Prof. Sherief Reda School of Engineering, Brown University Fall 2014
EN2911X: Reconfigurable Computing Topic 01: Programmable Logic Prof. Sherief Reda School of Engineering, Brown University Fall 2014 1 Contents 1. Architecture of modern FPGAs Programmable interconnect
More informationCAD for VLSI Design - I Lecture 38. V. Kamakoti and Shankar Balachandran
1 CAD for VLSI Design - I Lecture 38 V. Kamakoti and Shankar Balachandran 2 Overview Commercial FPGAs Architecture LookUp Table based Architectures Routing Architectures FPGA CAD flow revisited 3 Xilinx
More informationFPGA Design. Part I - Hardware Components. Thomas Lenzi
FPGA Design Part I - Hardware Components Thomas Lenzi Approach We believe that having knowledge of the hardware components that compose an FPGA allow for better firmware design. Being able to visualise
More information11. Sequential Elements
11. Sequential Elements Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 11, 2017 ECE Department, University of Texas at Austin
More informationLecture 23 Design for Testability (DFT): Full-Scan
Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads
More informationChapter 7 Memory and Programmable Logic
EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error
More informationRead-only memory (ROM) Digital logic: ALUs Sequential logic circuits. Don't cares. Bus
Digital logic: ALUs Sequential logic circuits CS207, Fall 2004 October 11, 13, and 15, 2004 1 Read-only memory (ROM) A form of memory Contents fixed when circuit is created n input lines for 2 n addressable
More informationAdvanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20
Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.
More informationTestability: Lecture 23 Design for Testability (DFT) Slide 1 of 43
Testability: Lecture 23 Design for Testability (DFT) Shaahin hi Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared p by
More informationLecture 23 Design for Testability (DFT): Full-Scan (chapter14)
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system Summary
More informationOF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS
IMPLEMENTATION OF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS 1 G. Sowmya Bala 2 A. Rama Krishna 1 PG student, Dept. of ECM. K.L.University, Vaddeswaram, A.P, India, 2 Assistant Professor,
More information9 Programmable Logic Devices
Introduction to Programmable Logic Devices A programmable logic device is an IC that is user configurable and is capable of implementing logic functions. It is an LSI chip that contains a 'regular' structure
More informationObjectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
More informationExamples of FPLD Families: Actel ACT, Xilinx LCA, Altera MAX 5000 & 7000
Examples of FPL Families: Actel ACT, Xilinx LCA, Altera AX 5 & 7 Actel ACT Family ffl The Actel ACT family employs multiplexer-based logic cells. ffl A row-based architecture is used in which the logic
More informationESE534: Computer Organization. Previously. Today. Previously. Today. Preclass 1. Instruction Space Modeling
ESE534: Computer Organization Previously Instruction Space Modeling Day 15: March 24, 2014 Empirical Comparisons Previously Programmable compute blocks LUTs, ALUs, PLAs Today What if we just built a custom
More informationIE1204 Digital Design. F11: Programmable Logic, VHDL for Sequential Circuits. Masoumeh (Azin) Ebrahimi
IE1204 Digital Design F11: Programmable Logic, VHDL for Sequential Circuits Masoumeh (Azin) Ebrahimi (masebr@kth.se) Elena Dubrova (dubrova@kth.se) KTH / ICT / ES This lecture BV pp. 98-118, 418-426, 507-519
More informationTKK S ASIC-PIIRIEN SUUNNITTELU
Design TKK S-88.134 ASIC-PIIRIEN SUUNNITTELU Design Flow 3.2.2005 RTL Design 10.2.2005 Implementation 7.4.2005 Contents 1. Terminology 2. RTL to Parts flow 3. Logic synthesis 4. Static Timing Analysis
More informationCombinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
More informationESE534: Computer Organization. Last Time. Last Time. Today. Preclass. Preclass. LUTs. Day 15: March 22, 2010 Compute 2: Cascades, ALUs, PLAs
ESE534: Computer Organization Last Time LUTs area Day 15: March 22, 2010 Compute 2: Cascades, ALUs, PLAs structure big LUTs vs. small LUTs with interconnect design space optimization 1 2 Today Last Time
More informationScan. This is a sample of the first 15 pages of the Scan chapter.
Scan This is a sample of the first 15 pages of the Scan chapter. Note: The book is NOT Pinted in color. Objectives: This section provides: An overview of Scan An introduction to Test Sequences and Test
More informationChapter Contents. Appendix A: Digital Logic. Some Definitions
A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational
More informationComputer Architecture and Organization
A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationA Fast Constant Coefficient Multiplier for the XC6200
A Fast Constant Coefficient Multiplier for the XC6200 Tom Kean, Bernie New and Bob Slous Xilinx Inc. Abstract. We discuss the design of a high performance constant coefficient multiplier on the Xilinx
More informationLecture 6: Simple and Complex Programmable Logic Devices. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 6: Simple and Complex Programmable Logic Devices MEMORY 2 Volatile: need electrical power Nonvolatile: magnetic disk, retains its stored information after the removal
More informationInvestigation of Look-Up Table Based FPGAs Using Various IDCT Architectures
Investigation of Look-Up Table Based FPGAs Using Various IDCT Architectures Jörn Gause Abstract This paper presents an investigation of Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs)
More informationINTERMEDIATE FABRICS: LOW-OVERHEAD COARSE-GRAINED VIRTUAL RECONFIGURABLE FABRICS TO ENABLE FAST PLACE AND ROUTE
INTERMEDIATE FABRICS: LOW-OVERHEAD COARSE-GRAINED VIRTUAL RECONFIGURABLE FABRICS TO ENABLE FAST PLACE AND ROUTE By AARON LANDY A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN
More informationLossless Compression Algorithms for Direct- Write Lithography Systems
Lossless Compression Algorithms for Direct- Write Lithography Systems Hsin-I Liu Video and Image Processing Lab Department of Electrical Engineering and Computer Science University of California at Berkeley
More informationEE 447/547 VLSI Design. Lecture 9: Sequential Circuits. VLSI Design EE 447/547 Sequential circuits 1
EE 447/547 VLSI esign Lecture 9: Sequential Circuits Sequential circuits 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking Sequential
More informationLogic Devices for Interfacing, The 8085 MPU Lecture 4
Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs
More informationRegister Files and Memories
Register Files and Memories ECE 554 Digital Engineering Laboratory C. R. Kime 2/18/2002 Register Files and Memories Register Files Issues and Objectives Register File Concepts Implementation of Register
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Tajana Simunic Rosing. Source: Vahid, Katz
CSE140L: Components and Design Techniques for Digital Systems Lab FSMs Tajana Simunic Rosing Source: Vahid, Katz 1 Flip-flops Hardware Description Languages and Sequential Logic representation of clocks
More informationBoolean, 1s and 0s stuff: synthesis, verification, representation This is what happens in the front end of the ASIC design process
(Lec 11) From Logic To Layout What you know... Boolean, 1s and 0s stuff: synthesis, verification, representation This is what happens in the front end of the ASIC design process High-level design description
More informationLecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time
More informationIE1204 Digital Design F11: Programmable Logic, VHDL for Sequential Circuits
IE1204 Digital Design F11: Programmable Logic, VHDL for Sequential Circuits Elena Dubrova KTH/ICT/ES dubrova@kth.se This lecture BV pp. 98-118, 418-426, 507-519 IE1204 Digital Design, HT14 2 Programmable
More informationThe Stratix II Logic and Routing Architecture
The Stratix II Logic and Routing Architecture David Lewis*, Elias Ahmed*, Gregg Baeckler, Vaughn Betz*, Mark Bourgeault*, David Cashman*, David Galloway*, Mike Hutton, Chris Lane, Andy Lee, Paul Leventis*,
More informationSelf-Test and Adaptation for Random Variations in Reliability
Self-Test and Adaptation for Random Variations in Reliability Kenneth M. Zick and John P. Hayes University of Michigan, Ann Arbor, MI USA August 31, 2010 Motivation Physical variation is increasing dramatically
More informationSlide Set 14. Design for Testability
Slide Set 14 Design for Testability Steve Wilton Dept. of ECE University of British Columbia stevew@ece.ubc.ca Slide Set 14, Page 1 Overview Wolf 4.8, 5.6, 5.7, 8.7 Up to this point in the class, we have
More informationDepartment of Electrical and Computer Engineering University of Wisconsin Madison. Fall Final Examination CLOSED BOOK
Department of Electrical and Computer Engineering University of Wisconsin Madison Fall 2014-2015 Final Examination CLOSED BOOK Kewal K. Saluja Date: December 14, 2014 Place: Room 3418 Engineering Hall
More informationOptimizing area of local routing network by reconfiguring look up tables (LUTs)
Vol.2, Issue.3, May-June 2012 pp-816-823 ISSN: 2249-6645 Optimizing area of local routing network by reconfiguring look up tables (LUTs) Sathyabhama.B 1 and S.Sudha 2 1 M.E-VLSI Design 2 Dept of ECE Easwari
More informationXC4000E and XC4000X Series. Field Programmable Gate Arrays. Low-Voltage Versions Available. XC4000E and XC4000X Series. Features
book 1 XC000E and XC000X Series Field Programmable Gate Arrays November 10, 1997 (Version 1.) 1 * Product Specification XC000E and XC000X Series Features Note: XC000 Series devices described in this data
More informationEECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS January 23, 2003 John Wawrzynek Spring 2003 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
More informationSequencing. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,
Sequencing ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2013 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Introduction Sequencing
More informationLow Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 29 Minimizing Switched Capacitance-III. (Refer
More informationDesign and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL
Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL Indira P. Dugganapally, Waleed K. Al-Assadi, Tejaswini Tammina and Scott Smith* Department of Electrical and Computer
More informationMore on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98
More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 98 Review: Bit Storage SR latch S (set) Q R (reset) Level-sensitive SR latch S S1 C R R1 Q D C S R D latch Q
More informationUNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 1. Briefly explain the stream lined method of converting binary to decimal number with example. 2. Give the Gray code for the binary number (111) 2. 3.
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More information12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009
12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 Project Overview This project was originally titled Fast Fourier Transform Unit, but due to space and time constraints, the
More informationOutline Synchronous Systems Introduction Field Programmable Gate Arrays (FPGAs) Introduction Review of combinational logic
EECS150 - igital esign Lecture 2 - Synchronous igital Systems and FPGAs January 24, 2013 John Wawrzynek Electrical Engineering and Computer Sciences University of California, Berkeley http://www-inst.eecs.berkeley.edu/~cs150
More information3/5/2017. A Register Stores a Set of Bits. ECE 120: Introduction to Computing. Add an Input to Control Changing a Register s Bits
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Registers A Register Stores a Set of Bits Most of our representations use sets
More informationCS 61C: Great Ideas in Computer Architecture
CS 6C: Great Ideas in Computer Architecture Combinational and Sequential Logic, Boolean Algebra Instructor: Alan Christopher 7/23/24 Summer 24 -- Lecture #8 Review of Last Lecture OpenMP as simple parallel
More informationESE (ESE534): Computer Organization. Last Time. Today. Last Time. Align Data / Balance Paths. Retiming in the Large
ESE680-002 (ESE534): Computer Organization Day 20: March 28, 2007 Retiming 2: Structures and Balance Last Time Saw how to formulate and automate retiming: start with network calculate minimum achievable
More informationTowards Trusted Devices in FPGA by Modeling Radiation Induced Errors
Digital Design and Dependability Research Group FIT, CTU in Prague Towards Trusted Devices in FPGA by Modeling Radiation Induced Errors Tomáš Vaňát, Jan Pospíšil, Jan Schmidt {vanattom, pospij17,schmidt}@fit.cvut.cz
More informationAn Application Specific Reconfigurable Architecture Diagnosis Fault in the LUT of Cluster Based FPGA
International Journal of Innovative Research in Electronics and Communications (IJIREC) Volume 2, Issue 5, July 2015, PP 1-7 ISSN 2349-4042 (Print) & ISSN 2349-4050 (Online) www.arcjournals.org An Application
More informationispmach 4000 Timing Model Design and Usage Guidelines
September 2001 Introduction Technical Note TN1004 When implementing a design into an ispmach 4000 family device, it is often critical to understand how the placement of the design will affect the timing.
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS150, Spring 2011
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS150, Spring 2011 Homework Assignment 2: Synchronous Digital Systems Review, FPGA
More informationAn Application Specific Reconfigurable Architecture Diagnosis Fault in the LUT of Cluster Based FPGA
An Application Specific Reconfigurable Architecture Diagnosis Fault in the LUT of Cluster Based FPGA Abstract: The increased circuit complexity of field programmable gate array (FPGA) poses a major challenge
More informationEECS 270 Midterm 1 Exam Closed book portion Winter 2017
EES 270 Midterm 1 Exam losed book portion Winter 2017 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. NOTES: 1. This part of
More informationWhere Are We Now? e.g., ADD $S0 $S1 $S2?? Computed by digital circuit. CSCI 402: Computer Architectures. Some basics of Logic Design (Appendix B)
Where Are We Now? Chapter 1: computer systems overview and computer performance Chapter 2: ISA (machine-spoken language), different formats, and various instructions Chapter 3: We will learn how those
More informationDesign for Testability
TDTS 01 Lecture 9 Design for Testability Zebo Peng Embedded Systems Laboratory IDA, Linköping University Lecture 9 The test problems Fault modeling Design for testability techniques Zebo Peng, IDA, LiTH
More informationnmos transistor Basics of VLSI Design and Test Solution: CMOS pmos transistor CMOS Inverter First-Order DC Analysis CMOS Inverter: Transient Response
nmos transistor asics of VLSI Design and Test If the gate is high, the switch is on If the gate is low, the switch is off Mohammad Tehranipoor Drain ECE495/695: Introduction to Hardware Security & Trust
More informationModeling and simulation of altera logic array block using quantum-dot cellular automata
The University of Toledo The University of Toledo Digital Repository Theses and Dissertations 2011 Modeling and simulation of altera logic array block using quantum-dot cellular automata Rohan Kapkar The
More informationJin-Fu Li Advanced Reliable Systems (ARES) Laboratory. National Central University
Chapter 3 Basics of VLSI Testing (2) Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Testing Process Fault
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics
Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and
More informationEEC 118 Lecture #9: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #9: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Review: Static CMOS Logic Finish Static CMOS transient analysis Sequential
More informationMUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL
1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage 2. To serially shift a byte of data into a shift register, there must be (a) one click
More informationEECS 151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: N. Weaver & J. Wawrzynek. Lecture 2 EE141
EECS 151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: N. Weaver & J. Wawrzynek Lecture 2 Class Schedule - UPDATE Discussions: Friday 11am-12, 106 Moffit Library LAB A (ASIC): W
More informationIntegrated circuits/5 ASIC circuits
Integrated circuits/5 ASIC circuits Microelectronics and Technology Márta Rencz Department of Electron Devices 2002 1 Subjects Classification of Integrated Circuits ASIC cathegories 2 Classification of
More informationLecture 10: Programmable Logic
Lecture 10: Programmable Logic We ve spent the past couple of lectures going over some of the applications of digital logic And we can easily think of more useful things to do like having a 7-segment LED
More informationDay 21: Retiming Requirements. ESE534: Computer Organization. Relative Sizes. Today. State. State Size
ESE534: Computer Organization Day 22: November 16, 2016 Retiming 1 Day 21: Retiming Requirements Retiming requirement depends on parallelism and performance Even with a given amount of parallelism Will
More informationAutomatic Transistor-Level Design and Layout Placement of FPGA Logic and Routing from an Architectural Specification
Automatic Transistor-Level Design and Layout Placement of FPGA Logic and Routing from an Architectural Specification by Ketan Padalia Supervisor: Jonathan Rose April 2001 Automatic Transistor-Level Design
More informationPrinciples of Computer Architecture. Appendix A: Digital Logic
A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationL14: Quiz Information and Final Project Kickoff. L14: Spring 2004 Introductory Digital Systems Laboratory
L14: Quiz Information and Final Project Kickoff 1 Quiz Quiz Review on Monday, March 29 by TAs 7:30 P.M. to 9:30 P.M. Room 34-101 Quiz will be Closed Book on March 31 st (during class time, Location, Walker
More informationVLSI Design: 3) Explain the various MOSFET Capacitances & their significance. 4) Draw a CMOS Inverter. Explain its transfer characteristics
1) Explain why & how a MOSFET works VLSI Design: 2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel
More informationDigital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
More informationEE292: Fundamentals of ECE
EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 23 121120 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Combinatorial Logic Sequential Logic 3 Combinatorial Logic Circuits
More informationSolution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
More informationESE534: Computer Organization. Today. Image Processing. Retiming Demand. Preclass 2. Preclass 2. Retiming Demand. Day 21: April 14, 2014 Retiming
ESE534: Computer Organization Today Retiming Demand Folded Computation Day 21: April 14, 2014 Retiming Logical Pipelining Physical Pipelining Retiming Supply Technology Structures Hierarchy 1 2 Image Processing
More informationIntroduction to CMOS VLSI Design (E158) Lecture 11: Decoders and Delay Estimation
Harris Introduction to CMOS VLSI Design (E158) Lecture 11: Decoders and Delay Estimation David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University
More informationDesigning for High Speed-Performance in CPLDs and FPGAs
Designing for High Speed-Performance in CPLDs and FPGAs Zeljko Zilic, Guy Lemieux, Kelvin Loveless, Stephen Brown, and Zvonko Vranesic Department of Electrical and Computer Engineering University of Toronto,
More informationEL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043
EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP Due 16.05. İLKER KALYONCU, 10043 1. INTRODUCTION: In this project we are going to design a CMOS positive edge triggered master-slave
More informationTesting Digital Systems II
Testing Digital Systems II Lecture 2: Design for Testability (I) structor: M. Tahoori Copyright 2010, M. Tahoori TDS II: Lecture 2 1 History During early years, design and test were separate The final
More informationIn-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs
In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs Harmish Rajeshkumar Modi Thesis submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment
More informationMicroprocessor Design
Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview
More informationPROGRAMMABLE ASIC LOGIC CELLS
ASICs...THE COURSE ( WEEK) PROGRAABLE ASIC LOGIC CELLS 5 Key concepts: basic logic cell multiplexer-based cell look-up table (LUT) programmable array logic (PAL) influence of programming technology timing
More information