5- Introduction Combinational Circuit The output levels at any instant of time are dependent on the levels present at the inputs at that time» Any prior input-level conditions have no effect on the present outputs because combinational logic circuits have no memory Most = Combinational circuits + Memory elements General digital system that combines combinational logic gates with memory device : Fig. 5-» The external outputs are a function of both its external inputs and the information stored in its memory elements The most important memory element = Flip-Flop F/F is made up of an assembly of logic gates : Feedback» Even though a logic gate, by itself, has no storage capability, several can be connected together in ways that permit information to be stored(refer to Fig. 5-7). Output State of F/F : Fig. 5-2 Normal output () : or = HIGH = Set Inverted output() : or = LOW = Clear = Reset F/F = Latch = Bistable multivibrator (Refer to Slide 5-28). F/F : Clock Edge Sensitive Latch : Level Sensitive
5-2 5- NAND Gate Latch NAND gate latch(or Latch) Fig. 5-3 참고 Normal rest Constructed from two NAND gates : Fig. 5-3 Setting the Latch Both cases ends up HIGH : Fig. 5-4 Clearing the Latch Both cases ends up LOW : Fig. 5-5 Simultaneous Setting and Clearing Set = Clear =» = = : Undesired condition Set = Clear =» No change NAND Latch Summary Fig. 5-6(a),(b) Normally High Input Set Clear Output No change = = Invalid Fig. 5-3 Fig. 5-4 Fig. 5-5 SET CLEAR SET CLEAR Fig. 5-3 2 possible resting state when SET=RESET= SET CLEAR SET CLEAR SET SET CLEAR Fig. 5-4 Pulsing SET input to CLEAR Fig. 5-5 Pulsing CLEAR input to
5-3 Alternate Representations : Fig. 5-7 Ex. 5-) Determine output in Fig. 5-8 Ex. 5-2) Switch debouncing circuit in Fig. 5-9 5-2 NOR gate Latch Resting Input = Ex. 5-4 SW Ex. 5-3) Determine output in Fig. 5- Ex. 5-4) What happen if the light beam is momentarily interrupted in Fig. 5-2 will remain HIGH and the alarm will remain ON even if phototransistor return to ON ( Set=, Clear= : no change) F/F State on Power-Up Set Clear Output No change = = Invalid Set Clear Output No change = = Invalid Fig. 5- (a) NOR gate latch, (b) truth table, (c) simplified block symbol When power is on, not possible to predict the starting state of a F/F s output Output depend on factors such as internal propagation delays, parasitic capacitance, and external loading. To start of in a particular state, activate SET/CLEAR input at the start of circuit. SET CLEAR * Inactive Stage(Resting ) NAND latch : S=C= NOR latch : S=C= S R Fig. 5-7 Alternate Representation * Invalid = =
5-4 5-3 Troubleshooting Case Study Ex. 5-5) Describe & analyze the circuit in Fig. 5-3 Ex. 5-6) What are the possible faults(refer to Tab. 5-) Possible faults(switch position A에서 Fault : =이여야함 )» Internal open at Z- : 이입력되지않음 SET=RESET=» Component failure in NAND gate Z» Internally shorted to ground at Z-3, Z-4, and Z2-2» Node externally shorted to ground 5-4 Digital Pulses Pulse A signal switches from a normal inactive state to the opposite (active) state, then the signal returns to its inactive state. Positive pulse Performs its intended function when it goes HIGH : Fig. 5-4(a) Negative pulse Performs its intended function when it goes LOW : Fig. 5-4(b) Rise time t r / Fall time t f The time it takes the voltage to change between % and 9% Refer to Fig. 5-4(a), (b)
5-5 Fig. 5-3 : Example 5-5 and 5-6
5-6 Leading edge The transition at the beginning of the pulse Trailing edge The transition at the end of the pulse Pulse width tw The time between the points when the leading and trailing edges are at 5% Ex. 5-7) Draw a scaled drawing of the RD pulse. : Fig. 5-5 5-5 Clock Signals and Clocked F/Fs Async/Synchronous System Asynchronous System : The output of logic circuits can change state any time Synchronous System : The exact times at which any output can change states are determined by a signal commonly called the clock» Synchronous circuits are easier to design and troubleshoot because the circuit outputs can change only at specific instants of time. Clock Signal = rectangular pulse train or square wave(fig. 5-6) Positive-Going Transition(PGT), Negative-Going Transition(NGT) The synchronizing action of the clock signals is accomplished through the use of clocked flip-flops
5-7
5-8 Clocked Flip-Flops : Fig. 5-7. Clocked FFs have a clock input(clk, CK, or CP)» In most clocked FFs, the CLK input is edge-triggered : NGT or PGT 2. Clocked FFs have one or more control inputs» The control inputs will have no effect on until the active clock transition occurs(=synchronous control inputs) 3. In summary,» The control inputs control the WHAT : Output state(data or ) will go to» The clock input determines the WHEN : actually triggers the change Setup and Hold Times : Fig. 5-8 Setup time(5-5 ns)» minimum time that control input must remain at constant value before the transition. Hold time( - ns)» minimum time that control input must not change after the positive transition 5-6 Clocked S-C F/F Clocked S-C F/F Set-Clear F/F Waveform analysis in Fig. 5-9 : positive going edge transition Fig. 5-8 5 % t s t h Positive clock transition Control Input Clock Input
5-9 The clock input = Trigger input Negative-going edge transition : Fig. 5-2 Internal circuitry of the edge-triggered S-C F/F Edge-triggered S-C F/F : Fig. 5-2». NAND Latch» 2. Pulse-steering : NAND gate에모두이입력되면 SET/CLEAR= 이되고=/» 3. Edge-detector : Fig. 5-22 5-7 Clocked J-K F/F Jack-King F/F Clocked J-K F/F : Fig. 5-23 Toggle Mode : J = K = (S-C F/F 에서는 Invalid) Negative-going edge transition : Fig. 5-24 Internal circuitry of the edge-triggered J-K F/F : Fig. 5-25 =, = 인상태에서 J=K=이입력되면 5-8 Clocked D F/F» NAND 의입력은모두 이고따라서출력은 이되고 =로 Toggle» NAND 2의입력은,, 이고따라서출력은 이되고 =으로 Toggle Clocked D F/F : Fig. 5-26 Data F/F Implementation of the D F/F : Fig. 5-27 Parallel Data Transfer : Fig. 5-28
5- PGT NGT
5- Fig. 5-22 2-5 ns
5-2 x
5-3 5-9 D Latch : Transparent Latch D Latch : Fig. 5-29 Edge detector is not used : EN(Enable) input 사용 Ex. 5-8) Determine waveform in Fig. 5-3 5- Asynchronous Inputs Asynchronous Inputs(= override inputs) Used to set the FF to the or clear the FF to the state at any time, regardless of the conditions at the other inputs Clocked J-K F/F with asynchronous inputs : Fig. 5-3 Designations for Asynchronous Inputs PRE(Preset), CLR(Clear) S D (Direct SET), R D (Direct RESET) Ex. 5-9) Determine the output in Fig. 5-32 D Latch is not Edge Triggered, (Level Triggered) Use the overbar to indicate the active LOW
5-4
5-5
5-6 5- IEEE/ANSI Symbols : deleted in th Ed. A single edge-triggered J-K flip-flop : Fig. 5-33(a) 74LS2 dual edge-triggered J-K flip-flop : Fig. 5-33(b) A single edge-triggered D flip-flop : Fig. 5-34(a) 74HC75 quad D flip-flop common clock and clear : Fig. 5-34(b) 5- F/F Timing Considerations Setup/Hold Time : slide # 5-8 Propagation Delays : Fig. 5-33 (Typ. MAX Few - ns) t PLH : Delay going from LOW to HIGH, t PHL : HIGH to LOW 5% CLK t PLH t PHL
5-7 Maximum Clock Frequency : f MAX (Typ. Max 2 to 35 MHz) Clock Pulse HIGH and LOW Times : Fig. 5-34(a) The minimum time duration that the CLK must remain LOW before it goes HIGH t W (L), and HIGH before it returns LOW t W (H) Asynchronous Active Pulse Width : Fig. 5-34(b) The minimum time duration that a PRESET or CLEAR input must be kept in its active state in order to reliably set or clear the FF CLK t W (L) for active-low asynchronous inputs Clock Transition Times Manufacturer usually do not list a maximum transition time requirement Generally less than 5 ns for TTL, and less than 2 ns for CMOS Actual ICs : Tab. 5-2(TTL : 7474, 74LS2, CMOS : 74C74, 74HC2) Ex. 5-) Determine the following from Tab. 5-2 (a) t PLH = 25 ns for 7474, (b) t PHL = 4 ns for 74HC2, (c) t W (L) for 74LS2, active-low CLR input, (d) 7474, Hold time is needed(non-zero hold time), (e) All F/F, Setup time is needed(no non-zero setup time)
5-8 5-2 Potential Timing Problem in FF Circuits Potential Timing Problem : Fig. 5-35 J2 input of 2 will be changing as it receives the same NGT( ). This could lead to an unpredictable response at 2 해결책 : t PHL must be greater than 2 s hold time requirement Hold time 이적다 = CLK 후에도 control input 을계속유지시킬필요없음 Fortunately, all modern edge-triggered FFs have hold time requirements that are 5 ns or less; most have t H = (clock transition 과동시에 control input 이바뀌어도상관이없다 ) For these FFs, situation like that in Fig. 5-35 will not be a problem 가정 : FF s hold time requirement is short enough to respond reliably The FF output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition» if we apply this rule to Fig. 5-35, J2 =, K2 = Ex. 5-) Determine the output in Fig. 5-36 Clock transition 의이전입력값을갖는다 - 현재그림은정상동작 - CLK 입력전에 = 이며, CLK 입력과동시에 J2 = 이고따라서 2 = CLK 입력과동시에 J2 에는 () 이유지되어야하지만 J = K = 에따라 Toggle 되어 CLK 입력과동시에곧바로 J2 = 이되어 J2 의 Hold time 을만족시킬수없다
5-9 t PHL must be greater than 2 s hold time requirement Fig. 5-35 5-3 FF Applications Unclocked FFs Switch debouncing(ex. 5-2), Event storage(ex. 5-4) Clocked FFs We will briefly introduce the more common applications in the following sections
5-2 5-4 FF Synchronization Asynchronous signal input FF Synchronization A human operator s actuating input switch at some random time A FF can be used to synchronize the effect of an asynchronous input Partial Pulse : Fig. 5-37 (Ex. 5-2)» The operator actuates or releases the switch are essentially random, This can produce partial clock pulses at output X A method for preventing the appearance of partial pulses : Fig. 5-38 (Ex. 5-2) 5-5 Detecting an Input Sequence Detecting an Input Sequence : Fig. 5-39 An output is to be activated only when the inputs are activated in a certain sequence» HIGH output only if A goes HIGH and then B goes HIGH some time later 5-6 Data Storage and Transfer Register A data(binary number, BCD number,..) are generally stored in groups of FFs called registers
5-2
5-22 Data Transfer The data transfer involves the transfer of data from one FF or register to another The logic value stored in FF A is transferred to FF B upon the NGT of the TRANSFER pulse Synchronous data transfer : Fig. 5-4 Asynchronous data transfer : Fig. 5-4 next slide» Transfer Enable = : PRE=CLR=, 통상적인 FF으로동작» Transfer Enable = : A= 이면 B=, A= 이면 B= Parallel Data Transfer : Fig. 5-42 The contents of X, X2, and X3 are transferred simultaneously into Y, Y2, and Y3(Upon application of the PGT of the TRANSFER pulse) Parallel transfer does not change the contents of source register 5-7 Serial Data Transfer : Shift Registers Shift Register : Fig. 5-43 next slide A group of FFs arranged so that the binary numbers stored in the FFs are shifted from one FF to the next for every clock pulse Hold Time Requirement In shift register, the FFs must have a very small or zero hold time requirement Sec. 5-2 Timing Problem 과동일
5-23 Enable Disable Asynchronous data transfer : Fig. 5-4
5-24 Shift Register : Fig. 5-43
5-25 Serial Transfer between Registers : Fig. 5-44 Ex. 5-3) The contents of each FF after sixth shift pulse in Fig. 5-44? The registers are filled up with zeros(zero inserted) Shift-Left Operation 역으로배치 (Shift 방향에따른장단점은없으며, 응용특성에따라선택 ) Parallel versus Serial Transfer Parallel transfer : Speed 여러개의 Transmission wire 필요» All of the information is transferred simultaneously upon the occurrence of a single transfer command pulse Serial transfer : economy and simplicity» The complete transfer of N bits requires N clock pulses 5-8 Frequency Division and Counting 3 bit binary counter : Fig. 5-45 The FFs change state(toggle) whenever the pulses are applied Each FF divides the frequency of its input by 2 Counting Operation : Fig. 5-46(State Table) State Transition Diagram : Fig. 5-47 Graphical representation of state table» Circle(state), Line(transition), I/O(input/output) N 개 FF 은 /2 N 까지분주가능 / clock
5-26 MOD Number MOD Number indicates the number of states» N Flip-flops = 2 N different state, and count up to 2 N - Ex. 5-4) What will be the state after 3 pulses( 현재는 ) in Fig. 5-45 Ex. 5-5) 6 Flip-flop arrangement of Fig. 5-45 5-9 Microcomputer Application Transfer binary data of internal register to external register X : Fig. 5-48 ) Place the binary number onto its data output lines 2) Place the proper address code on its address output lines 3) Generate the clock pulse CP(Write signal) Ex. 5-6) a) What is address decode logic? : b) address code = 일때 X =? : X will not change( 그대로 ) 5-2 Schmitt-Trigger Devices Schmitt-Trigger Inverter : Fig. 5-49 Schmitt-trigger type of input is designed to accept slow-change signals and produce an oscillationfree output 표시 : Fig. 5-49(b) STATE V T- V T+ VOLT
5-27 5-2 One-Shot (=Monostable Multivibrator) One-Shot uasi-stable State One-Shot : Fig. 5-5(a) ) Once triggered by trigger input(t), = Opposite state 2) remains for a fixed period of time t p (Determined by t p =.69RC) 3) After a time t p, the OS outputs return to their resting state( ) stable t p 보통 에서 Non-retriggerable One-Shot : Fig. 5-5(b) Retriggerable One-Shot : Fig. 5-5 Actual Devices : Fig. 5-52 742/22 :» Single/Dual non-retriggerable one-shot 7422/23 :» Single/Dual retriggerable one-shot Vcc * R INT : optional For output pulse width stability
5-28 5-22 Clock Generator Circuits Multivibrator Bi-stable multivibrator : Flip-flops have two stable state Mono-stable multivibrator : One-shots have one stable state( ) Astable = Free-running multivibrator : no stable state = uasi-stable State Schmitt-Trigger Oscillator : Fig. 5-53 555 Timer Used as an Astable Multivibrator : Fig. 5-54 Ex. 5-7) Calculate the frequency and the duty cycle of the 555 timer Ex. 5-8) Calculate RA and RB (less than 5%) Crystal-Controlled Clock Generators Output frequency = Crystal s resonant frequency Clock Generator Circuit : khz 8 MHz» Using TTL inverter : R = 3-5 Ohm, 최대 2 MHz» Using CMOS inverter : R = K Ohm, 최대 MHz 5-23 Troubleshooting FF circuits Open Inputs : Ex. 5-9 ( Fig. 5-55 ) K 가 Open 되어 J = K = 로 Toggle 됨 (TTL open = ) * R depends on the type of crystal used and its frequency (Graph 로제공됨 )
5-29 Shorted Outputs : Ex. 5-2 ( Fig. 5-56 ) Rule out D(Z2-2) 에 이입력되며, 따라서 (Z2-5) = 이어야정상 Possible Circuit Faults» Z2-5 or Z-4 is internally shorted to Vcc» Z2-5 or Z-4 is externally shorted to Vcc» Z2-4 is internally or externally shorted to GROUND(Preset : = )» Z2 internal failure In case of Z2 internal failure» ) Check Z2 s Vcc and GROUND : O.K.» 2) Unsolder Z2, and Check it s amplitude, frequency, pulse width, and transition times (by using oscilloscope) : O.K.» 3) Replace it with new one, but the new chip behaves in exactly the same way» 4) Finally he detects a solder bridge between pins 6 and 7 of Z2» 5) Remove the solder bridge and then the circuit functions correctly Explain how this fault produced the operation observed» The and outputs are internally cross-coupled so that the level on one will affect the other» A constant LOW at would keep a LOW at one input of NAND gate so that would have to stay HIGH regardless of the J or K 현재는 = Both outputs should be checked for faults, even those that are not connected to other devices SET CLEAR
5-3 Solder bridge
5-3 Clock Skew A clock signal arrives at the CLK inputs of different FFs at different times(propagation delay 가원인 ) The skew can cause a FF to go to a wrong state : Fig. 5-57» 2 는 CLOCK 에서 = 이입력되어계속 2= 이되어야함 ( 그러나그림에서는 CLOCK 2 이후에 2= 이되어오동작 ) 해결방법» Problems caused by clock skew can be eliminated by equalizing the delays(the active transition arrives at each FF at approximately the same time) 각각의 Clock Input 에서의 Propagation Delay 를계산
5-32
5-33 5-24. Sequential Circuits in PLDs Using Schematic Entry * Altera s uartus II development system software allows the designer the option of describing the desired circuit using schematics. uartus provides component libraries that contain flip-flop and latch devices that can be used to create the schematics. These libraries are named primitives(dff, jkff..), maxplus2(macrofunction), and megafunction(lpm=library of Parameterized Modules) The megafunction library contains various high-level modules that can be used to create logic designs(lpm_ff, LPM_LATCH, and LPM_SHIFTREG..) Exam. 5-2 : Compare the operation of a level-enabled D latch and edge-trigered D flip-flop D latch and D flip-flop uartus schematic : Fig. 5-58 D latch and D flip-flop simulation report : Fig. 5-59
5-34 Exam. 5-22: Construct a register that consists of four D flip-flop using the LPM_FF megafunction. Input signals for Exam 5-22 : Fig. 5-6 MegaWizard Manager set up dialogs for Exam 5-22 : Fig. 5-6 Schematic for a 4-bit register using an LPM_FF megafunction: Fig. 5-62 Functional simulation results for Exam 5-22 : Fig. 5-63
5-35 5-25. Sequential Circuits Using HDL Three input/output modes : Fig. 5-64 Behavioral description of an SR latch : Fig. 5-65 Exam. 5-23 NAND latch using AHDL : Fig. 5-66 NAND latch using VHDL : Fig. 5-67 D latch : Fig. 5-29 AHDL : variable q LATCH primitive (connection: q.ena=enable, q.d=din)» Tab. 5-3 Altera primitive port identifiers VHDL : description (PROCESS) 5-26. Edge-Triggered Devices JK FF using AHDL : Fig. 5-68, Fig. 5-69 standard JK FF is a fundamental part of sequential logic circuits called a logic primitive.- Tab. 5-3. Input only : D 2. Output only : 3. Output with feedback : use logic primitives defined in library files to describe FF operation. JK FF using VHDL. Library component : Fig. 5-7 and Fig. 5-7 next slide 2. explicitly describe logic circuit operation in the code : Fig. 5-72 VARIABLE ff :JKFF;
5-36 Library Components ( VHDL only ). Graphic representation using a component : Fig. 5-7(a)» Used again and again (exactly what IC manufacturers do)» VHDL component declaration : Fig. 5-7(b) 2. JK FF component from the library in VHDL is used to create a circuit equivalent to the graphic design of Fig. 5-7(a) : Fig. 5-7 Library define : ieee std_logic and altera components Placing the following line at the top of your design file ( refer to Fig. 5-7 ). LIBRARY ieee; define std_logic USE ieee.std_logic_64.all LIBRARY altera; standard component USE altera.maxplus2.all Simulation of the JK FF : Fig. 5-73 Verifying Fig. 5-69 (AHDL) and Fig. 5-72 (VHDL). 5-27. HDL Circuits with Multiple Components MOD-8 ripple counter / 3 bits Binary Counter : Fig. 5-74 ( = Fig. 5-45 ) ADHL Ripple-up Counter : Fig. 5-75 VHDL Ripple-up Counter : Fig. 5-76 No library is used, new neg_jk component define, describe explicitly