Panel Discussion: EUVL HVM Insertion and Scaling Readiness and Challenges of EUV Mask Takashi Kamo Toshiba Corporation Semiconductor & Storage Products Company
Contents [1] Introduction [2] EUV Mask Defect (1) Defect Management for HVM Insertion - Quality Assurance of Repaired Absorber Pattern - Management of Multilayer Defects - Patterned Mask and Particle Inspection (2) EUV Mask Infrastructure Readiness [3] Challenges for Scaling (1) Scaling of Absorber Pattern (2) Scaling with High NA or Shorter Wavelength 2
More than Moore Lithography Challenges More Moore ArF IM Light Source EUVL NA0.33 Infra EUVL+DPT Performance & Economics NA>1~1.35 ArF DPT Cost ArF DPT*2 Tool Defect NIL(+DPT) ML2 Defect DSA Roll to Roll Imprint 3
Half pitch [nm] Scaling Road Map 40 35 30 25 20 15 10 5 0 2010 2012 2014 2016 2018 2020 2022 2024 Year of production DRAM metal MPU metal Flash gate Ref: ITRS 2011 Edition Table B Key Lithography-related Characteristics by Product 4
Current EUV Mask Structure and Challenges Defect Contamination Defect Particle /wo Pellicle Absorber Defect clear opaque Absorber Stack Capping Layer Embedded Particle Multilayer Defect Multilayer Defect (Phase Defect) Low Thermal Expansion Material (LTEM) Mask yield & defect inspection/review infrastructure is key challenges before HVM. Back-side Coating 5
QA of Repaired Absorber Pattern EUV-AIMS will not available at the early stage of HVM. 3D SEM + Litho. simulation is applied to bridge the gap. Top-down & tilted SEM images of mask pattern UR-7T (TOPCON) -5deg top-down +5deg 3D mask image Prediction of wafer image Lithography simulation - Max. image size; 8000x8000pixels -Max. acquisition area; 8x8um @1nm pixels - Image distortion; <0.2% -Tilt range; +5~-5 degrees & 4 scan rotations - Throughput; 70min/5points 6
Simulated Wafer Printability Result We predicted wafer printability of EB repaired absorber pattern with 3D- SEM and lithography simulation. -5deg tilt Top-down +5deg tilt 3D mask image Predicted wafer image Repaired pattern has different side wall angle and line edge roughness. Printability evaluation Base pattern ; 100nm Line / Space Area of 3D mask image ; 2000x2000nm @mask CD Def CD Ref Space All repaired results are in acceptable range. CD variation CD Def - CD Ref = x 100 CD Ref Actual wafer printability evaluation is on-going. 7
Mask Yield (Y) [%] Mask Yield (Y) [%] Mask Defect Yield vs Defect Counts Estimation from Poisson Distribution 100 Dependency on acceptable defect counts (Bright Field) 100 Dependency on pattern variation (Zero Defect Yield) 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 1 2 3 4 5 6 7 8 9 10 11 12 0 0 1 2 3 4 5 6 7 8 9 10 11 12 Mean Defect Counts (λ) [pcs/plate] Mean Defect Counts (λ) [pcs/plate] Blanks with small defect counts are required. 8
Challenges for Managing Multilayer Defect Blank Defect Map Redundancy Acceptable Area Redundancy NOT Acceptable Area OK NG, but might be OK if #defects are acceptable counts OK Challenges: NG if the defect is in redundancy NOT acceptable area multilayer defects : difficult to be identified by SEM/AFM after mask patterning - Identify the position of multilayer defect (position error << pattern half pitch) - Predict multilayer (phase) defect printability under the condition that EUV-AIMS is not available. 9
SEM image Blank defect examples identified by SEM (Mask pattern for hp3x-nm (after litho.)) Defect Position of BI corrected SEM image Defect Position Error of DUV BI Tool (3 rd Gen.) #1 #2 #3 #5 #6 #7 Defect position of BI corrected #9 #12 #18 # N1 # N2 # N3 Residual X (3σ) : 108 nm Defect position error of BI coordinates is smaller than the pattern hp. 10
Defect Defect Size [a.u.] [a.u.] Projection Defect Size to ML Absorber ML -3σ 0 +3σ Projection Defect Size to ML (Expectation Value) 3σ 3σ S( x) P( x) dx S(x): projection defect size to ML P(x): probability of defect location Defects at Redundancy Acceptable Area It is necessary to reduce defects further for HVM. Raw Value Raw Value Projection Size to ML These will NOT print because (a part of ) defect is located under absorber. 21 12 3 4 65 56 7 18 8 12 9 26 10 23 11 25 12 13 29 14 22 15 28 16 17 15 18 19 8 21 20 14 21 27 22 20 23 24 9 24 25 11 26 19 27 10 28 16 29 Defect ID (size: below main pattern s half pitch) The idea of projection defect size to multilayer avoids overestimating the number of potential killer defects. 11
Patterned Mask Inspection Tool NPI-7000 (NuFlare) Hirano, et al. (BACUS2010) 12
EBeyeM (EBARA) EB Inspection Areal illumination of PEM improves inspection throughput. 13
EB Inspection (Particle Inspection Mode) 14
absorber defect multilayer defect EUV Mask Infrastructure Readiness Mask QA Inspection Mitigation Inspection Repair hp 3x ~ hp 2x 3D SEM + Litho. Simulation DUV inspection Redundancy Absorber covering (for dark field mask) DUV inspection after litho. EB repair hp 1x EUV-AIMS Actinic inspection Redundancy Absorber covering EB inspection @EIDEC/Lasertec Compensation repair @EIDEC/EBARA Particle inspection ready EB inspection under developing 15
Absorber Pattern Generation Rinse Suction Developing Solution Suction Rinse EB writer : EBM8000 (NuFlare) Scanning-type Developer : PGSD Proximity-Gap-Suction-Development System (Tokyo Electron) Scan Dry Etching Equipment : ARES TM (Shibaura Mechatronics) http://www.nuflare.co.jp/ product/ebm.html 44nm (4x) L&S Slit and scan type development Narrow gap Suction slits for removing dissolution products Scan Mask Mask Stage PGSD Nozzle TaBO TaBN Ru 90(deg) CDU of 44nm (4x) L&S : 1.7nm (3sigma) Gap Sensor Iino, et al. (BACUS2010) Developing Area Cross-sectional view Gap Mask Extreme high uniformity of developing solution supply Nearly zero loading effect caused by dissolution products Etched absorber pattern has capability for scaling down to hp1x EUVL single exposure. 16
EUV Mask Structure for Scaling Current Absorber Stack Capping Layer Multilayer TaO/TaN based Ru Mo/Si 40~50 pairs needs fine tuning for high throughput needs optimization for high NA scaling Low Thermal Expansion Material (LTEM) Back-side Coating needs material change for shorter wavelength ±5ppb/ @ 19~25 CrN need further R&D 17
Readiness and Challenges of EUV Mask EUV masks for hp3x~2x (after litho.) /hp1x (after DP process) can be almost ready for HVM insertion. Mask CD of absorber pattern has capability for scaling down to hp1x EUV single exposure. Further R&D is necessary for EUV mask to scale with high NA / shorter wavelength. 18