EE207: Digital Systems I, Semester I 2003/2004 CHAPTER 3 -ii: Combinational Logic Design Design Procedure, Encoders/Decoders (Sections 3.4 3.6) Overview Design Procedure Code Converters Binary Decoders Expansion Circuit implementation Binary Encoders Priority Encoders (3.4-3.6) 2 (Sections 3.4-3.6) 1
Combinational Circuit Design Design of a combinational circuit is the development of a circuit from a description of its function. Starts with a problem specification and produces a logic diagram or set of boolean equations that represent the circuit. (3.4-3.6) 3 Design Procedure 1. Determine the required number of inputs and outputs and assign variables to them. 2. Derive the truth table that defines the required relationship between inputs and outputs. 3. Obtain and simplify the Boolean function (K- maps, algebraic manipulation, CAD tools, ). Consider any design constraints (area, delay, power, available libraries, etc). 4. Draw the logic diagram. 5. Verify the correctness of the design. (3.4-3.6) 4 (Sections 3.4-3.6) 2
Design Example Design a combinational circuit with 4 inputs that generates a 1 when the # of 1s equals the # of 0s. Use only 2-input NOR gates (3.4-3.6) 5 More Examples - Code Converters Code Converters transform/convert information from one code to another: BCD-to-Excess-3 Code Converter Useful in some cases for digital arithmetic BCD-to-Seven-Segment Segment Converter Used to display numeric info on 7 segment displays (3.4-3.6) 6 (Sections 3.4-3.6) 3
BCD-to-Excess-3 Code Converter Design a circuit that converts a binary- coded-decimal decimal (BCD) codeword to its corresponding excess-3 codeword. Excess-3 code: Given a decimal digit n,, its corresponding excess-3 codeword (n+3) 2 Example: n=5 n+3=8 1000 excess-3 n=0 n+3=3 0011 excess-3 We need 4 input variables (A,B,C,D) and 4 output functions W(A,B,C,D), X(A,B,C,D), Y(A,B,C,D), and Z(A,B,C,D). (3.4-3.6) 7 BCD-to-Excess-3 Converter (cont.) The truth table relating the input and output variables is shown below. Note that the outputs for inputs 1010 through 1111 are don't cares s (not shown here). (3.4-3.6) 8 (Sections 3.4-3.6) 4
Maps for BCD-to-Excess-3 Code Converter The K-maps for are constructed using the don't care terms (3.4-3.6) 9 BCD-to-Excess-3 Converter (cont.) (3.4-3.6) 10 (Sections 3.4-3.6) 5
Another Code Converter Example: BCD-to-Seven-Segment Segment Converter Seven-segment display: 7 LEDs (light emitting diodes), each one controlled by an input a 1 means on, 0 means off f Display digit 3? g b Set a, b, c, d, g to 1 Set e, f to 0 e c (3.4-3.6) 11 d BCD-to-Seven-Segment Segment Converter Input is a 4-bit BCD code 4 inputs (w, x, y, z). Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be displayed. a Example: Input: 0000 BCD Output: 1111110 (a=b=c=d=e=f=1, g=0) (3.4-3.6) 12 f e g d c b (Sections 3.4-3.6) 6
BCD-to-Seven-Segment Segment (cont.) Truth Table Digit wxyz abcdefg 0 0000 1111110 1 0001 0110000 2 0010 1101101 3 0011 1111001 4 0100 0110011 5 0101 1011011 6 0110 X011111 7 0111 11100X0?? Digit wxyz abcdefg 8 1000 1111111 9 1001 111X011 1010 XXXXXXX 1011 XXXXXXX 1100 XXXXXXX 1101 XXXXXXX 1110 XXXXXXX 1111 XXXXXXX (3.4-3.6) 13 Decoders A combinational circuit that converts binary information from n coded inputs to a maximum 2 n decoded outputs n-to- 2 n decoder n-to-m decoder, m 2 n Examples: BCD-to-7-segment decoder, where n=4 and m=7 (3.4-3.6) 14 (Sections 3.4-3.6) 7
Decoders (cont.) (3.4-3.6) 15 2-to-4 Decoder (3.4-3.6) 16 (Sections 3.4-3.6) 8
2-to-4 Active Low Decoder (3.4-3.6) 17 3-to-8 Decoder data address (3.4-3.6) 18 (Sections 3.4-3.6) 9
3-to-8 Decoder (cont.) Three inputs, A 0, A 1, A 2, are decoded into eight outputs, D 0 through D 7 Each output D i represents one of the minterms of the 3 input variables. D i = 1 when the binary number A 2 A 1 A 0 = i Shorthand: D i = m i The output variables are mutually exclusive; exactly one output has the value 1 at any time, and the other seven are 0. (3.4-3.6) 19 Implementing Boolean functions using decoders Any combinational circuit can be constructed using decoders and OR gates! Why? Here is an example: Implement a full adder circuit with a decoder and two OR gates. Recall full adder equations, and let X, Y, and Z be the inputs: S(X,Y,Z) = X+Y+Z = m(1,2,4,7) C (X,Y,Z) = m(3, 5, 6, 7). Since there are 3 inputs and a total of 8 minterms, we need a 3-to-8 decoder. (3.4-3.6) 20 (Sections 3.4-3.6) 10
Implementing a Binary Adder Using a Decoder S(X,Y,Z) = Σm(1,2,4,7) C(X,Y,Z) = Σm(3,5,6,7) (3.4-3.6) 21 Decoder Expansions Larger decoders can be constructed using a number of smaller ones. -> HIERARCHICAL design! Example: A 6-to-64 decoder can be designed using four 4-to-16 and one 2-to-4 decoders. How? (Hint: Use the 2-to-4 decoder to generate the enable signals to the four 4- to-16 decoders). (3.4-3.6) 22 (Sections 3.4-3.6) 11
3-to-8 decoder using two 2-to-4 decoders (3.4-3.6) 23 4-input tree decoder (3.4-3.6) 24 (Sections 3.4-3.6) 12
Encoders An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n input lines and n output lines. The output lines generate the binary equivalent of the input line whose value is 1. (3.4-3.6) 25 Encoders (cont.) (3.4-3.6) 26 (Sections 3.4-3.6) 13
Encoder Example Example: 8-to-3 binary encoder (octal-to-binary) A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7 (3.4-3.6) 27 Encoder Example (cont.) (3.4-3.6) 28 (Sections 3.4-3.6) 14
Simple Encoder Design Issues There are two ambiguities associated with the design of a simple encoder: 1. Only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination (for example, if D 3 and D 6 are 1 simultaneously, the output of the encoder will be 111. 2. An output with all 0's can be generated when all the inputs are 0's,or when D 0 is equal to 1. (3.4-3.6) 29 Priority Encoders Solves the ambiguities mentioned above. Multiple asserted inputs are allowed; one has priority over all others. Separate indication of no asserted inputs. (3.4-3.6) 30 (Sections 3.4-3.6) 15
Example: 4-to-2 Priority Encoder Truth Table (3.4-3.6) 31 4-to-2 Priority Encoder (cont.) The operation of the priority encoder is such that: If two or more inputs are equal to 1 at the same time, the input in the highest- numbered position will take precedence. A valid output indicator,, designated by V, is set to 1 only when one or more inputs are equal to 1. V = D 3 + D 2 + D 1 + D 0 by inspection. (3.4-3.6) 32 (Sections 3.4-3.6) 16
Example: 4-to-2 Priority Encoder K-Maps (3.4-3.6) 33 Example: 4-to-2 Priority Encoder Logic Diagram (3.4-3.6) 34 (Sections 3.4-3.6) 17
8-to-3 Priority Encoder (3.4-3.6) 35 A Matrix of switches = Keypad C0 C1 C2 C3 1 2 3 F 4 5 6 E 7 8 9 D 0 A B C R0 R1 R2 R3 (3.4-3.6) 36 (Sections 3.4-3.6) 18
Keypad Decoder IC - Encoder COL. 4-bit 1 2 3 F 4 5 6 E 7 8 9 D 0 A B C ROW 4-bit 4-bit Binary (encoded) (3.4-3.6) 37 Priority Interrupt Encoder Schematic Interrupting Devices Interrupt Encoder Microprocessor Device A Device B Req(1:0) Device C Device D IntRq (3.4-3.6) 38 (Sections 3.4-3.6) 19
Priority Encoding - Interrupt Requests Interrupting Device A B C D Req (1:0) IntRq 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 0 1 0 1 Exercise: Complete this table? (3.4-3.6) 39 (Sections 3.4-3.6) 20