Registers & ounters BME28 Logic ircuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com
Registers Registers are clocked sequential circuits A register is a group of flip-flops 2 Each flip-flop capable of storing one bit of information An n-bit register consists of n flip-flops capable of storing n bits of information besides flip-flops, a register usually contains combinational logic to perform some simple tasks In summary flip-flops to hold information combinational logic to control the state transition
ounters A counter is essentially a register that goes through a predetermined sequence of states ounting sequence FF FF Register FF n- ombinational logic 3
Uses of Registers and ounters Registers are useful for storing and manipulating information internal registers in microprocessors to manipulate data ounters are extensively used in control logic P (program counter) in microprocessors 4
4-bit Register R clear REG R 2 2 3 3 2 2 R F6E 6 6 [5:] [5:] clock clear 5 3 R 3 E LR
Verilog ode of F6E always @ (posedge or posedge LR) begin if (LR) <= 4 b; else begin if (E) <= ; end end
Register with Parallel Load Load R R 2 R 2 3 clock 7 clear R 3
Register Transfer /2 load n R R 2 R 2 R clock clock R load 8 R 2
Register Transfer 2/2 n-bit adder n n load R R 2 clock R R + R 2 9
Shift Registers A register capable of shifting its content in one or both directions Flip-flops in cascade serial input SI SO serial output clock The current of n-bit shift register state can be transferred in n clock cycles
Serial Mode A digital system is said to operate in serial mode when information is transferred and manipulated one bit a time. SI SO SI SO shift register A shift register B clock shift control clock shift control clk clk clk T T 2 T 3 T 4
B A Serial Transfer Suppose we have two 4-bit shift registers Timing pulse Shift register A Shift register B initial value After T After T 2 After T 3 After T 4 clock shift control A clk B clk clk 2 T T 2 T 3 T 4 shift control clock
Serial Addition In digital computers, operations are usually executed in parallel, since it is faster Serial mode is sometimes preferred since it requires less equipment serial output clock shift control SI shift register A SO a b _in FA S serial input SI shift register B SO 3 clear
Example: Serial Addition A and B are 2-bit shift registers clock shift control SR-A SR-B _in 4
Universal Shift Register apabilities:. A clear control to set the register to. 2. A clock input 3. A shift-right control 4. A shift-left control 5. n input lines & a parallel-load control 6. n parallel output lines 5
4-Bit Universal Shift Register parallel outputs A 3 A 2 A A clear clk s s 3 4 MUX 2 3 4 MUX 2 3 4 MUX 2 3 4 MUX 2 serial input for shift-right serial input for shift-left 6 parallel inputs
Verilog ode v // Behavioral description of a 4-bit universal shift register // Fig. 6.7 and Table 6.3 module Shift_Register_4_beh ( // V2, 25 output reg [3: ] A_par, // Register output input [3: ] I_par, // Parallel input input s, s, // Select inputs MSB_in, LSB_in, // Serial inputs LK, lear_b // lock and lear always @ ( posedge LK, negedge lear_b) // V2, 25 if (lear_b == ) A_par <= 4 b; else case ({s, s}) 2'b: A_par <= A_par; // No change 2'b: A_par <= {MSB_in, A_par[3: ]}; // Shift right 2'b: A_par <= {A_par[2: ], LSB_in}; // Shift left endcase endmodule 2'b: A_par <= I_par; // Parallel load of input 7
Verilog ode v2 // Behavioral description of a 4-bit universal shift register // Fig. 6.7 and Table 6.3 module Shift_Register_4_beh ( // V2, 25 output reg [3: ] A_par, // Register output input [3: ] I_par, // Parallel input input s, s, // Select inputs MSB_in, LSB_in, // Serial inputs LK, lear_b // lock and lear always @ ( posedge LK, negedge lear_b) // V2, 25 if (lear_b == ) A_par <= 4 b; else case ({s, s}) // 2'b: A_par <= A_par; // No change 2'b: A_par <= {MSB_in, A_par [3: ]}; // Shift right 2'b: A_par <= {A_par [2: ], LSB_in}; // Shift left 2'b: A_par <= I_par; // Parallel load of input endcase endmodule 8
Universal Shift Register Mode ontrol s s Register operation No change Shift right Shift left Parallel load 9
ounters registers that go through a prescribed sequence of states upon the application of input pulses 2 input pulses are usually clock pulses Example: n-bit binary counter count in binary from to 2 n - lassification. Synchronous counters flip-flops receive the same common clock as the pulse 2. Ripple counters flip-flop output transition serves as the pulse to trigger other flip-flops
3-bit binary ripple counter Binary Ripple ounter 2 3 4 5 6 7 Idea: to connect the output of one flip-flop to the input of the next high-order flipflop We need complementing flip-flops We can use T flip-flops to obtain complementing flip-flops or JK flip-flops with its inputs are tied together or flip-flops with complement output connected to the input. 2
4-bit Binary Ripple ounter count T R A 2 count R A 3 T R A 4 5 6 R A 7 T R A 2 8 9 R A 2 logic- 22 clear T R A 3 2 3 4 5 clear R A 3
4-bit Binary Ripple ounter count T R A T A R T A 2 R logic- T A 3 23 clear R
Synchronous ounters There is a common clock that triggers all flip-flops simultaneously If T = or J = K = the flip-flop does not change state. If T = or J = K = the flip-flop does change state. esign procedure is so simple no need for going through sequential logic design process A is always complemented A is complemented when A = A 2 is complemented when A = and A = so on 24 2 3 4 5 6 7
4-bit Binary Synchronous ounter ount_enable J K A J K A Polarity of the clock is not essential J K A 2 25 clock J K A 3 to next stage
Timing of Synchronous ounters clock A A A 2 A 3 26
Timing of Ripple ounters clock A A A 2 A 3 27 27
Up-own Binary ounter When counting downward the least significant bit is always complemented (with each clock pulse) A bit in any other position is complemented if all lower significant bits are equal to. For example: Next state: For example: Next state: 28 7 6 5 4 3 2
Up-own Binary ounter up down T A T A T A 2 The circuit 29 clock
count load Binary ounter with Parallel Load J K A J K A 2 J K A 2 clock carry output clear 3
Binary ounter with Parallel Load Function Table clear clock load ount Function X X X clear to X load inputs count up no change 3
Other ounters Ring ounter A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others are cleared. shift right T T T 2 T 3 initial value Usage Timing signals control the sequence of operations in a digital system 32
Ring ounter Sequence of timing signals clock T T T 2 T 3 33
Ring ounter To generate 2 n timing signals, we need a shift register with? flip-flops or, we can construct the ring counter with a binary counter and a decoder count T T T 2 T 3 2x4 decoder 2-bit counter ost: 2 flip-flops 2-to-4 line decoder ost in general case: n flip-flops n-to-2 n line decoder 2 n n-input AN gates n NOT gates 34
Johnson ounter A k-bit ring counter can generate k distinguishable states The number of states can be doubled if the shift register is connected as a switch-tail ring counter X Y Z T X Y Z T clock 35
Johnson ounter ount sequence and required decoding sequence number Flip-flop outputs X Y Z T Output S = X T 2 S = XY 3 S 2 = YZ 4 S 3 = ZT 5 S 4 = XT 6 7 S 5 = X Y S 6 = Y Z 8 S 7 = Z T 36
Johnson ounter ecoding circuit S S S 2 S 3 S 4 S 5 S 6 S 7 X Y Z T clock 37
Unused States in ounters 4-bit Johnson counter 38
orrection 39
4 Johnson ounter Next State Present State T Z Y X T Z Y X
K-Maps ZT XY X(t+) = T ZT XY ZT XY Y(t+) = XY + XZ + XT ZT XY 4 Z(t+) = Y T(t+) = Z
Unused States in ounters Remedy X(t+) = T Z(t+) = Y Y(t+) = XY + XZ + XT T(t+) = Z Y = X(Y+Z+T ) X Y Z T clock 42