SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT OF ECE COURSE PLAN Course Code : EC0205 Course Title : DIGITAL SYSTEMS Semester : III Course Time : JULY NOVEMBER 2011 Location : S.R.M.E.C Faculty Details Sec. Name Office Class hour Mail id A NS-2 Day1-1 st hr, Day2-3 rd hr, Day5-1 st & 2 nd hr B Mr. J. Selvakumar TP12S8 Day1-4 th Hr, Day3-6 th & 7 th hr, Day5-1 st selvakumarj@ktr.srmuniv.ac.in C Ms. Sabitha Gauni Day1-3 rd hr, Day2-5& 6 th hr, TP1103A Day3-1 st hr sabithagauni@ktr.srmuniv.ac.in D Ms.S.Kayalvizhi TP903A Day1-6 th &7 th, Day4-2 nd hr, Day5-1 st hr, kayalvizhis@ktr.srmuniv.ac.in E NS-8 Day1-2 nd & 3 rd hr, Day2-1 st hr, Day3-5 th hr F Ms.P.Radhika TP12S6 Day3-3 rd & 4 th, Day4-1 st, Day2-5 th hr radhikap@ktr.srmuniv.ac.in Required Text Books: 1. Morris Mano. M, "", Pearson education, Third Edition 2002 2. Ronald J. Tocci, "Digital System Principles and Applications", PHI, Sixth Edition, 1997 3. Floyd, "Digital Fundamentals", Universal Book Stall, New Delhi,1986 4. Morris Mano. M, "", PHI, Third Edition 5. Ronald J. Tocci, "Digital System Principles and Applications", Pearson education 9th edition Web Resources : www.freebookcentre.net www.cse.iitd.ernet.in www.circuit- magic.com www.utwired.engr.utexas www.books.google Prerequisite : GE0106 s : 1. To understand concepts of combinational and sequential circuits. 2. Analyze synchronous and asynchronous logic circuits. 3. Understand concepts of memory, programmable logic and digital integrated circuits. Page 1 of 8
Assessment Details Cycle Test I : 10 Marks Surprise Test I : 5 Marks Cycle Test II : 10 Marks Surprise Test II : 5 Marks Attendance : 5 Marks Model Exam : 15 Marks Test Schedule S. DATE TEST PORTIONS DURATION 1 1 rd week of Aug 11 Cycle Test-1 1 to 17 2 Periods 2 3 rd week of Sep 11 Cycle Test-2 18 to 29 2 Periods 3 4 th week of Oct 11 Model Test 1 to 45 3 Hrs Outcomes Students who have successfully completed this course 1. To understand concepts of combinational and sequential circuits. 2. Analyze synchronous and asynchronous logic circuits. 3. Understand concepts of memory, programmable logic and digital integrated circuits. Program outcome identify, formulate and design and conduct, analyze and interpret data Page 2 of 8
Detailed Plan NUMBER SYSTEMS - BOOLEAN ALGEBRA AND LOGIC GATES Number Systems - Boolean algebra - Canonical and standard forms. Digital logic gates - Integrated circuits. Map method - four and five variable map methods -Products of Sums Simplification - Don't care conditions. Quine -McClucskey Method. 1. Number Systems- Chapter 1 Binary, Decimal, Octal, Hexadecimal & 1-13 conversion from system to other 2. Boolean algebra- Basic laws and postulate with proof 3. Canonical and standard forms POS and SOP with problems 4. Digital logic gates, Integrated circuits. 5. Map method four and five variable K- map methods 6. K-Map method four and five variable map methods 7. Sum of Product and Products of Sum Simplification 8. Don t care conditions with K-map 9. Quine -McClusky Method-problems with don t care conditions to be discussed 36-44 44-51 53-61 65-76 65-76 76-79 80-82 80-82 1.To understand concepts of combinational and sequential circuits. Page 3 of 8
GATE LEVEL MINIMIZATION & COMBINATIONAL LOGIC Two level implementation - NAND & NOR Implementations - EXOR Functions. Combinational Circuits - Analysis and design procedure - Binary adder - Subtractor - Decimal Adder - Binary Multiplier - Magnitude Comparator - Decoders - Encoders - Multiplexers. 10 Two level Chapter 3 implementation 82-84 11 NAND & NOR Implementations and EXOR Functions 12 Combinational Circuits : Introduction & Binary Adder 13 Binary Adder- 1-bit adder and 4-bit ripple carry adder 14 Subtractor Implementation of Half & Full Subtractor 15 Decimal Adder and Binary Multiplier 16 Magnitude Comparator 4-bit magnitude comparator 17 Decoders and Encoders namely 3:8 decoder and 8:3 Encoder and Priority encoder 18 Multiplexers & demultipliers- Boolean function Mux s, combinational logic implementation using basic mux s Chapter 3 85-99 111-115 119-125 126-128 129-132 133-134 134-141 141-145 1.To understand concepts of combinational and sequential circuits. d. Graduate will design a system, d. Graduate will design a system, Page 4 of 8
SYNCHRONOUS SEQUENTIAL LOGIC Sequential circuits - Latches - Flip-Flops - Analysis of Clocked Sequential Circuits - State Reduction and Assignment - Design Procedure. Registers - Shift Registers - Ripple counters - Synchronous Counters - Other counters. 19 Sequential circuits: Latches namely RS,D latch in detail with truth table 167-172 20 Flip-Flops brief description of RS and D FF with Truth & Excitation Table 172-174 21 Flip-Flops- brief description of JK and T FF with Truth & Excitation Table 175-179 22 Conversion technique from D FF to T FF, JK FF to T FF/D FF Analysis of Clocked 180-189 Sequential Circuits 23 State Reduction and Assignment 198-203 24 Design Procedure - explanation 25 Design Procedure implementation with an example 26 Registers and Shift Registers 203-207 208-211 Chapter 6 217-222 27 Ripple counters Chapter 6 28 Synchronous Counters 227-232 Chapter 6 232-239 To understand concepts of combinational and sequential circuits. Analyze synchronous and asynchronous logic circuits. d. Graduate will design a system, Page 5 of 8
29 Other counters: Synchronous/Asynchr onous counter with unused states, Ring Counter & Johnson Counter Chapter 6 239-244 d. Graduate will design a system, AYSYNCHRONUS SEQUENTIAL LOGIC AND MEMORY Introduction - Analysis Procedure - Circuit with Latches - Design Procedure - Reduction of State and Flow Tables - Race-Free state Assignment. Memory - Introduction - Random-Access Memory - Memory Decoding - Read only memory. 30 Asynchronous Chapter 9 Sequential Logic And Memory Introduction 342-344 31 Analysis Procedure and Circuit with Latches Chapter 9 352-360 32 Design Procedure Chapter 9 33 Reduction of State and Flow Tables and race free assignment 360-366 Chapter 9 367-373 34 Race free assignment Chapter 9 35 Memory Introduction Random-Access Memory 36 Memory Decoding 374-379 255-259 262-267 Analyze synchronous and asynchronous logic circuits. Understand concepts of memory, programmable logic and digital integrated circuits. component component component component component component component Page 6 of 8
37 Read only memory 270-275 component DIGITAL INTEGRATED CIRCUITS AND PROGRAMMABLE LOGIC Introduction - Special Characteristics - Bipolar-Transistor Characteristics - RTL and DTL Circuits - TTL - ECL - MOS - CMOS - CMOS Transmission Gate Circuits - Programmable Logic Array - Programmable Array Logic - Sequential Programmable Devices 38. Bipolar-Transistor Characteristics Chapter 10 400-407 39. RTL and DTL Circuits Chapter 10 40. NAND/NOR gate TTL logic with detailed description 41. NAND/NOR gate ECL, MOS and CMOS 408-410 Chapter 10 411-416 Chapter 10 420-426 Understand concepts of memory, programmable logic and digital integrated circuits 42. CMOS Transmission Gate Circuits-its advantages & disadvantages 43. Programmable Logic Array-. Boolean function PLA logic Chapter 10 427-430 276-280 Page 7 of 8
44. Programmable Array Logic - Boolean function PLA logic 45. Sequential Programmable Devices 280-283 283-287 Page 8 of 8