SLAC-TN-70-10 Boris Bertolucci May 1970 A DIGITAL TIME SEQUENCE GENERATOR ( GIUSEPPE ) Abstract A circuit, which starts at T = 0 with an input pulse and puts out 10 pulses which start at arbitrarily variable times Tistart and stop at adjustable time Ti stop is described in this report. It is more or less equivalent to 10 Gate Generators (GGZOO). Introduction During the course of high energy physics experiments, particular importance has been given to gate generators to perform the functions of gating input dis- criminators, delaying a pulse, lighting fiducials and Nixies, advancing film, etc. During the 1968 run of Experimental Group D 12 GG2OO s were used for operation with an incremental tape recorder, 5 camera-data boxes, quantameter and fiducials. The gate generators were needed to delay the pretrigger, generate a machine gate (before the event), generate a kill gate, enable the quantameter DVM, gen- erate gates for fiducials and Nixies, advancing frame counter and film, reset interface (DG102). Most of these functions were completely independent in time from the others. The circuit described here can be used as a replacement for 10 gate genera- tors (extendable to any number, depending on the program boards and the output circuits). pletely Principle Its main characteristic is the complete flexibility, each output being com- independent of all the others. of Operation Suppose a gated clock oscillates at some fixed frequency v (the period T = l/v), the nth pulse, the time t = nt. after the gate has been opened by a start pulse at to = 0, occurs at If the start pulse (to = 0) also sets a FF and the nth clock resets it, we will have an output pulse whose width is W = nt and w&h starts at to = 0. The reset pulse has a delay d = nt. -l-
, If we set the FF with the mth pulse and reset with the nth (where m and n are arbitrarily numbers with n > m) we have a very versatile gate generator having an output starting at tl = mt and ending at t2 = nt with a width W = (n - m)t. The important parts of this circuit are, therefore, the clock, which generates the time base T, and the Program Board, which permits one to arbitrarily program the delay and duration of the gate with respect to time to = 0, in other words the numbers m and n. Block Diagram (Fig. 1) A. start logic pulse in coincidence with a gate pulse enables the clock to oscillate at the frequency fixed by the Time Base switch (SW3). The clock pulses are counted by a 4 decade-scaler whose 4 x 10 outputs are sent to the Program Board (P. B. ) where they are programmed on the two parts (set and reset). The 10 set outputs from the P. B. set 10 flip-flops and the 10 reset reset the same FF. The outputs of the FF are the gate-outputs, thus allowing any wanted choice of delay and gate duration. The reset-outputs from the P. B. are the delayed- outputs. With the switch SW2 (mode) in the Auto position the cycle. Specifications : the last (tenth) reset stops INPUT: LO-GATE: HI- GATE : SELECT: L-OUTPUT: G-OUTPUT: INDICATOR LIGHTS: Start input pulse. Accepts NIM standard logic signals (-700 mv). Input impedance 50 ohms. Accepts NIM standard logic signals - Input impedance 50 ohms. Accepts signals > 6 volts. Input impedance 50 ohms. 3 positions switch. Selects LO, HI, or OFF Gate. Ten logic delayed outputs (-700 mv). Output impedance 50 ohms. Width at any clock frequency 40 nsec. Typical Tr = 4 nsec; Tf = 10 nsec. The logic delayed output starts at the end of the G-output. Ten Gate output of 10 volts on 50 ohms. Width = variable range between 1 psec and 10 sec. Delay from the start pulse between 1 psec and 10 sec. One each channel. 5V/60 ma bulb lights up when the G-outputs are on. -3-._I - _ t,... ---,,_,.. _
TIME BASE: Rotary 4 positions switch. Selects the operate frequency of the clock. The four ranges are as follows: Incremental Clock Scale Range Time Frequency 1.0 psec l.op - 10.0 msec 1 psec 1 MHz 10.0 psec 10.0~ - O.lsec 10 psec 100 KHz 0.1 msec 0.1 m- l. 0 set 100 psec 10 KHz 1.0 msec 1.0 m- 10.0 set 1 msec 1 KHz MODE: AUTO: automatic reset. At the end of the cycle a reset pulse gates the clock off and ends the cycle. The reset pulse occurs with the trailing edge of the 10th output. Therefore the 10th output must have the maximum delay. FREE RUNNING: no automatic reset occurs. The cycles repeat themselves one after another. To stop the operation the manual reset has to be used. MANUA.L: STA.RT: (pushbutton) starts the cycle of operation. RESET: (pushbutton) stops the cycle at any time and resets all the outputs to zero. PROGRAMBOARD:is a double 10 x 4 decade matrix. The top part sets the times of the beginning of the gate pulses (leading edges) and the bottom part the ends of the gate pulses (trailing edges). N.B.: It is not necessary to program all the 10 channels, but it is strictly necessary to program the 10th stopping time as the longest one because this gives the automatic reset of the circuits. Circuit Description A logic (NIM Standard) pulse at the input (IN) (Fig. 2) turns on Tl and drives T2 to saturation. The pulse at T2 is then a 5 volt (TTL compatible) positive pulse. Bl is a NAND Gate so the start (IN) pulse has to be in coincidence with a LO-GA.TE pulse (logic pulse) or a HI-GATE pulse (+lov) according to SW5- switch (SELECT). With SW5 in OFF position, no coincidence is needed. B2 works as a NOR, so we will have an outgoing pulse with either of the two inputs (MANUAL or N0RMA.L). The pulse from B2 (start pulse) defines the zero time to. It enables (Fig. 3) the gated clock through the flip-flop Cl-C2 and the Gate Al, and also -4-
becomes the first pulse that goes to the scaler through the NOR Gate C4. The FF Cl- C2 open the Gate Al and the NAND Gate C3. Al enables the clock AZ-A3 to oscillate with the frequency v fixed by the TIME BASE switch (SW3). The two clock wave-shapes (points 3 and 6) are ANDed in A4 and a train of narrow pulses is generated at time-interval T = l/v (see below). The train of pulses is counted Clock A2-3 I I I, Clock A3-6 / GA.TE A4-12 Clock Pulses A4-11 in the 4 decade scaler (Fig. 4), so as many as lo4 pulses can be counted. This means that times between 0 and 104T can be fixed. The 4 X 4 outputs of the BCD Decade Counter are decoded to decimal (Gl-G4) and the 4 X 10 outputs are connected to the SET and RESET P. B. matrices (Fig. 5). The top 4 matrices (Sl-S4) are used to set the gate-generators, and the bottom 4 (Rl-R4) to reset them. Programming is done with diode-pins. A 4-fold coincidence occurs on each horizontal line when programming that line. EJ: Suppose we wish to program the fifth output to have a gate pulse starting 50.5 msec after the start pulse to with a width 141.5 msec. The programming is as follows: First the Time Base switch has to be set on. 1 msec (because this is the precision required); 4 diode-pins will be put on channel No. 5 (horizontal line) of the Sl-S4 matrices to form the number 0505 from left (thousands) to right (units). This will set the FF at 505 X. 1 msec = 50.5 msec from the start pulse. On channel No. 5 of the Rl-R5 matrix 4 diode pins will form the number 1920 (1415 + 505 = 1920): this will reset the FF at 1920 X. 1 msec = 192 msec. The 20 output-lines from the program board drive 10 flip-flop (Fig. 6) H2 - H3; 12-13,... Q2 - Q3 whose outputs are amplified (Fig. 7a) to +lo volts on 500 to give the gate-pulse. The same outputs drive also 10 indicator lamps to show when the gate is on (Fig. 7b). The 10 output lines from the reset program board are also converted to NIM standard logic levels (Fig. 7c) to give the delayed logic outputs. -5-
START uf- -._. -_---_1-- I G-OUT s I L-OUT ;, 6, 192 msec The output of the 10th channel of the reset program board functions to reset automatically the circuit (Fig. 8). Automatic and manual reset are ORed in B3. The pulse out drives a one-shot multivibrator (D2-D3) whose output from D4 switches the FF Cl-C2 (Fig. 3) and gates the clock off, stopping the cycle. At the same time, I outputs from El, E2 and 22 reset the 4-qecade scaler (Fig. 4) and the 10 gate genera- tor (flip-flops H... Q) (Fig. 6). Resetting the H... Q flip-flops is not strictly neces- sary as long as the 10th channel reset is programmed as the latest in time. With reset switch SW2 (Fig. 3) in the free running position, the automatic reset resets only the scaler and the H... Q flip-flops will repeat synchronously until a manual reset is given. Conclusion but will not gate the clock; so the cycle The first generator of this type was built and tested successfully in the first K decay experiment in the Group D Streamer Chamber,, The unit is capable of replacing from 10 to 20 E.G. & G., GG200 Gate Generators in experiments in which a large number of channels is required. It has been suggested that the number of outputs per channel be increased from G and delay to G, E, logic and delay. This and other smaller modifications will be incorporated Acknowledgements into the next generator. I would like to thank Dr. A.. Odian whose suggestions and general help were very useful and gratefully appreciated, Mr. Ray Larsen and Dr. F. Villa for their discussions and encouragement and Mr. W. Knapp for his great help in packaging. - 6-
I DCD + DEC CONfE PT.FR 0 OFF -T- Fl6. I - Blorw Diabtat,,
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c L-Output (LC #2) 200 mv/cm 20 psec/cm