Desig Techiues of FPGA Base Rao Nuber Geerator Pog P. Chu a Robert E. Joes Departet of Electrical a Coputer Egieerig, Clevela State Uiversity, Clevela, Ohio 445 NASA Gle Research Ceter, Clevela, Ohio 44 ABSTRACT Rao ubers are reuire i a wie variety of applicatios. As igital systes becoe faster a eser, it is feasible, a freuetly ecessary, to ipleet rao uber geerators irectly i harware. I this paper, we escribe techiues suitable for harware ipleetatio, icluig oe-bit true rao uber geerator, oe-bit LFSR (Liear Feebac Shift Register) geerator, ultiplebit LFSR geerator, ultiple-bit leap-forwar LFSR geerator, a ultiple-bit lagge Fiboaci geerator. We also iscuss the beefit of each techiue a its circuit copleity, particularly for ipleetatio utilizig FPGA (Fiel Prograable Gate Array) evices. I. INTRODUCTION Rao ubers are reuire i a wie variety of applicatios, icluig ata ecryptio, circuit testig, syste siulatio a Mote Carlo etho. I the past, the rao uber geeratio was ostly oe by software. However, as igital systes becoe faster a eser, it is feasible, a freuetly ecessary, to ipleet the geerator irectly i harware. Although the software-base ethos are well uerstoo [] [4] [5] [7], they freuetly reuire cople arithetic operatios a thus are ot feasible to be costructe i harware. Ieally, the geerate rao ubers shoul be ucorrelate a satisfy ay statistical test for raoess. A geerator ca be either truly rao or pseuo rao. The forer ehibits true raoess a the value of uber is upreictable. The later oly appears to be rao. The seuece is actually base o specific atheatical algoriths a thus the patter is repetitive a preictable. However, if the cycle perio is very large, the seuece appears to be o-repetitive a rao. Although it is possible to ipleet a true rao uber geerator i harware, it is slow a relatively epesive. The ai focus of this paper is o pseuo rao uber geerators. For siplicity, we will rop the wor pseuo i our iscussio. This paper provies a overview o the ethos that are suitable for harware ipleetatio, outlies the basic esig a iscusses their relative beefits. I reaiig paper, sectio II iscusses the ipleetatio of a true, theral-oise base rao uber geerator; sectios III a IV escribe sigle-bit a ultiple-bit geerator base o LFSR; sectio V shows a special leap-forwar LFSR ipleetatio for ultiple-bit geerator; sectio VI iscusses a ore coplicate lagge Fiboaci approach; a last sectio suarizes the paper. II. TRUE RANDOM NUMBER GENERATOR True raoess ca be erive fro certai physical pheoea, such as the tie betwee tics fro a Geiger couter epose to raioactive aterials. I electroic circuit, theral oise is freuetly use as the source of raoess because of its well-ualifie spectral a statistical properties. A represetative ipleetatio [8] is show i Figure. I this circuit, the source of the oise is the theral oise of a precisio resistor, which is represete as V oise. It is aplifie by a low-oise aplifier a the passe to a high-spee coparator. The threshol of the coparator (V ref ) correspos to the ea voltage of the iput oise sigal. The output of the coparator is saple a latche to a register. The latche sigal is a oe-bit biary sigal that ehibits true raoess. The true rao uber geerator is fairly ivolve sice it ees to preserve a aplify the theral oise, a at the sae tie shiel all eteral isturbaces. It cosists of aily aalog copoets a caot be ipleete by pure igital circuitry. The ie-sigal ipleetatio sigificatly icreases the syste copleity. This ipleetatio is also relatively slow a caot atch the high-spee igital circuit. Oe ajor applicatio of the true rao uber is to geerate the iitial see for pseuo rao uber geerator. III. SINGLE-BIT RANDOM NUMBER GENERATOR USING LFSR A sigle bit rao uber geerator prouces a value of or. The ost efficiet ipleetatio is to use a LFSR (Liear Feebac Shift Register) []. It is base o the recurrece euatio: Chu Chu Voise = a a L a low oise ap Vref coparator saplig & latchig -bit output Figure. A True -bit Rao Nuber Geerator Here, i is the i th uber geerate, a i is a pre-eterie
costat that ca be either or, a a are AND operator XOR (e ) operator respectively. euatio iplies that a ew uber ( ) utilizig (,, L, ) through a uece of AND XOR operatios. geerate patter will repeat itself after a certai. ow as the perio of the erator. I a LFSR, the achievable perio is eterie by which is. I orer to achieve the aiu perio, a special set of a i. I these sets, ost ai s are, a oly two to four of the are. Thus, the actual recurrece euatio is fairly siple. Despite of its siplicity, the recurrece euatios are ifferet for ifferet values of. May tets, such as [] [], have tables that list the recurrece euatios ehaustively. Table i Figure lists the recurrece euatios for with values fro to 8. For eaple, whe is 4, the euatio becoes: = 4 Assue the iitial see (i.e.,,, 4 ) is. The rao uber seuece ca be obtaie by the euatio: Note that the patter repeats itself after 5 ubers. The step is to ipleet the recurrece euatio i harware. The ew value,, epes o previous values, L, a thus -bit registers are reuire to,, Recurrece euatio 4 4 5 5 6 6 7 7 8 4 8 Figure. Saple Recurrece Euatios store these values. After a ew value is geerate, the olest store value is o loger eee for future geeratio a ca be iscare to ae place for the ew value. This ca be oe by a -slot shift register, which shifts out the olest value a shifts i a ew value i every cloc cycle. I aitio to the register, few XOR gates are also reuire to perfor eclusive-or operatio. Let us use the previous eaple of =4 agai. We ee 4 -bit registers to store the reuire values. Let,, a be the outputs of registers, a _, _, _ a _ be their values. The Boolea euatios for these registers ca be writte as: = = = ipleetatio is show i Figure (the ychroous coectios are oitte for clarity). A LFSR rao uber geerator is a very efficiet -bit shift register a to its operatio is etreely fast. I soe FPGA evices, aize as shift registers a further reuce the LFSR ipleetatio has show ay ice statistical uber. Furtherore, sice the perio grows epoetially with the size of the register, large o-repetitive seueces ruig at GHz, the perio is ore tha 5 years. iitial see is eee The see correspos to the iitial coitio of the registers. It ca be ay state ecept for all cobiatio (i.e.,, which causes to be stuc at zero fo Oe way to fi the proble is to a a special circuit that s coitios a value accorigly. The circuit ow as e Bruij couter, cosists a. It to. euatios for a 4-bit e Bruij couter are -bit output Figure. 4-bit LFSR D5 Chu
= = = = ) ( ) ( The rao seuece ow has a etra a is show below (the ew is uerlie): Its bloc iagra is show i Figure 4. Note that the e Bruij couter estroys the liearity of the syste a the recurrece euatio ca o loger be applie for all i. statistical tests. This shoul ot coe to a surprise sice a ew rao uber eeps ost bits fro the ol uber a cotais oly -bit ew iforatio. To overcoe the correlatio proble, it is ecessary to replace all bits i the rao uber rather tha just oe bit. There are several ways to o it a they are iscusse i the Sigle LFSR Leap-forwar LFSR (8) (5) (8) () () () (5) () () (6) (5) (6) (7) () (9) (4) (5) (9) () (7) (4) () (4) () () (4) () () () () _ Figure 5. 4-bit Rao Seuece of fro Sigle-LFSR a Leap-forwar LFSR Methos subseuet subsectios. _ IV. MULTIPLE-BIT RANDOM NUMBER GENERATOR USING LFSR Soe applicatios reuire ore accuracy a ee ore tha a sigle-bit rao uber. Sice the ubers prouce by a sigle-bit LFSR rao uber geerator are ucorrelate, oe way to obtai a ultiple-bit rao uber is to accuulate several sigle-bit ubers. There are several techiues to achieve this a they are iscusse i below. A. Sigle-LFSR Metho -bit output Figure 4. 4-bit e Bruij Couter The Sigle-LFSR etho reuires oly oe LFSR. It utilizes the values store i shift register to for a ultiplebit uber. For eaple, if a 4-bit rao uber is eee, we ca use the output of register of the 4-bit LFSR show i Figure (i.e.,,, a ). The geerate 4- bit seuece is show i the left colu of Figure 5. Note that all possible 4-bit cobiatios, ecept for, appear i the seuece. Although this ipleetatio is siple, the geerate rao ubers are highly correlate a fail ay B. Sigle-LFSR with a Couter Metho This ipleetatio cosists of a sigle LFSR a a couter. This etho replaces ew bits oe at a tie. A - bit rao uber reuires shift operatios of a LFSR to for a ew uber. As log as is relatively prie to the perio of the LFSR, the -bit uber will cycle through all possible states. I orer to eep trac the uber of shift operatio, a aitioal oulo- coutig circuit is reuire. The couter will geerate a special eable sigal that is asserte oce every cloc cycles. The LFSR will operate as usual. However, its output is iterprete as vali oly whe the eable sigal of the couter is asserte. The isavatage of this approach, of course, is the operatio spee. Clearly, the rao uber geerator is slower by a factor. C. Parallel-LFSR etho Parallel-LFSR etho is a straightforwar etesio of the previous sigle-bit rao uber geerator etho. It utilizes copies of ietical oe-bit geerator harware to geerate bits cocurretly. The ajor avatage of this etho is the operatio spee, which is ietical to that of a sigle-bit geerator. However, this etho also reuires a large aout of harware. First, copies of LFSRs are reuire. Seco, each LFSR ust have a ifferet see i orer to avoi correlatio. Sice logic cells of ost FPGA chips oes ot cotais both reset a preset iputs, aitioal iitializatio circuit is reuire. Recall that the D5 Chu
origial LFSR ees oly few XOR gates. The iitializatio circuit ay sigificatly icrease the circuit copleity. Aother cocer of parallel LFSR etho is the poor utilizatio of FPGA s resource. FPGA evices are ae of a collectio of geeric logic cells, which orally cotai a prograable cobiatioal circuit plus oe or two registers. Sice LFSRs reuire little cobiatioal circuitry, logic cells are ot fully utilize. A better approach is to use the ebee SRAM, which will be iscusse i sectio VI. V. MULTIPLE-BIT LEAP-FORWARD LFSR Leap-forwar LFSR etho utilizes oly oe LFSR a shifts out several bits. However, ulie the couter etho of sectio IV, all shifts are perfore i oe cloc cycle; i.e., ultiple steps are oe i the recurrece euatio. This etho is base o the observatio that a LFSR is a liear syste a the register state ca be writte i vector forat: ( i + ) = A ( i) I this euatio, ( i +) a (i) are the cotet of shift register at (i+) th a i th steps, a A is the trasitio atri. After the LFSR avaces steps, the euatio becoes ( i + ) = A ( i + ) = A ( A ( i + )) = A ( i + ) = A ( i + ) = LL = A ( i) We ca calculate A a eterie the XOR structure accorigly. The ew circuit ca leap steps i oe cloc cycle. It still cosists the ietical shift register although the feebac cobiatioal circuitry becoes ore cople. The actual ipleetatio ca be best eostrate by a eaple. Let us use the 4-bit LFSR i Figure as a eaple. It ca be writte as ( i + ) = A ( i) where = a A = Assue that we ee a four-bit rao uber geerator a thus we have to avace 4 steps at a tie. The ew 4 trasitio atri, A, becoes: 4 A = For the purpose of circuit ipleetatio, the euatio ca be writte as = After perforig atri ultiplicatio, we ca erive the feebac euatio for each sigal: = = = = The correspoig bloc iagra is show i Figure 6 a the four-bit output rao seuece is show i the right colu of Figure 5. Leap-forwar LFSR etho achieves its goal by utilizig etra cobiatioal circuit istea of uplicate LFSRs. For sall, the cobiatioal circuit is ot very cople. It is ieal for FPGA evices sice it balaces register a cobiatioal circuitry a fully utilizes the resource of logic cells. However, for very large, the XOR structure grows very large a becoes the oiat factor. VI. MULTIPLE-BIT LAGGED FIBONNACI GENERATOR Lagge Fiboaci etho processes a -bit wor irectly. It is govere by a recurrece euatio: = where l > > l Figure 6. 4-bit Leap-forwar LFSR I this euatio,, l a are all -bit wors, a represet the values at th, (-l) th a (-) th steps respectively. The sybol eotes a operator, which ca 4-bit output D5 4 Chu
be bit-wise XOR, aitio or ultiplicatio. I orer to obtai goo raoess properties a the largest possible perio, l, a have to be carefully chose. Tables of recurrece euatios are available i the literature [4] [7]. I geeral, cople operator perfors better tha siple operator oes sice it provies ore utatio aog the iiviual bits. Aitio is the ost cooly use operator a the correspoig ipleetatio has bee stuie i ore etail. Lagge Fiboaci etho is cosiere to be the best pseuo rao geerator [5] [6] [7]. Note that the parallel-lfsr etho ca be cosiere as a special case of the lagge Fiboaci etho. file ca be replace by a FIFO (first-i-first-out) buffer, which ca be ipleete by SRAM. The coceptual bloc iagra is show i Figure 8. The SRAM is orgaize as a circular ueue, with a poiter hea poitig to the olest eleet of the buffer (i.e., ). The other two locatios (i.e., l a) are costats relative to hea a ca be easily erive. I this ipleetatio, l a are rea fro SRAM a passe to circuit, a the result is LL l hea + L l+ l M l M To ipleet this etho, we ee l -bit registers to eorize l past values a a circuit to perfor operatio. The bloc iagra is show i Figure 7. This approach reuires a large uber of registers, which causes poor logic cell utilizatio i FPGA, as we iscusse i previous sectio. A better alterative is to utilize the ebee SRAM. Note that the access patter is very regular a thus the register -bit output Figure 7. Direct Ipleetatio of Lagge Fiboaci Geerator Figure 8. Coceptual SRAM Ipleetatio of Lagge Fiboaci Geerator writte to. I cloc cycle, hea oves ahea oe step (i.e., the value of hea is icrease by ) a the process is repeate. Note that the ol value of is overwritte by the ew value of l iscare a. The rough bloc iagra is show i Figure 9. Sice the structure of the ebee SRAM varies sigificatly for FPGA chips, the actual ipleetatio is evice epeet. Basically, the operatio ees two eory reas a oe eory write. It reuires three cycles for a sigle port SRAM a two cycles for a ual-port SRAM. I ay FPGA chips, SRAM is orgaize as a collectio of sall SRAM oules istribute over the logic blocs. It is possible to perfor two reas at ifferet SRAM oules at the sae tie a further reuce the uber of cycles. D5 5 Chu
+ ata aress SRAM l hea +(l-) +l aress of aress of aress of l Figure 9. Bloc Diagra of SRAM-Base Lagge Fiboaci Geerator []. P. Alfe, Efficiet Shift Registers, LFSR Couters, a Log Pseuo-Rao Seuece Geerators, Xili Applicatio Note, 995. []. P. H. Barell, W. H. McAey a J. Savir, Buil-i Test for VLSI: Pseuo-rao Techiues, Joh Wiley a Sos, 987. []. F. Jaes, A Review of Pseuo-rao Nuber Geerators, Coputer Physics Couicatios 6, 99. [4]. D.E. Kuth, The Art of Coputer Prograig Vol. : Seiuerical Methos ( eitio), Aiso-Wesley, Reaig, Mass., 98. [5]. P. L'Ecuyer, Rao Nubers for Siulatio, Co. ACM :, 99. [6]. P. L'Ecuyer, Efficiet a Portable Cobie Rao Nuber Geerators, Co. ACM :6, 988. [7]. G.A. Marsaglia, A Curret View of Rao Nuber Geerators, Coputatioal Sciece a Statistics: The Iterface, e. L. Balliar, Elsevier, Astera, 985. [8]. Quatu Worl Corporatio, QNG Moel JKP True Rao Nuber Geerator Users Maual, 998 I FPGA ipleetatio, aitio is preferre for the operator sice it provies proper perutatio betwee iiviual bits a aitio circuit ca be efficietly sythesize i ost evices. Oe other cocer is the iitializatio of lagge Fiboaci etho, which reuires l - bit wie sees. Freuetly, it is oe by usig a sall oe-bit LFSR geerator to fill the eory urig the syste iitializatio. VII. SUMMARY We have eaie several eig techiues for harware rao uber geerators a their feasibility for FPGA evices. For a sigle-bit rao uber geerator, LFSR is the ost effective etho. Whe ultiple bits are reuire, LFSR ca be etee by utilizig etra tie (as i couter etho) or etra circuitry (as i parallel LSFR etho a leap-forwar LSFR etho). For a sall uber of bits, leap-forwar LFSR etho is ieal sice it balaces the cobiatioal circuitry a register a thus fully utilizes the FPGA's resource. For a large uber of bits, lagge Fiboaci etho is preferre. Its circuit is ore cople a reuires ebee SRAM for efficiet ipleetatio. ACKNOWLEDGEMENTS Part of Dr. Pog Chu s wor was supporte by NASA Grat NAG-4. REFERENCES D5 6 Chu