Point System (for instructor and TA use only)

EEL 4744C - Drs. George and Gugel Spring Semester 2002 Final Exam NAME SS# Closed book and closed notes examination to be done in pencil. Calculators are permitted. All work and solutions are to be written on the exam where appropriate. Point System (for instructor and TA use only) Part A 20 points Part B 27 points Part C 15 points Part D 12 points Part E 10 points Part F 16 points TOTAL out of 100

Part A: Basic Concepts [20] Answer T or F. [15] 1) In full-duplex serial I/O, one pair of signal wires is used and data alternates in each direction. 2) In serial transmission with even parity sending the 8-bit data $AA, a 1 is appended for the parity bit. 3) The PIC is a family of RISC-based microcontrollers that focuses on low cost, small footprint, and ease of use for a variety of embedded applications. 4) Moore's Law dictates that the performance of new microprocessors has been increasing in density and thereby performance by a factor of 4 every 18 months.. 5) In analog I/O, signals much be sampled as least two times their highest frequency to avoid aliasing. 6) In successive approximation A/D, starting at the LSB each bit is set and tested versus the input signal. 7) An N-bit flash A/D provides fast conversion via the use of 2 N -1 comparators operating in parallel. 8) In analog I/O, transducers convert physical processes directly to digital signals. 9) When using the timer overflow in the 68HC12, the TOF flag is set once every 32K M-clock cycles. 10) In contrast to the timer overflow, output compare provides for more accurate timing delays. 11) With input capture in a timer system, the internal counter is latched based on an external event. 12) A pulse accumulator provides the capability for the counting of external pulses representing events. 13) In pulse-width modulation, the duty cycle is the ratio of the duty time versus the period time. 14) The SCI subsystem on the 68HC12 provides for high-speed synchronous serial I/O. 15) The A/D subsystem on our 68HC12 is limited to 10-bit resolution and conversion frequency 2MHz. Fill in the blank. [5] 1) A is a general type of digital device used for the transmission and reception of serial I/O in an asynchronous manner and involves parallel-to-serial and serial-to-parallel conversion. 2) In all events with the timer subsystem on the 68HC12, the flag is reset by software writing to the flag. 3) If the data rate is 9600 baud, what is the rate of ASCII characters that can be sent assuming 7 data bit, 1 parity bit, and 1 stop bit? 4) If an A/D converter has a conversion time of 100µs, what is the maximum frequency that can be converted without aliasing? 5) Given that the TCNT free-running counter register on the 68HC12 is mapped to $84, give an appropriate instruction to read the value of TCNT and store in a data register. 2

Part B: Memory Cycles and Port Expansion [27] You are given a microprocessor that has a 16-bit address bus, 16-bit data bus, address strobe, read/-write signal and data strobe. See the timing diagram below for more details. General-Purpose µp Timing Diagram +AS R/-W (read) R/-W (write) -DS AD15:0 A15:0 D15:0 Timings in nsecs 40 320 140 160 90 Signal Information +AS Address Strobe, indicates when address is valid on the multiplexed AD15:0 bus. R/-W Read/Write signal shown in both modes above. Data Strobe, indicates when address is valid on the multiplexed AD15:0 bus. On a read cycle, data is -DS read on the rising edge by the µp. On a write cycle, data is written out on the rising edge of DS. AD15:0 Multiplexed address (16 bits) and data (16 bits) bus. Assume: On a read cycle, data hold time required from rising edge of DS is zero. On a write cycle, data hold time from rising edge of DS is 20 nsec. B-1. Design a circuit below to de-multiplex the address and data buses for this microprocessor. An important part of this problem is selecting the appropriate type of digital device(s) to use in the design of this circuit. [6] 3

B-2. Assuming that we are using a CPLD with a 30 nsec propagation delay, how fast (i.e. what is the access time) must our memory (EPROM or SRAM) be such that we do not violate any critical timings shown earlier? [3] B-3. Given the devices below, show how to create an output port to drive 8 LEDs and an input port to read 8 switches. Assume memory-mapped I/O and that an address decoder exists to give you a port enable signals ~PE_IN for the input port and ~PE_OUT for the output port. Show the LED and switch circuits in your design and all connections to the microprocessor. Octal D-type flip-flop 74HC574 Octal bus transceiver; 3-state 74HC245 Vcc D7 D6 D5 D4 D3 D2 D1 D0 Gnd Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Vcc B7 B6 B5 B4 B3 B2 B1 B0 Gnd A7 A6 A5 A4 A3 A2 A1 A0 CP ~OE DIR ~OE Note1: CP is a rising-edge-triggered clock. Note2: ~OE is an active-low output enable. Note1: DIR controls the direction of data flow. If DIR = L then A B; if DIR = H then B A. Note2: ~OE is an active-low output enable used in either direction to enable or tri-state the data output. Show the Output Port below: [6] 4

Show the Input Port below: [6] B-4. Assuming that both ports will be mapped to $8000, show the decode equations below to place in a CPLD. The decoding for the output port should be simplified by reduced-address decoding such that 256 addresses are mapped to the same port. By contrast, the input port should be fully decoded. Note: For simplicity, in your equations please refer to DS active as DS.L, R/ W as RW.H or RW.L, etc. $8000, Partial-Decoding Equation for the Output Port: [3] PE_OUT.L = $8000, Full-Decoding Equation for the Input Port: [3] PE_IN.L = 5

Part C: Timers Real-Time Interrupt [15] The US Navy has contracted you to use a 68HC12 to create a signal that will be used as a beacon for a lighthouse. The specifications are that you turn Bit-7 in Port P on (i.e. high) for 30 seconds +/- 0.1 sec and then off (i.e. low) for 30 seconds +/- 0.1 sec. Use the RTI in an interrupt-driven capacity to perform this function and assume that you are using the lab board you used this semester that has an 8MHz ceramic oscillator connected externally to your 68HC12 chip. C-1. Write the code to enable/configure your interrupt in a main routine below. Assume that this main routine will be placed in EPROM starting at $D000. You can write this code as two columns of instructions, where the second column is assumed to follow right after the first column. [5] C-2. Write the interrupt handler (ISR) below. Assume it will be placed in EPROM starting at $E000. [7] (more lines available on the next page) 6

C-3. Show the code necessary to set up the interrupt vector to your handler in the EPROM which we assume is mapped from $D000 to $FFFF in the 68HC12's address space. [3] Part D: Timer Input Capture [12] You are working with a team of engineers to produce a system that will display the heartbeat of a patient undergoing surgery. The heartbeat can range from 10-200 beats per second and a sensor has been created that outputs a TTL rising edge for every beat. Use the Input Capture mechanism in the 68HC12 to measure the time between rising edges and assume that the sensor's TTL output is connected to PT0. Additional Information: 1. Assume that the M-Clock is operating at 4MHz. 2. We are to set the prescalar for the TCNT register to it slowest update rate in this application. D-1. In pseudo-code format, describe what needs to be done in the main program for application initialization. You should use register names (i.e. TMSK2, TFLG1, TFLG2, etc.) in your description, and if you set a particular bit a certain way then you should indicate why it was done and if it was set high or low. [5] Initialize TC0 (Input Capture channel 0) interrupt vector to first address of input capture ISR. Set Bit-7 (TEN) high in TSCR to turn on the timer module. 7

D-2. In pseudo-code, detail what must be performed in the Input Capture ISR. Assume that you only have to calculate the time in periods that correspond to the M-clock divided by the maximum prescalar divisor and then write this value to $0900. Another engineer is working on a routine in the main program that will read this value and display the actual heartbeat number on an LCD. [7] 8

Part E: Asynchronous Serial Data I/O [10] We would like to connect our 68HC12 via its asynchronous serial port to a PC serial port. The PC has been set for 9600 baud, 1 even parity bit, 1 stop bit and 8 data bits. We need a program that, via polling, reads in a character and then sends it back out, repeatedly. E-1. First, write the data and SCI initialization section of this program. [5] E-2. Now, write the operating section of this program where the polling and serial I/O takes place. [5] 9

Part F: A/D and D/A Conversion [16] A microphone has been amplified such that its signal swings between +/-5V. We would like to digitize this signal and have found a family of A/Ds that will allow us to tie V low to -5V and V high to +5V. F-1. If the noise in our amplified microphone system has been found to be +/- 0.01V, what is the dynamic range of the system? [3] F-2. How many bits are required for the A/D to meet the above specifications and maintain +/- 1/2 LSB of resolution? [2] F-3. If we use 16 bits for the A/D, what is the voltage resolution for an A/D with V low and V high at -5V, +5V? [3] F-4. If the 16-bit A/D described in F-3 has 2.78V at its analog input, what is the expected digital value assuming the A/D is an unsigned converter? Note: A decimal answer is acceptable. [4] F-5. You now are given an 8-bit two's complement D/A converter and told that it is connected such that line-level signals are produced (+/- 1V). What is the voltage output value that corresponds to an input of $C0? [4] 10