Sequential Circuit esign: Part 1 esign of memory elements Static latches Pseudo-static latches ynamic latches Timing parameters Two-phase clocking Clocked inverters James Morizio 1
Sequential Logic FFs Out LOGIC t p,comb In 2 s torage mechanis ms pos itive feedback charge-bas ed James Morizio 2
Combinational logic Sequencing output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline clk clk clk clk in CL out CL CL Finite State Machine Pipeline James Morizio 3
Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. James Morizio 4
Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence James Morizio 5
Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger clk (latch) clk clk Latch Flop (flop) James Morizio 6
Flip-Flop: Timing efinitions t In t setup t hold ATA STABLE t Out t pff ATA STABLE t James Morizio 7
Maximum Clock Frequency FFs LOGIC t p,comb James Morizio 8
Latch esign Pass Transistor Latch Pros + Tiny + Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s James Morizio 9
Latch esign Transmission gate + No V t drop - Requires inverted clock James Morizio 10
Latch esign Inverting buffer X + Restoring + No backdriving + Fixes either Output noise sensitivity Or diffusion input Inverted output James Morizio 11
Latch esign Buffered input + Fixes diffusion input + Noninverting X James Morizio 12
Latch esign Buffered output + No backdriving X Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading James Morizio 13
Latch esign Tristate feedback + Static Backdriving risk X Static latches are now essential James Morizio 14
Latch esign atapath latch + Smaller, faster - unbuffered input X James Morizio 15
esign of Memory Elements C C C C Positive edge-triggered flip-flop Why use inverters on outputs? Skew Problem : may be delayed with respect to (both may be 1 at the same time) This is what happens- Eliminating/Reducing skew: in 1 Transmission gate acts a buffer, should have same C delay as inverter James Morizio 16
Latch design C C C Static latch Jamb latch Weak inverter James Morizio 17
Latch esign Variant of latch C C James Morizio 18
Flip-Flop esign Flip-flop is built as pair of back-to-back latches X X James Morizio 19
Enable Enable: ignore clock when en = 0 Mux: increase latch - delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en Latch 1 0 Latch Latch en en en Flop 1 0 en Flop Flop en James Morizio 20
Reset Force output low when reset asserted Synchronous vs. asynchronous Symbol Latch Flop reset reset Synchronous Reset Asynchronous Reset reset reset reset reset reset reset James Morizio 21
Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset set reset reset set James Morizio 22
ynamic Latches So far, all latches have been static-store state when clock is stopped but power is maintained ynamic latches reduce transistor count Eliminate feedback inverter and transmission gate Latch value stored on the capacitance of the input (gate capacitance) James Morizio 23
ynamic Latch and Flip-Flop ynamic latch C C ata stored as Charge on gate capacitance ynamic negative edge-triggered flip-flop C C ifficult to ensure reliable operation Similar to RAM Refresh cycles are required James Morizio 24
Charge-Based Storage Non-overlapping clocks Schematic diagram P s e udo -s tatic Latc h James Morizio 25
Master-Slave Flip-Flop A B Overlapping Clocks Can Caus e Race Conditions Undefined Signals To reduce skew: generate complement of clock within the cell Extra inverter per cell James Morizio 26
Two-Phase Clocking Inverting a single clock can lead to skew problems Employ two non-overlapping clocks for master and slave sections of a flip-flop Also, use two phases for alternating pipeline stages James Morizio 27
Two-Phase Clocking 1 C C 2 1 2 1 (t). 2 (t) = 0 1 =1, 2 = 0 1 =0, 2 = 1 James Morizio 28
2-phase non-overlapping clocks Pseudo-static flip-flop 1 2 2 1 1 2 t Important: Non-overlap time t must be kept small James Morizio 29
2-phase dynamic flip-flop 1 2 Input Sampled 1 2 Output Enable James Morizio 30
Use of p Leakers Flip-flop based on nmos pass gates 1 2 No need to route signals egraded voltage V -V t 1 2 Problem: Increased delay (extra inverter) pmos leaker transistors provide full-restored logic levels James Morizio 31
Clocked Inverters Similar to tristate buffer = 1, acts as inverter = 0, output = Z i1 i2 i3 Latch James Morizio 32
Flip-flop insensitive to clock overlap V V M2 M6 In M4 X M8 M3 C L1 M7 C L2 M1 M5 section section C 2 MOS flip-flop James Morizio 33
C 2 MOS avoids Race Conditions V V V V M2 M6 M2 M6 In X In 0 M4 0 X M8 1 M3 1 M7 M1 M5 M1 M5 (a) (1-1) overlap (b) (0-0) overlap James Morizio 34