The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning. Flip-Flops and Registers (Lecture #19)
Flip-Flops (continued)
SR Flip-Flop The SR Flip-Flop has three inputs Clock (Ck) --- denoted by the small arrowhead Set (S) and Reset (R) Similar to an SR Latch S = 1 sets the flip-flop (Q + = 1) R = 1 resets the flip-flop (Q + = 0) Like the D Flip-Flop, the Q output of an SR Flip-Flop only changes in response to an active clock edge. Positive edge-triggered Negative edge-triggered
SR Flip-Flop S R Q Q + 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 not 1 1 1 allowed } Q+ } } = Q store Q + = 0 reset Q + = 1 set positive edge-triggered SR Flip-Flop State change occurs after active Clock edge
SR Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock
SR Flip-Flop: Timing Diagram
JK Flip-Flop The JK Flip-Flop has three inputs Clock (Ck) --- denoted by the small arrowhead J and K Similar to the SR Flip-Flop J corresponds to S: J = 1 Q + = 1 K corresponds to R: K = 1 Q + = 0 Different from the SR Flip-Flop in that the input combination J = 1, K = 1 is allowed. J = K = 1 causes the Q output to toggle after an active clock edge.
JK Flip-Flop } Q+ } Q+ } Q+ } Q+ = Q store = 0 reset = 1 set = Q' toggle Characteristic Equation: Q + = J.Q' + K'.Q
JK Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock
JK Flip-Flop: Timing Diagram
T Flip-Flop The Toggle (T) Flip-Flop has two inputs Clock (Ck) --- denoted by the small arrowhead Toggle (T) The T input controls the state change when T = 0, the state does not change (Q + = Q) when T = 1, the state changes following an active clock edge (Q + = Q') T Flip-Flops are often used in the design of counters.
T Flip-Flop Characteristic Equation: Q + = T.Q' + T'.Q = T xor Q
T Flip-Flop: Timing Diagram
Building a T Flip-Flop
Asynchronous Control Signals
Asynchronous Control Signals: Timing Diagram
D FF with Clock Enable
Flip-Flops in VHDL
JK Flip-Flop architecture JKFF of JKFF_entity is signal Qint: std_logic; begin Q <= Qint; Qnot <= not (Qint); process (Clk) begin if Clk'event and Clk = '0' then FF Clk Qint <= (J and not (Qint)) or (not (K) and Qint); end if; end process; end architecture;
D FF with Asynchronous Inputs Clk process (Clk) begin if ClrN = '0' then Q <= 0; elsif PreN = '0' then Q <= 1; elsif Clk'event and Clk = '1' then Q <= D; end if; end process;
Registers
Registers Several D flip-flops may be grouped together with a common clock to form a register. Because each flip-flop can store one bit of information, a register with n D flip-flops can store n bits of information. A load signal can be ANDed with the clock to enable and disable loading the registers. A better approach is to use registers with clock enables if they are available.
Register: 4 bits
Data Transfer between Registers Data transfer between registers is a common operation in computer (i.e. digital) systems. Multiple registers can be interconnected using tri-state buffers. Data can be transferred between two registers by enabling the proper tri-state buffer.
Data Transfer between Registers
Register with Tri-state Output
Data Transfer using Tri-state Bus
Shift Register shift register is a register in which binary data can be stored nd shifted either left or right. The data is shifted according to he applied shift signal; often there is a left shift signal and a ight shift signal. shift register must be constructed using flip-flops (i.e. edgeriggered devices); it cannot be constructed using latches or ated-latches (i.e. level-sensitive devices).
Shift Register: 4 bits
Shift Register (4 bits): Timing Diagram
8-bit SI SO Shift Register
4-bit PI PO Shift Register
-bit PI PO Shift Register: Operation
Registers in VHDL
4-bit Shift-Right Register process (Clock) begin if (Clk'event and Clk = '1') and Shift = '1' then Q3 <= SI after 8 ns; Q2 <= Q3 after 8 ns; Q1 <= Q2 after 8 ns; Q0 <= Q1 after 8 ns; SO <= Q0 after 8 ns; end if; end process;
Parallel Adder with Accumulator
Parallel Adder with Accumulator In computer circuits, it is frequently desirable to store one number in a register (called an accumulator) and add a second number to it, leaving the result stored in the register.
n-bit Parallel Adder with Accumulator
Loading the Accumulator Before addition in the previous circuit can take place, the accumulator must be loaded with X. This can be accomplished in several ways. The easiest way is to first clear the accumulator using the asynchronous clear inputs on the flip-flops, and then put the X data on the Y inputs to the adder and add the accumulator in the normal way. Alternatively, we could add multiplexers at the accumulator inputs so that we could select either the Y input data or the adder output to load into the accumulator.
Adder Cell with Multiplexer
Questions?