D.2. Encoders Often we use diverse peripheral devices such as switches, numeric keypads and more in order to interface the analog world with the digital one and, along with the usage of these devices, we are facing with the necessity of converting from familiar numbers, alphabetic characters or symbols to a coded format such as BCD or binary. Therefore, our next pits stop is at digital encoders. a) b) c) Fig. no. 7 Example of peripheral devices used to interface with digital systems (www.diytrade.com) a) switches, b) rotary switches, c) numeric keypads A digital encoder, one of the classics of combinational logic circuitry, takes all its data inputs one at a time and then converts them into a single encoded output (i.e. the binary equivalent of the input line whose value is equal to 1). One of the main disadvantages of standard digital encoders (i.e. those designed in a simplistic manner, with only the logical sum of terms) is that they can generate the wrong output code (i.e. unpredictable or rather not the one we expect it to be) when two or more inputs are simultaneous activated. This ambiguity is solved if a priority function is included in the design of the encoder so that only one input (i.e. the one having highest priority) is encoded, no matter how many inputs are active at a given point of time. In the following we ll proceed to the designing of our own priority encoder (e.g. a 4-bit priority encoder, also called 4:2 or 4 to 2 PE), starting as usual with the truth table from which, by means of VK maps, we can derive the minimized form of each output bit, as shown in Fig. no. 8. EI In_0 In_1 In_2 In_3 O_1 O_0 EO 1 0 0 0 0 0 0 0 0 1 0 0 0 X 1 0 0 X X 1 0 X X X 1 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 a) b) Fig. no. 8 4 bit priority encoder a) truth table, b) VK maps simplification Reviewing truth table we can say that another ambiguity can occur when all inputs are 0s in which case all outputs are 0s as when In_0 = 1. This ambiguity can be resolved by providing an additional output that specifies the valid condition. This output (i.e. EO, from figure above) is active when at least one input is active. - 6 -
Speaking about truth table, in order to achieve an accurate and complete design of our encoder, we observe the presence of an additional input. This input (i.e. EI, from figure above) proves to be very useful in cascaded priority encoders because it is connected to the EO output of the next higher priority encoder, which means that if one input of the encoder with higher priority is activated the outputs of the following lower priority encoders will be deactivated. The function performed by this input can be implemented very easily just by driving each of the output functions of our priority encoder with this particular input through a 2-input AND gate. All the equations which fully describes the functionality of our 4 bit priority encoder and with aid of which (using means offered by LabVIEW DE FPGA Board) we can proceed to implement it, as shown in Fig. no. 9, are presented below: i PE O _ 1 = ( In _ 2 + In _ 3) EI ii PE O _ 0 = ( In _ 3 + In _1 In _ 2) EI iii PE OE = In _ 0 + In _1+ In _ 2 + In _ 3 Fig. no. 9 4 bit Priority Encoder LabVIEW DE FPGA Board schematic implementation The capability of our encoder can be extended (e.g. from a 4:2 priority encoder to an 8:3 priority encoder, as shown in Fig. no. 10) by ORing the outputs of each 4:2 priority encoder, by rank, with the outputs of subsequent ones (since off, at the most, one priority encoder will be enabled at a time), then connecting EI of the encoder with most higher priority to ground and EO of each encoder to EI of next one with lower priority and considering the signal EO as an output (by itself, as in our case or by ORing it, in pairs of two by two, with the same signal of subsequent encoders). Based on the equations below, as they result from Fig. no. 10, and on all the explanations given above, VHDL implementation for a typical 8:3 priority encoder is presented in Fig. no. 11. i PE_8:3 O _ 2 = In _ 7 + In _ 6 + In _ 5 + In _ 4 ii PE_8:3 O _ 1 = ( In _ 6 + In _ 7) EI + ( In _ 3 + In _ 2) ( In _ 7 + In _ 6 + In _ 5 + In _ 4) iii PE_8:3 O _ 0 = ( In _ 7 + In _ 5 In _ 6) EI + ( In _ 3 + In _1 In _ 2) ( In _ 7 + In _ 6 + In _ 5 + In _ 4) iv PE_8:3 OE = In _ 0 + In _1+ In _ 2 + In _ 3-7 -
Fig. no. 10 8:3 Priority Encoder using 4:2 Priority Encoder LabVIEW DE FPGA Board schematic implementation of 8:3 PE using 4:2 PE a) b) Fig. no. 11 8:3 Priority Encoder implementation using VHDL code a) VHDL code sequence, b) LabVIEW DE FPGA Board implementation Homework: Synthesize a 16:4 PE, using the elementary 4:2 PE and a number of supplementary OR gates. - 8 -
D.3. Decoders Decoders (a.k.a. DCDs) are multiple-input, multiple-output logic circuits which converts coded inputs into coded outputs, thus performing one of the basic functions in digital systems, opposite to the one performed by an encoder, namely: with one of its one-bit outputs specifies the binary configuration applied on its inputs. Such logic circuit has numerous applications in digital systems, most of them being discussed in the following, one by one, after we have successfully synthesized the elementary 2:4 DCD. Fig. no. 12.a) shows the truth table for a 2:4 DCD. As shown in the truth table, if enable input is 1 (i.e. EN=1), then one, and only one, of the outputs P_0 P_3 is active, for a given input; but if enable input is 0, then all the outputs are 0, regardless of inputs. In other words, this additional input (which is optional) acts as a switch, turning ON or OFF the device, thus controlling its outputs. EN In_0 In_1 P_0 P_1 P_2 P_3 1 0 0 1 0 1 1 1 0 1 1 1 0 X X 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 a) b) Fig. no. 12 2:4/2_to_4 DCD a) truth table, b) VK maps simplification Expressions describing the outputs of our 2:4 DCD are computed based on the truth table, using VK maps, as shown in Fig. no. 12.b), and they are: i DCD ii DCD iii DCD iv DCD P _ 0 = In _ 0 In _ 1 EN P _ 1 = In _ 0 In _ 1 EN P _ 2 = In _ 0 In _ 1 EN P _ 3 = In _ 0 In _ 1 EN As we can see, notwithstanding the enable input and its influence on the equations i DCD iii DCD, respectively on the functionality of our DCD, each output represents one minterm of a 2-input logic function and implicitly, the logic interpretation for the outputs of our 2:4 DCD is that they represent all the minterms of a 2-input logic function. Therefore, any 2-input function can be implemented using a 2:4 DCD and an OR gate and, implicitly, any n-input function can be implemented using a n:2 n DCD and a number of supplementary OR gates. Fig. no. 13 and Fig. no. 14 shows the 2:4 DCD in schematic and VHDL implementation, both performed using means offered by LabVIEW and DE FPGA Board. - 9 -
Fig. no. 13 2:4/2_to_4 DCD LabVIEW DE FPGA Board schematic implementation a) b) Fig. no. 14 2:4 DCD implementation using VHDL code a) VHDL code sequence, b) LabVIEW DE FPGA Board implementation - 10 -
D.3.I. Multiple Output Function Synthesis using DCDs In the following, in order to showcase the idea that any logic function can be implemented using DCDs and a number of supplementary OR gates, we will try to design a 3-bit Binary to Gray Code Converter. ABinary BBinary CBinary A B C Gray Gray Gray 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0 P_0 P_1 P_2 P_3 P_4 P_5 P_6 P_7 Fig. no. 15 Table of correspondence between 3-bit Binary and 3-bit Gray codes From Fig. no. 15, which shows the table of correspondence between the two codes, we can conclude that for the implementation of our 3-bit Binary to Gray Code Converter will be needed: a 3:8 DCD having on its inputs the binary vector {A Binary, B Binary, C Binary }, used to compute all the minterms P_0 through P_7, and three 4-input OR gates used to produce the sum of the minterms corresponding to each function of the output vector {A Gray, B Gray, C Gray }. Since we need a 3:8 DCD and as we have already designed our elementary 2:4 DCD, we can use it, in multiple ways, to form a larger decoder circuit, as suggested in Fig. no. 16 and Fig. no. 17. In Fig. no. 16.a) and Fig. no. 17.a), one input line (usually the one corresponding to the most significant bit) is used to enable/disable the decoders. When MSB is 0 (i.e. A=0), the top decoder is enabled and thus its outputs generate minterms 000 through 011 (i.e. P_0 P_3). When MSB is 1, the enable conditions are reversed, the bottom decoder is enabled and thus its outputs generate minterms 100 through 111 (i.e. P4 P_7). In Fig. no. 16.b) and Fig. no. 17.b), a 2:4 DCD is used to generate the MSB which also controls the enable/disable signal for the other two decoders. The other two input signals being connected in parallel to the elementary decoders controlled by MSB means that the same output pin for each of them is selected but only one is enabled. A A B C In_0 In_1 DCD 2:4 EN B C In_0 In_1 DCD 2:4 EN P_0 P_1 P_2 P_3 P_4 P_5 P_6 P_7 a) b) Fig. no. 16 Ways to cascade elementary DCDs to form a larger one Block diagrams - 11 -
a) b) Fig. no. 17 Ways to cascade elementary DCDs to form a larger one (LabVIEW DE FPGA Board implementation) a) MSB is used as conditioning signal for DCDs, b) another DCD is used to generate the conditioning signal Now we can proceed to implement our 3-bit Binary to Gray Code Converter using DCDs and supplementary logic gates. Firstly, we will construct a 3:8 DCD using one of the methods presented above and then, with the aid of 3 supplementary 4-input OR gates, the equation for each output will be computed as shown in Fig. no. 18. The output equations are: i G_DCD ii G_DCD iii G_DCD A Gray = P _ 4 + P _ 5 + P _ 6 + P _ 7 B Gray = P _ 2 + P _ 3 + P _ 4 + P _ 5 C = P _ 1+ P _ 2 + P _ 5 + P _ 6 Gray Fig. no. 18 3-bit Binary to Gray Code Converter implementation using DCDs and OR gates LabVIEW DE FPGA Board schematic implementation From figure above we can see that each minterm is computed only once, but it can be used as many times as the implemented functions suppose. Thus we were able to show that the combination of decoder(s) and external logic gates can be used to implement single or multiple output functions. - 12 -
D.3.II. BCD to 7-Segment Display Decoder Reiterating the idea that the Light Emitting Diode is the most powerful and useful tool in electronics, it s common use being as display item (e.g. LED as on/off indicator, current direction indicator, mechanical motion indicator and more), we are used to see that in almost all practical applications optoelectronic devices such as LEDs, 7-Segment Displays or LCDs are used to give visual indication of the output states of digital ICs or to display information or digital data in a more convenient way, in the form of numbers, letters or even alpha-numerical characters. In order to make a convenient device for displaying numbers (as shown in Fig. no. 20) and/or some letters, the 7-Segment Display is composed of 7 LEDs, also called Segments, denoted by letters a g and arranged as eight (as shown in Fig. no. 19.a)) that are fabricated in one chassis (as shown in Fig. no. 19.b)). a) b) Fig. no. 19 The 7-Segment Display a) internal structure (www.electronics-tutorials.ws), b) typical chassis (www.parts.didikey.com) Fig. no. 20 The 7-Segment Display Formation of decimal numbers (www.electronics-tutorials.ws) Now, before we start the designing of our BCD to 7-Segment Display decoder/driver, is very useful to know the fact that 7-Segment Displays come in two flavors: CCD (Common Cathode Display) and CAD (Common Anode Display). In CAD version, the positive pin (i.e. the anode) of each LED is joined to a common point permanently connected to 1L and a 0L must be applied to the negative pin (i.e. the cathode) of each LED/Segment in order to illuminate them. In CCD version, the negative pin of each LED is joined to a common point permanently connected to 0L and a 1L must be applied to the positive pin of each LED/Segment in order to illuminate them. Taking into consideration the above information one more specification for our decoder is that it must be capable to drive a CCD type 7-Segment Display (i.e. the outputs must be active on 1L). Starting with the truth table, presented in Fig. no. 21, and using all the means offered by VK diagrams, as shown in Fig. no. 22 and Fig. no. 23, each output bit is minimized, the final result being the gate level implementation presented in Fig. no. 24 (schematic implementation). As we can see some segments share SOPs between them, thus we were able to compute a faster, optimized version of our decoder. VHDL implementation of our decoder/driver, designed using LabVIEW DE FPGA Board, is shown in Fig. no. 25. - 13 -
Fig. no. 21 BCD to 7-Segment Decoder Truth Table a) b) c) d) e) f) Fig. no. 22 BCD to 7-Segment Decoder VK map simplification for segments SEG_a through SEG_f As it can be observed in DCD to 7-Segment Decoder s truth table, for any binary combinations starting with 1010, through 1111, no digit is displayed. Thus, another function (called Indicator ) was computed, in order to highlight all situations when the input code exceeds value 1001. This function takes a FALSE value when the input code is within 0000 1001 range, respectively a TRUE value when the input code is within 1010 1111 range. VK map of this supplementary function is presented along with the one corresponding to segment SEG_g, in Fig. no. 23. - 14 -
A A C C 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 B B B D D D Fig. no. 23 BCD to 7-Segment Decoder VK map simplification for segment SEG_g a) and Indicator function b) Fig. no. 24 BCD to 7-Segment Decoder LabVIEW DE FPGA Board schematic implementation - 15 -
a) b) Fig. no. 25 BCD to 7-Segment Decoder VHDL implementation a) VHDL code sequence, b) LabVIEW DE FPGA Board implementation - 16 -
D.3.III. Memory Address Decoding Each computer system has its own data/information repository, the memory system, a collection of storage locations (i.e. memory words) accessed by the CPU (Central Processing Unit) through reading or writing operations. DCDs are playing multiple roles in memory systems design. Besides their use as mean to access a particular storage location, based on a numeric address produced by the CPU, DCDs can be used to select one of the many storage devices, in a memory system consisting of multiple memory chips. Both ways of using DCDs within memory systems are showcased in Fig. no. 26. a) b) Fig. no. 26 DCDs used for memory address decoding a) to access a particular storage location, b) to select one of the many storage devices (memory chips) First case, depicted in Fig. no. 26.a), starts from the assumption that within a specific application a 4 x 8bit ROM is required. To access one of the four memory locations, within the available ROM, only one of our pre-designed elementary 2:4 DCD will suffice. Thus, selection of correct memory location is done performing binary to decimal conversion of the input vector {A 1, A 0 }, which is the actual memory location address computed by CPU. The information at the particular internal memory location can be either displayed (as in our case, on LED0 LED7) either sent to CPU for further processing. A memory map example, for used 4 byte ROM, is presented in Fig. no. 27.a). - 17 -
For the second case, depicted in Fig. no. 26.b), another hypothetical situation is presented. It starts from the premises that, for a specific application, a bigger memory space (e.g. 16 x 8-bit) is required and that it has to be acquired using only available 4 x 8-bit ROM devices and pre-designed elementary 2:4 DCDs. At first assessment of the design, we can notice that 4 ROM devices and 2 pre-designed elementary DCD are required. Thus, from all the lines of input vector {A 3, A 2, A 1, A 0 } two (i.e. the most significant ones, A 3 and A 2 ) will be used to select each one of the 4 ROM chips, while the remaining 2 address lines (i.e. less significant ones, A 1 and A 0 ) select the correct memory location on selected memory chip. Fig. no. 27.a) and b) show memory map of each ROM used in above circuits, i.e. as standalone memory map for the case depicted in Fig. no. 26.a) and as multiple banks memory map for the case presented in Fig. no. 26.b). It should be noted that these memory maps have test purposes, aim of presented cases being the usage of DCDs in memory address decoding. a) b) Fig. no. 27 Memory maps of ROMs used in Fig. no. 26 Homework: Design a Memory Address Decoder for a simple microprocessor system which requires 1Kb of ROM memory, using only 128x8-bit ROM memory chips and a 3:8 DCD. - 18 -