Unit 9 Latches and Flip-Flops Dept. of Electrical and Computer Eng., NCTU 1
9.1 Introduction Dept. of Electrical and Computer Eng., NCTU 2
What is the characteristic of sequential circuits in contrast to combinational circuits? The output of a sequential circuit depends not only on the present input, but also on the past sequence of inputs In effect, sequential circuits are able to remember the past history of inputs Two of the commonly used memory devices in sequential circuits are latches and flip-flops Flip-flops change states in response to a clock input, however latches change states in response to data inputs Either latches of flip-flops are formed through feedbacks Dept. of Electrical and Computer Eng., NCTU 3
A unstable feedback A bi-stable feedback How do we control stable outputs? Dept. of Electrical and Computer Eng., NCTU 4
9.2 Set-Reset Latch Dept. of Electrical and Computer Eng., NCTU 5
Introducing control inputs to a feedback circuit S R Q P 1 0 1 0 0 1 0 1 0 0 Q n-1 P n-1 1 1 0/1 0/1 Unstable when S and R both switch from 1 to 0 simultaneously Dept. of Electrical and Computer Eng., NCTU 6
The response time of a latch The duration of the S (or R) input pulse must be longer than in order for a change in the state of Q to occur Dept. of Electrical and Computer Eng., NCTU 7
We use the term present state to mean the state of Q at the time the inputs are applied, and the term next state to mean the state of Q after the latch or flip-flop has reacted to the inputs 0 1 Characteristic Equation Q(t +ε) =S(t) + R(t) Q(t) Dept. of Electrical and Computer Eng., NCTU 8
Debouncing circuit with a S-R latch When a mechanical switch is opened or closed, the switch contacts tend to vibrate or bounce open or closed several times before settling down to their final positions Dept. of Electrical and Computer Eng., NCTU 9
9.3 Gated D Latch Dept. of Electrical and Computer Eng., NCTU 10
A gated D latch has two inputs- a data input (D) and a gate input (G). When G = 0, the output Q doesn t change. When G=1, the Q output follows the D input Dept. of Electrical and Computer Eng., NCTU 11
The symbol and the truth table for gated D-latch Dept. of Electrical and Computer Eng., NCTU 12
9.4 Edge-Trigged D Flip-Flop Dept. of Electrical and Computer Eng., NCTU 13
The output of a D flip-flop (FF) changes only in response to a clock, not a change in D A D flip-flop has two inputs, D (data) and Ck (clock) A D-FF is said to be triggered on the rising edge of the clock if the output can change in response to the 0-to-1 transition on the clock input If the output can change upon the 1-to-0 clock transition, then the D-FF is said to be triggered on the falling edge Dept. of Electrical and Computer Eng., NCTU 14
The timing diagram for a falling-edge-triggered D-FF Dept. of Electrical and Computer Eng., NCTU 15
A rising-edge-triggered D-FF Dept. of Electrical and Computer Eng., NCTU 16
In order to function properly, the D input to a edgetriggered FF must be held constant for a period of time before and after the active edge of the clock If D changes at the same time as the active edge, the behavior is unpredictable Setup time Hold time Propagation delay Dept. of Electrical and Computer Eng., NCTU 17
The minimum clock period Dept. of Electrical and Computer Eng., NCTU 18
9.5 S-R Flip-Flop Dept. of Electrical and Computer Eng., NCTU 19
A S-R FF is similar to a S-R latch in that S=1 sets Q to 1, and R=1 set Q to 0. The difference is that the flip-flop has a clock input Dept. of Electrical and Computer Eng., NCTU 20
The master-slave S-R FF Dept. of Electrical and Computer Eng., NCTU 21
There is a subtle difference between the master-slave and the edge-trigged flip-flop For a rising-edge-triggered flip-flop, the value of the input is sensed at the rising edge of the clock, and the input can change while the clock is low For the master-slave flip-flop, if the input change while the clock is low, the flip-flop output may be incorrect See an example in the previous page The problem can be solved if we only allow the S and R inputs to change while the clock is high Dept. of Electrical and Computer Eng., NCTU 22
9.6 J-K Flip-Flop Dept. of Electrical and Computer Eng., NCTU 23
J-K flip-flop is an extended version of the S-R flip-flop The J-K FF has three inputs, J, K and clock: J corresponds to S and K corresponds to K Unlike the S-R FF, a 1 input may be applied simultaneously to J and K. Q Q when J=K=1 Dept. of Electrical and Computer Eng., NCTU 24
The timing diagram of J-K FF Dept. of Electrical and Computer Eng., NCTU 25
The master-slave J-K FF S= JQ Clk and R=KQClk, only one of S and R inputs to the first latch can be 1 at any given time Notice that a master-slave FF is different from the edgetrigged FF Dept. of Electrical and Computer Eng., NCTU 26
9.7 T Flip-Flop Dept. of Electrical and Computer Eng., NCTU 27
The T flip-flop is also called the toggle flip-flop When T=1, the flip-flop changes state after the active edge of the clock. When T=0, no state change occurs Dept. of Electrical and Computer Eng., NCTU 28
Two common methods to implement a T-FF (a) Conversion of J-K to T (b) Conversion of D to T, D=T Q Dept. of Electrical and Computer Eng., NCTU 29
9.8 Flip-Flops with Additional Inputs Dept. of Electrical and Computer Eng., NCTU 30
Flip-flop with clear and preset inputs A logic 0 applied to ClrN will reset Q to 0 A logic o applied to PreN will set Q to 1 ClrN and PreN are often referred to as asynchronous clear and preset inputs Dept. of Electrical and Computer Eng., NCTU 31
The operation of the clear and preset inputs Dept. of Electrical and Computer Eng., NCTU 32
When designing a synchronous system, we frequently encounter situations where we want some flip-flops to hold existing data even if the data input to the flip-flops may be changing. There are two approaches: Gating the clock may results in loss of synchronization A flip-flop with clock enable cost extra power Dept. of Electrical and Computer Eng., NCTU 33