Section I: Digital System Analysis and Review

Section I: Digital System Analysis and Review CEG 36/56; EE 45/65 Digital System Design Dr. Travis Doom, Assistant Professor Department of Computer Science and Engineering Wright State University Thanks to M. Mano, J. Wakerly, R. Haggard

Acknowledgements These slides were developed with the aid of examples found in: Logic and Computer Design Fundamentals - M. Morris Mano Digital Design: Principles and Practices - John Wakerly The original version of many of these slides were kindly provided by: Dr. Roger L. Haggard et al. Prentice Hall, Inc. CEG 36/56 - EE 45/65 Section I - 2

Outline Review of Combinational Logic Concepts What is Sequential Logic? Bi-stable Logic Elements and Metastability Basic Sequential Devices Flip-flops: Type, Function, and Structure Characteristic Equations The Clocked Synchronous State Machine (CSSM) Analysis of State Machines General structure, Analysis procedure CSSM Models: Mealy Vs. Moore Methods of Representation State tables and diagrams Timing Calculating Setup Time, Hold Times, and Maximum clock rate CEG 36/56 - EE 45/65 Section I - 3

Logic Devices Logic devices divide into two major types: Combinational Logic Current output depends on current input only Examples: gates, decoders, multiplexors (MUXs), ALUs Familiarity with combinational logic is a course prerequisite Sequential Logic Current output depends on past inputs as well as current input Thus has a memory (usually called the state) Examples: latches, flip-flops, state machines, counters, shift registers CEG 36/56 - EE 45/65 Section I - 4

Basic Logic Gates AND gate Output Z = only when inputs A and B are both A B Z OR gate Output Z = only when inputs A or B or both are A B Z NOT gate or inverter Output Z = only when input A is A Z Simple alone, but combine a few million gates properly and you have a computer! CEG 36/56 - EE 45/65 Section I - 5

Gate Symbols OR NOR AND NAND INVERTER BUFFER Exercise: show that the equivalent gates do the same function CEG 36/56 - EE 45/65 Section I - 6

Logic Diagram A A A B B B B A (A B) (AB ) A B + AB B Good Design Practices include: Bubble-to-Bubble logic All wires are either horizontal or vertical All wires are labeled with expression Wires are connected at T intersections Wires are not connected at X intersections Schematic diagrams should include IC-Type-Logic Family Pin numbers- Pin Diagram Logic Diagram Reference designator- Unit Number Wires connected Wires not connected CEG 36/56 - EE 45/65 Section I - 7

Bubble-to to-bubble Logic Design Purpose : To make it easy to understand the function of the Logic circuit / FAIL / OVERFLOW ERROR? / FAIL / OVERFLOW ERROR CEG 36/56 - EE 45/65 Section I - 8

Digital Devices Analog characteristics Continuous signal levels Very small, smooth level changes Digital characteristics Discrete signal levels (voltage usually) Two levels: on/off, high/low / (binary) Disjoint or quantized level changes v v t t Digital Concepts and Devices Digital Design also called Logic Design Logic Gates - the most basic digital devices Digital devices have analog electronic aspects Exercise: list some of these aspects CEG 36/56 - EE 45/65 Section I - 9

Electronic Aspects of Digital Design V out V cc V cc V in R b R c V out V OHmin V OLmax Abnormal except for switching V in low? I b = GND transistor cut off: V out = V cc V in high? I b > transistor on : V out = GND V CESat GND V in V OLmax V IHmin V cc V OLmax : max output voltage in low state V OHmin : min output voltage in high state V ILmax : max input voltage recognized as low V IHmin : min input voltage recognized as high CEG 36/56 - EE 45/65 Section I -

Electronic Aspects of Digital Design Digital devices are built with analog components A range of voltages associated with each logic value ( or ) Noise margin : The difference between the range boundaries in low state = V ILmax - V OLmax =.5 V -. V=.4 V for 5V CMOS in high state = V OHmin - V IHLmin = 4.9 V - 3.5 V=.4 V for 5V CMOS Voltage Outputs Noise Margin Inputs Logic Logic Invalid Logic Logic CEG 36/56 - EE 45/65 Section I -

Electronic Aspects of Digital Design Logic gates Specifications : - Conditions under which the digital device produces and recognizes logic signals within the appropriate range. - Examples : - Power-supply voltage - Temperature - Loading - Frequency Manufacturer specifications ( data sheets ) CEG 36/56 - EE 45/65 Section I - 2

Propagation Delay The delay time between input transitions and the output transitions due to the propagation delay of the the logic gates. tp of a signal depends on the signal path inside the logic circuit For a logic gate tplh may not equal tphl tp is specified in the manufacturer data sheets of the IC s Example : -The time delay for 74x in nanoseconds for three logic Families: Typical Maximum tplh tphl tplh tphl 74LS 9 5 5 74HCT 35 35 74ACT 5.5 4. 9.5 8. To find tp for a signal, add the propagation delays of all gates along the path of the signal CEG 36/56 - EE 45/65 Section I - 3

Timing Diagrams Actual Timing Diagram X Y X Y t plh(xy) t phl(xy) t rise t fall Functional Timing Diagram X Y Functional timing diagrams do not show exact delays. lining up everything allows the diagram to display more clearly which functions are performed in response to which action Illustrates operation, but does not specify upper and lower limits Not always sufficient for a real design CEG 36/56 - EE 45/65 Section I - 4

Decoder Multiple-input/multiple-output device. Decoder -Inputs (n) < outputs (m). Encoder - Inputs (n) > outputs (m) input code DECODER output code Converts input code words into output code words. One-to-One mapping : - Each input code produces only one output code. enable inputs Input codes : - Binary Code - Gray Code - BCD Code - Your Code! input code ENCODER output code CEG 36/56 - EE 45/65 Section I - 5

Binary Decoder n-to-2^n decoder: n inputs and 2^n outputs. Input code : Binary Code. Output code : -out-of-2^n, One output is asserted for each input code. Example : n=2, 2-to-4 decoder Inputs Outputs EN I I Y3 Y2 Y Y x x I I EN Y Y Y2 Y3 CEG 36/56 - EE 45/65 Section I - 6

Comparators Compares Two binary words and indicate if they are equal A B Comparator OUTPUT Advanced Comparators : A B Comparator A=B A>B A<B -bit Comparator : XOR gate, the Output is if A<>B A B F CEG 36/56 - EE 45/65 Section I - 7

Iterative Combinational Logic Iterative logic array: A device consisting of identical sub-circuits connected together in a chain to perform a larger overall function Iterative Comparator : cascaded -bit comparators -bit comparator : Function Table EI X Y EO x x EI X Y EO X Y X Y X(N-) Y(N-) E = X EI Y EO E X EI Y EO E E(N-) X EI Y EO EN CEG 36/56 - EE 45/65 Section I - 8

MSI Arithmetic Logic Units (ALU ) ALU performs Arithmetic and Logical Functions - A, B : 4 bits inputs - S3,S2,S,S : Function select - M= : Arithmetic operations +=Plus, - = Minus M= : Logical operations : += OR,. =AND Example : Inputs Functions S3 S2 S S M= M= F= A-+CIN F=A F= A-B-+CIN F=A XOR B F= A+B+CIN F=A XOR B F=(A OR B)+ CIN F=A+B F= A+A+CIN F= F=A+CIN F=A 74x8 S S S2 G S3 P M A=B CIN A F B F A F2 B F3 A2 COUT B2 A3 B3 CEG 36/56 - EE 45/65 Section I - 9

Multiplexers Multiplexing: transmitting large number of signals over a small number of channels or lines Digital multiplexer (MUX): selects one of many input lines and directs it to a single output (often a bus or party line ). Selection lines controls the selection of a particular input m-bit 2 n x multiplexer: n selection lines, 2 n m-bit inputs, m-bit output. Example : 4-to- line multiplexer: Function Table : S S Y I I I2 I3 Inputs I I I2 I3 4? MUX S S Select Y Output CEG 36/56 - EE 45/65 Section I - 2

Implementing Logic Functions Any n-variable logic function can be implemented using a 2 n -to- MUX (In fact, MUXs are a universal device! Any combinational function can be implemented using only MUXes). The inputs variables are connected to the select input. The function value for each input combination ( or ) is connected to the corresponding input of the MUX Example: I Row X Y F 2 3 X Y I I2 I3 4? MUX S S Y F CEG 36/56 - EE 45/65 Section I - 2

Functional Decomposition Effective way for using MUX to implement Logic Functions. n-variable truth table can be simplified using any MUX : Use one or more variables as control inputs Decompose the remaining logic function in terms of the remaining inputs For 3-variable Logic Function, the decomposed truth table is : Row X Y Z F, x F(Z) 2,3 x F(Z) 4,5 x F(Z) 6,7 x F(Z) F(Z) F(Z) F(Z) I I I2 4? MUX Y F Values of Fxx(Z) = or or Z or Z F(Z) I3 S S X Y CEG 36/56 - EE 45/65 Section I - 22

Demultiplexers Demultiplexer (DMUX) performs the opposite function of a MUX. A digital Demultiplexer receives input data on a single input and transmits it on one of 2^n possible outputs according to the value of the n select inputs MUX/DMUX are used in data transmission Source Destination A B MUX BUS DMUX A B C C Select Select CEG 36/56 - EE 45/65 Section I - 23

Programmable Logic Devices PLDs are generic logic devices capable of implementing a wide range of combinational (and sequential) functions. O = F (x x n ) O = F (x x n ) O m = F m (x x n ) n inputs Combinational PLD m outputs CEG 36/56 - EE 45/65 Section I - 24

Sequential Logic Definitions STATE- A collection of state variables whose values at any one time contain all the information about the past values necessary to account for future behavior. Example: A TV tuner could have a current channel stored internally, so the next channel can be predicted as a function of the inputs, i.e. the UP button increases the channel by one, the DOWN button decreases the channel by one. What is the state of this TV tuner? Digital sequential logic State variables are binary values Circuit with n binary state variables has 2 n possible states Also known as a finite state machine (FSM). Changes usually synchronized with a system clock CEG 36/56 - EE 45/65 Section I - 26

Bistable Element The simplest possible feedback sequential logic circuit is shown below: V in V out V in2 V out2 / It is bistable because it has two stable states: State : If (=V out =V in2 ) is high, the bottom inverter output (/ =V out2 =V in ) is low, which keeps the top inverter output high. State 2: If is low, the bottom inverter output / is high, which keeps the top inverter output low. CEG 36/56 - EE 45/65 Section I - 27

Analog Analysis of a Bistable Top Inverter alone Bottom Inverter alone V out V in2 V in V out2 / Complete Bistable V out =V in2 Stable High Metastable Stable Low V in =V out2 CEG 36/56 - EE 45/65 Section I - 28

Bistable Devices and Metastability There are not two stable states, but three (a problem!) A metastable point occurs when both outputs are halfway between high and low, the resulting output is not a valid logic level. Metastability could last forever, but noise usually pushes towards a stable state (HIGH or LOW). Noise in a bistable state returns it to the same stable state Every input pulse must remain stable long enough This is the minimum pulse width for the bistable element Analogous to a ball on a hill: Metastable Stable Low Stable High Strong kick (wide pulse)? Weak kick? Moderate kick? CEG 36/56 - EE 45/65 Section I - 29

S-R R Latch Set Symbol S Hold Function Table S R / Last Last / Reset R Reset Set ILLEGAL R S Schematic / Characteristic Equation: (t+) = S + R (t) Consider: Timing Diagram Propagation delay Minimum pulse width Oscillation CEG 36/56 - EE 45/65 Section I - 3

S-R R Latch with Enable S C R S R C / Last Last / S X X Last Last / C R S R Only sensitive to S and R when enabled (C=) Same oscillation problem How does C effect the minimum pulse width? CEG 36/56 - EE 45/65 Section I - 3

D Latch D C C D / X Last Last / Characteristic Equation: (t+) = D D C S C R Store a data bit, not set/reset The Transparent latch No illegal operation problem CEG 36/56 - EE 45/65 Section I - 32

Types of Sequential Logic An Asynchronous Sequential Circuit uses ordinary gates and feedback loops to implement memory in a logic circuit. Meeting minimum pulse width requirements may be tricky A Synchronous Sequential Circuit uses flip-flops (internally, an asynchronous sequential device) to form useful sequential logic functions or applications. The state variables and outputs of a synchronous system change with respect to a controlling clock signal Meeting minimum pulse width requirements is simplified by restating all timing constraints in terms of the clock signal CEG 36/56 - EE 45/65 Section I - 34

Sequential Logic Definitions Clock - the master timing element behind the state changes of most sequential circuits. a clock signal is active high if the state changes occur at the rising edge (for edge triggered devices) or in the logic state (for pulse-triggered devices) active low if state changes occur at the falling edge or in the logic state. Clock Period - time between successive transitions in the same direction Clock Frequency - reciprocal of the clock period Clock Tick - the first edge or pulse in a clock period, or the period itself Duty Cycle - the percentage of time that a clock is at its assertion level CEG 36/56 - EE 45/65 Section I - 35

Clock Characteristics State change Frequency = /Period Active High Period t L t H Duty Cycle = t H /Period State change Active Low Period t L t H Duty Cycle = t L /Period CEG 36/56 - EE 45/65 Section I - 36

Master/Slave S-R S R Flip-Flop Flop S R C / S C R X X Last Last Last / Last / Pulse-triggered S-R flip-flop Multiple signals may conflict Ideally, inputs are held for the entire enable pulse S R S C R S C R undef. undef. / C Only one state change/pulse CEG 36/56 - EE 45/65 Section I - 37

Master/Slave J-K J K Flip-Flop Flop J K C / J C K Fixes S=R= problem, now toggles /s catching - gate propagation delays complicate timing X X Last Last Last / Last / Last / Last J K S C R S C R / C CEG 36/56 - EE 45/65 Section I - 38

Positive-Edge Edge-Triggered D Flip-Flop Flop D D CLK / D >CLK Device samples inputs and changes state only on a clock edge. Simplifies the meeting of setup/hold times. Master FF - transparent on CLK (entire pulse) Slave FF - transparent on CLK (master fixed) Master D X X M Last Last Slave D Last / Last / C C / CLK CEG 36/56 - EE 45/65 Section I - 39

Negative-Edge Edge-Triggered D Flip-Flop Flop D >CLK D CLK / X X Last Last Last / Last / D D D C C / CLK CEG 36/56 - EE 45/65 Section I - 4

Edge-Triggered J-K J K Flip-Flop Flop J K C / J >CLK K X X X X Last Last Last Last / Last / Last / Last / Last J K D (t+) = J (t) + K (t) CLK >CLK / CEG 36/56 - EE 45/65 Section I - 4

T (toggle) Flip-Flop Flop A T flip-flop changes state on every clock tick (if enabled) Possible circuit designs T without enable D >CLK / J >CLK K / (t+) = (t) T with enable T D >CLK / T J >CLK K / (t+) = T (t) + T (t) CEG 36/56 - EE 45/65 Section I - 42

Types Latches and Flip-flops Common Latches S-R Latch /S-/R Latch S-R Latch with Enable D Latch Common Flip-flops Edge-Triggered D Flip-Flop Master/Slave S-R Flip-Flop Master/Slave J-K Flip-Flop Edge-Triggered J-K Flip-Flop T Flip-Flop CEG 36/56 - EE 45/65 Section I - 43

Characteristic Equations Describe the next state of a flip-flop as function of current state and inputs: (t+) = f ((t), inputs) t+ represents the next clock tick t represents the current clock tick t- represents the previous clock tick and so on... Derived from basic function table for a given flip-flop type Very useful in state machine analysis and design CEG 36/56 - EE 45/65 Section I - 44

Characteristic Equations D latch or flip-flop present next input state state D (t) (t+) Characteristic Equation: (t+) = D S-R latch S R (t) (t+) X X X X Characteristic Equation: (t+) = S + R (t) CEG 36/56 - EE 45/65 Section I - 45

Characteristic Equations J-K flip-flop J K (t) (t+) = hold = reset = set = toggle Characteristic Equation: (t+) = J (t) + K (t) T flip-flop with enable T (t) (t+) Characteristic Equation: (t+) = T (t) + T (t) CEG 36/56 - EE 45/65 Section I - 46

Characteristic Equations Summary Device Type Characteristic Equation S-R latch (t+) = S + R (t) D latch Edge-triggered D flip-flop Master/slave S-R flip-flop Master/slave J-K flip-flop Edge-triggered J-K flip-flop T flip-flop T flip-flop with enable (t+) = D (t+) = D (t+) = S + R (t) (t+) = J (t) + K (t) (t+) = J (t) + K (t) (t+) = (t) (t+) = T (t) + T (t) CEG 36/56 - EE 45/65 Section I - 47

What Are Flip-flops? Common asynchronous (feedback) sequential circuits Latch Single-bit storage (memory) Changes state at any time due to input change Must guarantee a minimum pulse width to avoid metastability Fast and cheap (small # of transistors) Often used in high speed microprocessor design Flip-flop Also single-bit storage Changes state ONLY when a clock edge or pulse is applied Uses setup and hold times before and after the clock pulse to avoid metastability Clocking simplifies the design process CEG 36/56 - EE 45/65 Section I - 48

Flip-flop Timing t pd Combinational Latch Flip-flip t pd,min t pd,max t pd,min t pd,max t w t pd, min t pd, max t setup t hold t setup, t hold J >CLK K - minimum propagation delay, input to output - maximum propagation delay, input to output - minimum propagation delay, input to output - maximum propagation delay, input to output - minimum pulse width, input to input - minimum propagation delay, CLK to output - maximum propagation delay, CLK to output - required time of stable input before CLK, input before CLK - required time of stable input after CLK, input after CLK CEG 36/56 - EE 45/65 Section I - 49

Asynchronous Inputs Most flip-flops have two asynchronous/direct inputs Preset and Reset (or Clear) Directly set or reset the /S-/R latches Operate independent of clock Good design practice dictates: NEVER use asynchronous inputs for logic functions, only for system initialization to a known state Why? Recall: Synchronous circuits: behavior of circuit depends on the value of the signals at discrete points in time, determined by a control signal (clock) Asynchronous circuits: behavior of circuit depends on the order in which the inputs signals change (changes can occur at any time) CEG 36/56 - EE 45/65 Section I - 5

Clocked Synchronous State-machine Analysis Analysis How does a given circuit work? What does it do? How do input sequences map to output sequences? Clocked synchronous state-machine Clocked: storage elements (flip-flops) use a clock input Synchronous: all flip-flops use the same clock signal State-machine types Mealy Machine (most general type): Next state = F ( current state, inputs ) Output = G ( current state, inputs ) Moore Machine: Next state = F ( current state, inputs ) Output = G ( current state ) CEG 36/56 - EE 45/65 Section I - 52

Clocked Synchronous State-machine Model (Mealy machine) inputs Next-state Logic excitation State Memory current state Output Logic outputs F G clock clock State memory: Usually edge-triggered D or JK flip-flops Moore Machine CEG 36/56 - EE 45/65 Section I - 53

Basic Analysis of State Machines Determine next-state and output functions F and G Use F and G to construct a state/output table Draw a graphical representation of the state/output table State Diagram Common for small designs Similar to a finite automata Algorithmic State Machine (ASM) Chart Common for larger designs Similar to a flowchart Timing Diagram Common for all designs CEG 36/56 - EE 45/65 Section I - 54

Detailed Analysis of State Machines Analyze the combinational logic to determine flip-flop input (excitation) equations: D i = F i ((t), X(t)) The input to each flip-flop is based upon current state and primary inputs Substitute excitation equations into flip-flop characteristic equations, giving transition equation: i (t+) = H i ( D i ) Construct a state table from the transition equations Find output equations: Z(t) = G ((t), X(t)) The primary outputs are based upon the current state and primary inputs Add output values to the state table Provide meaningful names for the states in state table, if possible The graphical representation of state table is called a state diagram Analyze timing requirements CEG 36/56 - EE 45/65 Section I - 55

Moore A B, State Diagram Format: Arc = input X Node = state/output Mealy Basic Format: State Output Input / A / B Format: Arc = input X / mealy output Y Node = state /, / CEG 36/56 - EE 45/65 Section I - 56

Example - Circuit w/o Primary Inputs Y D D D D Z CLK Excitation: D = ( + ) = D = Output: Y = Z = Thus, Moore machine CEG 36/56 - EE 45/65 Section I - 57

Example - Equations Excitation D = D = Characteristic (t+) = D (t+) = D Transition (t+) = D = (t+) = D = Output Y = Z = CEG 36/56 - EE 45/65 Section I - 58

State Table: Example - Tables 2 Y Z State Table w/named states: (t+)2(t+) S Y Z A A B C C B D B S(t+) No inputs! Transition (t+) = D = (t+) = D = CEG 36/56 - EE 45/65 Section I - 59

Example - State Diagram Format: Arc = no input Node = state/outputs YZ A B A,D Unreachable, Only B,C are useful. Therefore, only flip-flop is needed. D C CEG 36/56 - EE 45/65 Section I - 6

Example 2 - State Machine with D Flip-flops X Y /2 D D CLK Z D D CLK D2 D CLK 2 /2 /Z2 CLK Input Logic F State Memory Output Logic G CEG 36/56 - EE 45/65 Section I - 6

Example 2 - Equations Excitation D = X Y 2 D = X D2 = Y + Characteristic (t+) = D (t+) = D 2(t+) = D2 Transition (t+) = D = X Y 2 (t+) = D = X 2(t+) = D2 = Y + Output Z = X + /Z2= ( 2) CEG 36/56 - EE 45/65 Section I - 62

Example 2 - Two-Dimensional State table state XY name 2 A=,,,, B=,,,, C=,,,, D=,,,, E=,,,, F=,,,, G=,,,, H=,,,, 2(t+) (t+) (t+), Z /Z2 (Next State, Outputs) Transition Equations (t+) = D = X Y 2 (t+) = D = X 2(t+) = D2 = Y + X Y 2 - - - - - - - - - or - - - - Output Equations Z = X + /Z2= ( 2) CEG 36/56 - EE 45/65 Section I - 63

Example 2 - Named State / Output table XY S A E, A, A, F, B E, A, C, H, C E, E, E, F, D E, E, G, H, E E, A, A, E, F E, A, C, G, G E, E, E, E, H E, E, G, G, S(t+), Z /Z2 CEG 36/56 - EE 45/65 Section I - 64

Example 2 - State Diagram Y () () X Y B X Y () H Incomplete! A G XY () X Y () F X Y () C XY X +Y X Y () () () XY () XY () Different format Arc: input expression (outputs) = expression (Z /Z2) E D X () Also possible: Same transition, but different outputs x y () A x y () CEG 36/56 - EE 45/65 Section I - 65 B

Analysis of J-K J K Flip-Flop Flop State Machines There are two excitation equations per flip-flop (J, K) The characteristic equation : (t+) = J (t) + K (t) Use the same analysis procedure shown previously CEG 36/56 - EE 45/65 Section I - 66

Example 3 - State Machine with J-K J K Flip-flops X J J Z Y K J2 K J 2 Mealy Output: Z = X + 2 K2 K CLK CEG 36/56 - EE 45/65 Section I - 67

Example 3 - Equations Excitation J = X K = X Y J2 = X K2 = Characteristic (t+)= J + K (t+) = J + K 2(t+) = J2 2 + K2 2 Transition (t+) = X + (X Y) = X + X + Y 2(t+) = X 2 + 2 = X 2 + 2 Mealy Output Z = X + 2 CEG 36/56 - EE 45/65 Section I - 68

Example 3 - State Table XY S 2 A,,,, B,,,, C,,,, D,,,, (t+) 2(t+), Z Transition (t+) = X + (X Y) = X + X + Y 2(t+) = X 2 + 2 = X 2 + 2 Mealy Output Z = X + 2 CEG 36/56 - EE 45/65 Section I - 69

Example 3 - Named State/Output Table XY S A B, B, C, C, B B, B, D, D, C D, D, A, C, D D, D, B, D, S(t+), Z CEG 36/56 - EE 45/65 Section I - 7

Example 3 - State Diagram Arc Format: inputs xy output z A, B,,, D,,, C CEG 36/56 - EE 45/65 Section I - 7

Example 3 - State Diagram Arc Format: Transition Expression output A X B X X XY X XY X C (XY) D XY For each state/input combination there must be exactly one next-state (and output). Mutual Exclusion: No more than one transition arc from any state can be satisfied by any input assignment All Inclusion: At least one transition arc must exist from any state for any input assignment CEG 36/56 - EE 45/65 Section I - 72

Timing Analysis All digital devices have associated propagation delays (min,max) Sequential devices have setup and hold times that must be satisfied to avoid metastable behavior Providing a synchronous clock simplifies timing analysis All devices produce effects within a well-defined range At what speeds will a device function? One transition per clock What is the maximum clock rate? Sequential devices require the following timing documentation: Maximum propagation delay (clock to output) Minimum propagation delay (clock to output) Setup time (input before clock) Hold time (input after clock) CEG 36/56 - EE 45/65 Section I - 73

74LS74 Data Sheet Timing Parameter Min Max Units t W Pulse Width - Clock High 8 ns - Preset Low 5 ns - Clear Low 5 ns t SU Setup Time 2 ns t H Hold Time ns f MAX Max Clock Frequency 2 MHz t PLH Prop Delay, Clock-to- 35 ns t PLH Prop Delay, Preset-to- 35 ns t PLH Prop Delay, Clear-to- 35 ns CEG 36/56 - EE 45/65 Section I - 74

Clocked Synchronous State-machine Structure (Mealy machine) inputs Next-state Logic excitation State Memory current state Output Logic outputs F R G clock clock Calculate: t, F_pd(max) t, F_pd(min) t, R_pd(max) t, R_pd(min) t, R_setup(max) t, R_hold(max) t, G_pd(max) t, G_pd(min) CEG 36/56 - EE 45/65 Section I - 75

Timing Diagram CLOCK flip-flop outputs combinational logic t ffpd t H t clk t L t comb excitation inputs setup-time margin t setup t hold CEG 36/56 - EE 45/65 Section I - 76

Calculating Sequential Device Timing Specs. Calculate the delay from clock edge to worst-case primary output: t_pd,clock-to-output (min) = t,r_pd(min) + t,g_pd(min) t_pd,clock-to-output (max) = t,r_pd(max) + t,g_pd(max) Calculate the delay from input to worst-case (Mealy) primary output: t_pd,input-to-output (min) = t,g_pd(min) t_pd,input-to-output (min) = t,g_pd(min) Calculate the worst-case setup time for any input: t_setup = t,f_pd(max) + t,r_setup(max) Calculate the worst-case hold time for any input: t_hold = t,r_hold(max) - t,f_pd(min) Calculate the maximum clock rate by finding the minimum period: min. period = t,r_pd(max) + t,f_pd(max) + t,r_setup(max) Make certain that the device works! t,r_pd(min) + t,f_pd(min) > t,r_hold(max) CEG 36/56 - EE 45/65 Section I - 77

Synchronous System Example in in2 Combinational logic State Devices 3 2 t pd,comb = 2 ns (min) to 2 ns (max) t pd,ff = 3 ns (min) to 5 ns (max) t setup = 5 ns Setup/Hold Time: Max Frequency? Setup margin @ MHz? Hold Margin? t hold = 4 ns t setup = 2 + 5; t hold = 4-2 = 2 ns t clk,min >= 5 + 2 + 5 = 4 ns, f max <= 25 MHz - 4 = 6 ns (3 + 2) - 5 = ns (4ns) - = 25 MHz CEG 36/56 - EE 45/65 Section I - 78