A DELAY EFFICIENT LOW POWER SHIFT REGISTER BY MEANS OF PULSED LATCHES J.VIJAYA SAGAR 1, T.VIJAYA NIRMALA 2 1 M.Tech., VLSISD, Dept. of ECE, AITS, Kadapa, A.P., India, vijayasagarsadhu@gmail.com 2 Asst. Professor, Dept. of ECE, AITS, Kadapa, A.P., India, aitsnirmala@gmail.com stract--this paper proposes a Delay efficient low power shift register by means of pulsed latches. The delay and Power consumption are decreased by restored flip-flops with pulsed fastener. The timing problem among pulsed latches are resolved during various non-overlap postponed pulsed clock Signal in its place of straight signal pulsed clock signal. The shift register utilize A small quantity of the pulsed clock signals by alignment the latches to various sub shifter registers and by means of other temporary storage latches. A 256-bit shift register by means of pulsed latches was fictional through COMS 180NMTechnology of a 0.18 µm CMOS process with VDD = 1.8V. The core area is 6600µm². The power consumption is 1.2mW at a 100 MHz clock frequency. The projected shift register Saves 30% area and setback will be decrease than conservative method 44% power saves as associated to the conventional shift register with flip-flops. Keywords low power,edge triggered flip-flop, pulsed clock, pulsed latch, shift register. pulsed latch may be apply in a shift register since I.INTRODUCTION of timing problem among pulsed latches. Shift register are memory devices, which stores the digital data. Shift register which shift data as both left and right Shifts.IN VLSI circuits shift registers are plays very important role.are commonly used in many applications, such as digital filters, communication receivers,and image processing ICs. Recently, as the size of the image data continues to increase since of high demand for high quality image data, the word length of The shifter register increases to procedure tremendous photo data in picture processing ICs. An pictureextraction and vector new release VLSI chip uses a 4K-bit shift register. A sixteen-megapixel CMOS snapshot sensor uses a 45K-bit shift register. As the word size of the shifter register is propotional to the field and vigor consumption. The architecture of shift register is quite simple. A N-bit shift register is composed by series connected of N data Flip-flops.IN VLSI circuit are and power reduction is very important so that to choose the smallest flip-flop is suitable for the shift register to reduce the area and power.in shift register to maintain the certain level edge triggered by master slave flip-flop. But it is large size.recently, flipflops are replaced by pulsedlatches should restored flip-flop in various applications, since a pulsed latch is more slighter than a flip-flop. But the Fig. 1. (a) Master-slave flip-flop. (b) Pulsed latch. IN shift register timing problems are solved by multiple non-overlap postponed pulsed clock signals rather than the conventional single pulsed clock signal. The several non-ovelap signals are produced by belated pulse clock generator. II. CONVENTIONAL SHIFT REGISTER A master-slave flip-flop by means of two latches in Fig. 1(a) can be restore by a pulsed latch remaining of a latch and a pulsed clock signal in Fig. 1(b). Allpulsed latches share the pulse production circuit for the pulsed clock signal. Accordingly, the area and power utilization of the pulsed handle among roughly half of those the master-slave flip-flop. All pulsed latches share the pulse new release circuit for the pulsed clock sign. For this reason,
the field and energy consumption of the pulsed latch grow to be virtually half of of those of the grasp-slave flip-flop. The pulsed latch is an appealing resolution for small area and low vigour consumption. Through pulsed latches can t be used on the grounds that of timing issues will be occurred. Shown in Fig 2.. The shift register in Fig. 2(a) consists of several latches and a pulsed clock signal (CLK_pulse). The operation waveforms in Fig. 2(b) show the timing concern in the shifter register. The output sign of the first latch (Q1) changes properly on account that the enter signal of the primary latch (IN) is steady for the period of the clock pulse width. Through the second latch has an unsure output signal (Q2) in view that its enter sign (Q1) changes for the duration of the clock pulse width. Fig. 2. Shift register with latches and a pulsed clock signal. (a) Schematic. (b) Waveforms Those timing problems are reduced by adding the delay circuits in among the latches. Which is shown in Fig. 3(a). The latch output signal is postponed and it will be reaches to input of next latch after the clock pulse. As shown in Fig. 3(b) the first and second latches output signals(q1 and Q2) change during the clock pulse width, but the second and third latches input signals (D2 and D3) become the same as the the first and second latches outputs (Q1 and Q2) after the clock pulse. As a result, All latches have regular enter indicators for the duration of the clock pulse and no timing hindrance occurs among the latches. Through, the prolong circuits intent large area and vigour overheads. Fig. 3. Shift register with latches, delay circuits, and a pulsed clock signal. (a) Schematic. (b) Waveforms Another solution is to use multiple non-overlap postponed pulsed clock signals, as shown in Fig. 4(a). The postponed pulsed clock signals are produced while a pulsed clock signal goes through delay circuits. Every latch uses a pulsed clock signal that is belated from the pulsed clock signal used in its next latch. Therefore, each latch updates the data after its next latch updates the data. Hence, every latch steady input in the course of its clock pulse and no timing quandary in among the latches. Through, this resolution also requires many extend circuits. Fig. 4. Shift register with latches and postponed pulsed clock signals. (a) Schematic. (b) Waveforms The delays occurred when the out put of the first latch and to input of second one as well as the succession of latchs,is given Fig 5. IN conservative shift register although flip-flops are replaced by pulsed latch, are is increased by
delay circuits and power will be decrease little bit. The delay will be reduce in a proposed Shift register. III.PROPOSED SHIFT REGISTER Proposed shift register is separated into M sub shifter registers to decrease the number of belated pulsed clock signals. IN Proposed shift register, the N-BIT shift register can be divided in to M sub shift register,then the number of postponed circuits are reduced.a 4-bit sub shifter register consists of five latches and it performs shift operations with five non-overlap postponed pulsed clock signals (CLK_pulse 1:4 and CLK_pulse T ). In the 4-bit sub shift register #1, four latches store 4-bit data (Q1-Q4) and the last latch stores 1-bit temporary data (T1) which will be stored in the first latch (Q5) of the 4-bit sub shift register #2. Fig. 5(b) shows the process waveforms. Within the proposed shift register. Five non-overlap postponed pulsed clock indicators are generated via the postponed pulsed clock generator in Fig. 6. The pulsed clock indicators is in the reverse order of the 5 latches. Firstly, the pulsed clock signal CLK_pulse T updates the latch knowledge T1 from this fall. And then, the pulsed clock signals CLK_pulse 1:four replace the four latch data from this autumn to Q1 sequentially. The latches Q2 this autumn obtain knowledge from their prior latches Q1 Q3 through the latch Q1 receives information from the shift register enter (IN). The operations of the other sub shift registers are the equal as that of the sub shift register #1 besides that the first latch receives information from the temporary storage latch within the prior sub shift register. The conservative belated pulsed clock circuits in Fig. 4 can be used to save the AND gates in the belated pulsed clock producer in Fig. 6. In the conventional postponed pulsed clock circuits, the clock pulse width must be heavy than the summation of the rising and falling times in all inverters in the delay circuits to keep the shape of the pulsed clock. Through, in the postponed pulsed clock generator in Fig. 6 the clock pulsed width can be shorter than the summation of the rising and falling times since each sharp pulsed clock signal is generated from an AND gate and two postponed signals. Therefore, the postponed pulsed clock generator is suitable for short pulsed clock signals. The number of latches and clocks pulses are changes according to the number of sub shift registers. Fig. 5. Proposed shift register. (a) Schematic. (b) Waveforms. The power is consumed mainly in latches and clock generating circuit. Each latch consumes power for data transition and clock loading. When the powers are normalized with a latch, the power consumption of a latch and a clock-pulse circuit are 1 andαp respectively. The total power consumption is also. An integer for the minimum power is selected as a divisor nearest to Fig. 6. Postponed pulsed clock generator.. In selection, the clock buffers in Fig. 6 are not considered. The total area of the clock buffers is determined by the total number clock loading of latches. Although the number of latches increases from N to N(1+1/K), the increment ratio of the clock buffers is small. The number of clock buffers is. K.As K increases, the size of a clock buffer decreases in proportion to 1/Ksince the number of latches connected to a clock buffer (M = N/K) is proportional to 1/K.. Therefore, the total size of the
clock buffers directly propotional to K and the effect of the clock buffers can be neglected for choosing K.. CHIP IMPLEMENTATION The area and power consumption are more important than the speed for selecting the flip-flop. The proposed shift register uses latches for reduce the area and power consumption. In chip implementation, the SSASPL (static differential sense amp shared pulse latch) in Fig. 7, which is the smallest latch, is selected. The original SSASPL with 9 transistors is modified to the SSASPL with 7 transistors in Fig. 8 by removing an inverter to generate the complementary data input (Db) from the data input (D). In the proposed shift register, the differential data inputs (D and Db) of the latch come from the differential data outputs (Q and Qb) of the previous latch. The SSASPL makes use of the much less quantity of transistors 7. And it consumes the lowest clock power on account that it has a single transistor pushed via the pulsed clock sign. The SSASPL alterations as for the information with three NMOS transistors (M1 M3).And it holds the information with four transistors in two go-coupled inverters. It requires two differential data inputs (D and Db) and a pulsed clock signal. When the pulsed clock signal is high, its data is updated. The node Q or Qb is pulled down to ground according to the input data (D and Db). The pull-down current of the NMOS transistors (M1 M3). must be larger than the pull-up current of the PMOS transistors in the inverters. The SSASPL was implemented and simulated with a 0.18µm CMOS process at VDD = 1.8 V. The sizes (W/L) of the three NMOS transistors (M1 M3) are 1µm/0.18µm. The sizes of the NMOS and PMOS transistors in the two inverters are all 0.5µm/0.18µm. The minimum clock pulse width of the SSASPL to update the data is 62 ps at a typical process simulation (TT) and 54 76 ps at all process corner simulations (FF-SS). The rising and falling times of the clock pulse are approximately 100 ps. The clock pulse shape can be degraded since of wire delay, signal coupling, supply noise. The clock pulse Width ( TPULSE) of 170 ps was selected by adding the timing margin to the minimum clock pulse width at the slowest simulation case. Fig. 7. Schematic of the SSASPL Fig. 8. Simulation waveforms of a shift register with the SSASPLs driven by a pulsed clock signal. The shift registers are designed by different catagires flipflops. Different types of flip-flops and their transisters are listed by Table I shows the transistor comparison of pulsed latches and flipflops. The transmission gate pulsed latch (TGPL), hybrid latch flip-flop (HLFF), conditional pushpull pulsed latch (CP3L), Power-PC-style flip-flop (PPCFF), Strong-ARM flip-flop (SAFF), data mapping flip-flop (DMFF), conditional precharge sense-amplifier flip-flop (CPSAFF), conditional capture flip-flop (CCFF), adaptive-coupling flipflop (ACFF) are compared with the SSASPL used in the proposed shift-register. When counting the whole number of transistors in pulsed latches and flip-flops, the transistors for generating the differential clock signals and pulsed clock signals are not included since they are shared in all latches and flip-flops. The SSASPL uses 7 transistors, which is the smallest number of transistors among the pulsed latches. The PPCFF uses 16 transistors, which is the smallest number of transistors among the flip-flops.
TABLE I TRANSISTOR COMPARISON OF PULSED LATCHES AND FLIP-FLOPS thessaspls. The proposed shift register achieves a small area and low power consumption compared to the preavious shift register. The areas of the proposed shift registers with K = 4 and K = 8 and are 63.2% and 59.0%, respectively, compared to that of the preavious shift register. The power consumptions of the proposed shift registers with K = 4 and K = 8 are 56.3% and 56.5%, respectively, compared to that of the conventional shift register. TABLE II PERFORMANCE COMPARISONS OF THE PPCFF AND SSASPL TABLE III PERFORMANCE COMPARISONS OF SHIFT REGISTERS Fig. 9. Schematic of the PPCFF Shows Fih.9. the schematic of the PPCFF, which is a typical master-slave flip-flop composed of two latches. The PPCFF consists of 16 transistors and has 8 transistors driven by clock signals. For a fair comparison, it uses the minimum size of transistors. The sizes of NMOS and PMOS transistors are 0.5µm/0.18µm and 1µm/0.18µm, respectively. Its layout was drawn compactly by sharing all possible sources and drains of transistors. All circuits were implemented with a 0.18 µm CMOS process. The powers were measured at VDD = 1.8V and fclk = 100MH. Table II shows the performance comparisons of the PPCFF and SSASPL. The SSASPL is 48.8% smaller and consumes 60.2% less power than the PPCFF. Table III shows the performance comparisons of the 256-bit shift registers. The conventional shift register by means of flip-flops was implemented with the PPCFFs. The shift register by means of pulsed latches were implemented with Fig. 10. Area and power consumption of the proposed 256-bit shift registeraccording to K at fclk = 100MH.
IV. RESULTS IN this paper, the shift register designed by the Pulsed latchs. To obtained the delay efficient Low power shifter register by means of the pulsed latches. The d latch which is total voltage source Power dissipate the 165.0397µW. SSASPL latch is the compose by 7 transister, small are low power and delay will be reduced simple.the total voltage source power dissipation of SSASPL is 80.9659µw,and average power is 3.1033E-06. Fig.11.Simmulation of Pulsed Latch Fig.14.Delays of shift register with latches and Pulsed clock signal THE Proposed shifter register wich is designed by pulsed latches,which is low power applilication. which is total voltage source power Dissipation of 1.9069mw and average power is 8.8236E-04. Fig.12.Simmulation of SSASPL Fig.13.Simmulation PCFF The PCFF flip-flop is composed by 16 transister and which is total voltage source power dissipation of 224.6096µw and average power is 1.7819E-04. Fig.15. PROPOSED SHIFT REGISTER V.CONCLUSION This paper proposed A lengthen efficient low energy shift register by means of pulsed latches. The field and extend vigour consumption of shift register lowered with the aid of pulsed latches. The timing problem took place in among pulsed latches these are solved by means of by way of more than one non-overlap postponed pulsed clock signals rather than a single pulsed clock sign. A small number of the pulsed clock signals is utilized by aligning the latches to a number of sub shifter
registers and by way of further temporary storage latches. A 256-bit shift register was fabricated by means of a 0.18µm CMOS process with VDD = 1.8V. Its core area is6600µm². It consumes 1.2 mw at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops. ACKNOWLEDGMENT The chip fabrication was supported by the IC Design Education Center (IDEC). REFERENCES [1] P. Reyes, P. Reviriego, J. A. Maestro, and O. Ruano, New protection techniques against SEUs for moving average filters in a radiation environment, IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp. 957 964, Aug.2007. [2] M. Hatamian et al., Design considerations for gigabit ethernet 1000 base-t twisted pair transceivers, Proc. IEEE Custom Integr. CircuitsConf., pp. 335 342, 1998. [3] H. Yamasaki and T. Shibata, A real-time image-feature-extraction and vector-generation vlsi employing arrayed shift register architecture, IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 2046 2053, Sep. 2007. [4] H.-S. Kim, J.-H. Yang, S.-H. Park, S.-T. Ryu, and G.-H. Cho, A 10-bit column-driver IC with parasitic-insensitive iterative charge-sharing based capacitor-string interpolation for mobile active-matrix LCDs, IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 766 782, Mar. 2014. [8] H. Partovi et al., Flow-through latch and edgetriggered flip-flop hybrid elements, IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 138 139, Feb. 1996. [9] E. Consoli, M. Alioto, G. Palumbo, and J. Rabaey, Conditional push-pull pulsed latch with 726 fjops energy delay product in 65 nm CMOS, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 482 483. [10] V. Stojanovic and V. Oklobdzija, Comparative analysis of masterslave latches and flip-flops for high-performance and low-power systems, IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536 548, Apr. 1999. J. VIJAYA SAGAR has received his B.Tech Degree in Electronics &Communication Engineering from JNTU University, Kakinada, India. Presently pursuing M.Tech(VLSI System Design) from Annamacharya Institute of Technology & Sciences, Kadapa, A.P., India. His research interest include VLSI, Digital Signal Processing. T. VIJAYA NIRMALA, has received her M.Tech Degree from JNTU Anantapur, She is working as Assistant Professor in the Department of Electronics & Communication Engineering, Annamacharya Institute of Technology & Science, Kadapa, A.P., India. Her areas of interests are VLSI, Digital Image Processing and Communication Systems. [5] S.-H. W. Chiang and S. Kleinfelder, Scaling and design of a 16-megapixel CMOS image sensor for electron microscopy, in Proc. IEEE Nucl. Sci. Symp. Conf. Record (NSS/MIC), 2009, pp. 1249 1256. [6] S. Heo, R. Krashinsky, and K. Asanovic, Activity-sensitive flip-flop and latch selection for reduced energy, IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 15, no. 9, pp. 1060 1064, Sep. 2007. [7] S. Naffziger and G. Hammond, The implementation of the nextgeneration 64 b itanium microprocessor, in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 276 504.
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