Examples of FPL Families: Actel ACT, Xilinx LCA, Altera AX 5 & 7 Actel ACT Family ffl The Actel ACT family employs multiplexer-based logic cells. ffl A row-based architecture is used in which the logic cells are arranged in rows with horizontal routing channels between adjacent rows of logic cells. Interconnect cell 2
ACT odules ffl ACT FPGAs use a single type of logic module. Actel ACT (a) A A B B B odule odule odule F F A 3 F A F '' F F2 C 2 B B F2 F2 '' B 3 A 3 '' O O B (b) (c) (d) F F=(A B)+(B' C)+ (a) An Actel FPGA. (b) An ACT logic module. (c) An implementation of an ACT logic module using pass transistors. (d) An example of function implementation by an ACT logic module. 3 ACT 2 and ACT 3 odules ffl Both ACT 2 and ACT 3 FPGAs use two types of logic module. C-odule -odule (ACT 2) -odule (ACT 3) A B Y OU T A B Y E A B Y E B CLK B CLK (a) (b) (c) E (sequential element) E C2 C Z master latch Z slave latch CLK C2 C combinational logic for clock and clear flip-flop macro CLK C (d) (e) (a) The C-module used by both ACT 2 and ACT 3 FPGAs. (b) The ACT 2 -module. (c) The ACT 3 -module. (d) Equivalent circuit of the E. (e) The sequential element configured as a positive-edgetriggered flip-flops. 4
ffl A row-based architecture. Routing Architecture of ACT Family ffl Each horizontal channel consists of a number of routing tracks. ffl ome routing tracks are segmented where adjacent segments can be connected through antifuses to form longer lines. ffl There are also some vertical tracks running through the logic modules and horizontal channels. 5 FILENAE.APP=6822FG3.P I/O module Antifuses Vertical segments egmented routing channels Rows of logic modules Routing architecture of an Actel ACT FPGA. 6
Xilinx LCA Family ffl The Xilinx LCA family employs LUT-based logic cells. ffl A symmetrical architecture is used. Interconnect cell 7 Configurable Block of LCA Family ffl We consider the XC4 devices for an example. ffl The XC4 FPGAs use a single type of configurable logic (CLB). ffl Each CLB contains two 4-input LUTs that feed a 3-input LUT. This allows a CLB to implement any two logic functions with four or less variables, or some function with five or more variables. ffl A CLB can also be configured to be used as memory e.g. as two 6 memory RAs. ffl The outputs of the function generators can be optionally stored in flip-flops inside a CLB. 8
6-37 Figure 6-32 implified iagram of a Xilinx Configurable Block (Adapted with permission of Xilinx, Inc.) G G2 G3 G4 Look up Table for G' 6 bits of RA G' Look up Table for H' H' H IN /R EC UX IN F' G' H' /R Control UX PRE EC Y F F2 F3 F4 Look up Table for F' K (CLOCK) 6 bits of RA 8 bits of RA F' UX G' H' UX IN F' G' H' /R Control UX PRE EC Y X UX F' H' X - RA cell 9 Routing Architecture of LCA Family ffl A typical Xilinx LCA FPGA consists of a two-dimensional of CLBs with horizontal routing channels between rows of s and vertical routing channels between columns. ffl Routing tracks are segmented which can be interconnected inside the switch matrices. ffl Each interconnect point inside a switch matrix is formed by 6 pass transistors to allow connections between adjacent segments and/or between the vertical and horizontal lines that meet there.
T-53 Xilinx XC4 FPGA tructure (Adapted with Permission of Xilinx, Inc.) Long lines ingle length - Input/Output Block (IOB) - Configurable logic (CLB) - witch matrix a b c d e (a) (b) (a) A switch matrix. (b) Example of connections made through a switch matrix. 2
Altera AX 5 & 7 Family ffl The Altera AX family employs PAL-based logic cells. ffl The logic cells are called macrocells. ffl A hierarchical PL architecture is used where the macrocells are grouped into larger s called logic s. PL Chipwide interconnect 3 Array Block of AX Family ffl Each logic (LAB) contains 6 macrocells. ffl A simplified macrocell showing its basic PL-like combinational logic structure:... ffl ee Fig. 3.5 of text for the complete structure of a macrocell. ffl In addition to the basic combinational logic structure shown above each macrocell has a flip-flop there are special connections that allow sharing of product terms between different macrocells in the same LAB. 4
Routing Architecture of AX 5 & 7 Family ffl The LABs are interconnected by a chipwide interconnect called programmable interconnect (PIA). ffl The PIA acts as a global bus and is built such that the connections between different pairs of LABs all have the same delay. 5 T-5 Altera AX 7 tructure (Reprinted with Permission of Altera Corporation, Altera Corp., 99) I/O control Programmable interconnect I/O control I/O control I/O control 6
Comparison of FPL Families Actel ACT 3 Xilinx XC4 Altera AX 7 Programming antifuse RA EPRO technology Architecture row-based symmetrical hierarchical-pl cell type multiplexer-based LUT-based PAL-based Interconnect segmented channels segmented channels with programmable interconnection switch matrices architecture Interconnect variable variable fixed delay Basic C-module and Configurable 6 macrocells logic cells -module Block (CLB) in a LAB cell C-module: 4: UX, 3 LUTs, acrocell: contents 2-input OR, 2-input AN. 2 flip-flops, 5 ANs, OR, EXOR, -module: 4: UX, 2-input OR, UXes. flip-flop, 3 UXes. 2-input AN, latch/ flip-flop. Combinational One. Two or one. ultiple wide input functions ost 3-and 4-input Any two 4-input functions, functions per LAB per logic cell functions. or one selected function of <= 9 inputs. Basic 4 +96 C (A45) 64 CLBs (XC42XL) 32 macrocells (EP732) logic cells to to to per chip 697 +68 C (A4) 336 CLBs (XC485XL) 256 macrocells (EP7256E) 7