CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1
Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback The outputs and the next state of the sequential circuit depend on the external inputs of the combinational circuit and the present state. Memory content changes every T seconds Memory elements contain all the information about the past, necessary t o account for the system s future behavior Inputs Combination al circuit Next state Memory elements Present state Outputs clock 2
Asynchronous Synchronous Sequential Circuits. Asynchronous vs Synchronous State changes can be affected at any instant of time Become active the moment any input changes E.g. SR Latch State changes are controlled by a Clock Clock allows ordering of events Parts of the computer are made of synchronous sequential circuit change state clock period T clock frequency 1/T 3
Sequential Circuits Synchronous Circuits The synchronization may be achieved by a clock on: The Rising Edge The Falling Edge The High Level The Low level Synchronous sequential circuits that use clock pulses at the input of the memory device are called clocked sequential circuits. The memory devices used in clocked sequential circuits are Flip-Flops (FF). 4
Flip-Flops (FF) Flip-Flop properties A FF is a cell capable of storing 1 bit of information. It has 2 outputs one for the normal value and one for the complemented The FF maintains its state until directed by the CLK pulse to switch its state. Flip-Flop types : There are 4 basic flip-flops: RS, T, D, and JK. T, D, and JK are basically synchronous. The RS can be either asynchronous or synchronous can be converted to synchronous 5
Flip-Flops Latch : output changes as input changes while the clock pulse is in the logic 1. (Level triggered FF) Flip-flop : output only changes at clock edge (Edge triggered FF) 6
RS Flip-Flop The device is said to be: SET when Q output = 1 And RESET when Q output = 0 Block diagram R S Q - Q + 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 Timing Diagram 1 1 0 X 1 1 1 X Truth table 7
RS Flip-Flop with EN/CP (1) Can also have an implementation with an enable/clock S Q S Q C C R Ǭ R Ǭ Rising edge graphic symbol Falling edge graphic symbol If the En/Cp =0 device is not active the outputs of the NAND s remain at logic level 1 output does not change when the S, R inputs change. Therefore only when En/Cp =1 can an input be applied 8
D Flip-FLOP (1) Eliminate indeterminate state in SR latch C=1, output value is equal to D (transparent) Output Q is retained until the clock is enabled again, even though the data input is changed 9
D Flip-FLOP (2) A rising edge triggered D-FF stores a value on the positive edge of C. 10
J-K Flip-Flop (1) It is a refinement of the SR flip-flop. The indeterminate state of the SR type is defined in the JK type. Performs three operations Set (J=1,K=0), Reset (J=0,K=1), Complement (J=K=1) Characteristic Table Graphic symbol J K Q(t+1) Operation 0 0 Q(t) No change 0 1 0 Clear to 0 1 0 1 Set to 1 1 1 Q(t) Complement 11
J-K Flip-Flop (2) 12
T Flip-Flop The T Flip-Flop is obtained when JK inputs are connected. Characteristic Table Graphic Symbol T Q(t+1) operation 0 Q(t) No change 1 Q(t) Complement 13
Asynchronous Inputs J, K are synchronous inputs Effects on the output are synchronized with the CLK input. Asynchronous inputs operate independently of the synchronous inputs and clock Set the FF to 1/0 states at any time. 14
Characteristic Tables and Equations(1) Flip-Flop characteristic tables: Q(t): present state prior to the application of a clock edge Q(t+1): next state one clock period later Q(t+1)=JQ +K Q 15
Characteristic Tables and Equations(2) Q(t+1)=D Q(t+1)=TQ +T Q 16
Flip-Flops Excitation Tables Q - Q + S R 0 0 0 x 0 1 1 0 1 0 0 1 Q - Q + J K 0 0 0 x 0 1 1 X 1 0 x 1 Q - Q + D 0 0 0 0 1 1 1 0 0 Q - Q + T 0 0 0 0 1 1 1 0 1 1 1 x 0 1 1 x 0 1 1 1 1 1 0 SR FF JK FF D FF T FF Q(t) or Q - The State I have now. Q(t+1) or Q + : The state I want to have the next rising (or falling) edge What must I set the control bit to go from Q(t) to Q(t+1)? 17
Summary Flip-flops are powerful storage elements They can be constructed from gates and latches! D flip-flop is simplest and most widely used Asynchronous inputs allow clearing and presetting the flip-flop output Multiple flip-flops allow data storage The basis of computer memory! Combine storage and logic to make a computation circuit 18
Sequential Circuits Analysis A sequential circuit is an interconnection of FFs and gates. It consists of a combinational circuit and a number of FFs. External outputs of the sequential circuit are a function of both external inputs and the present state of the FF The next state of FFs are a function of their present state and external inputs. 19
Analysis of Clocked Sequential Circuits Behavior of clocked sequential circuit is determined from input, output and present state Output and next state are a function of input and present state There are different representations for specifying the nextstate condition in terms of the present state and inputs State equations State table State diagram 20
Analysis of Clocked Sequential Define the input equations of FFs Circuits Draw the state table it contains the following Present state Inputs - Next state - Outputs A sequential circuit with m FFs, n input variables and p output variables the state table will contain m columns for the present state, n columns for input variables, m columns for next state, p columns for outputs. It will have 2 n+m rows Draw the state diagram 21
State Equations (Transition Equations) Specifies the next state and output as a function of the present state and inputs A(t+1)=A(t)x(t) + B(t)x(t) B(t+1)=A (t)x(t) y(t)=(a(t)+b(t))x (t) t+1: one clock edge later 22
State Table (Transition Table) It relates the output and the next state of the FF to the input and the current state of FF. 23
State Diagram A kind of flow diagram Can be derived from state table State-circle, transition-line, I/O 24
Design Procedure Design steps 1) Derive a state diagram or state table 2) Reduce the number of states if necessary 3) Assign binary values to the states 4) Obtain the binary-coded state table 5) Choose the type of flip-flops to be used 6) Derive the flip-flop input equations and output equations 7) Draw the logic diagram Excitation tables are used. 25
Design Procedure: Example Example 1: Implementing D FF with a J-K FF: 1. Start with K-map of Q+ = f(d, Q) 2. Create K-maps for J and K with same inputs (D, Q) 3. Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map E.g., D = Q = 0, Q+ = 0 then J = 0, K = X 26
Flip-Flop Applications Parallel Data Storage Frequency Division Counting 27
Sequential Logic Registers Properties Shift Registers Applications Binary Counter Properties Memory Unit Properties RAM ROM 28
Registers A Register is a chain of flip-flops in cascade and gates. Gates control when and how new information is transferred into the register. They produce control inputs. Each FF holds one information bit. n-bits registers needs n FF. The more simplest registers contains no external gates. Register load is the transfer of new information into a register. Parallel loading : If the bits are loaded simultaneously at the same clock pulse. 29
A basic Register (1) Basic registers are easy to build. We can store multiple bits just by putting a bunch of flip-flops together! Internal implementation with D flip flop Notes: All the flip-flops share a common CLK and CLR signal Bits are stored in parallel If CLR =1 then all D FF outputs are cleared. 30
A basic Registers (2) The clock is very important from a timing standpoint The registers must all accept their new input values and change their storage elements at the same time. A synchronous sequential circuit cannot change state unless the clock pulses. The same clock signal is tied into all four D flip flops. 31
Adding a parallel load operation The input D3-D0 is copied to the output Q3-Q0 on every clock cycle. How can we store the current value for more than one cycle? Let s add a load input signal LD to the register. If LD = 0, the register keeps its current contents. If LD = 1, the register stores a new value, taken from inputs D3-D0 32
Adding a parallel load operation Internal implementation with D flip flop LD = 0 no change LD = 1 loading 33
Basic Shift Register Shift register consist of arrangements of flip-flop and are important in applications involving the storage and transfer of data in a digital system. A register capable of shifting its binary information in one direction is called Unidirectional Register. A register capable of shifting its binary information in both direction is called Bidirectional Register. Serial in/serial out shift registers Serial in/parallel out shift registers Parallel in/serial out shift registers Parallel in/parallel out shift registers Bidirectional shift registers Serial input determines what goes into leftmost FF. Serial output determines what comes from rightmost FF. 34
Shift Register A register capable of shifting its binary information in one or both direction. Chain of flip-flops in cascade. Unidirectional- one direction only. Figure 2-8 page 53 Bidirectional- both directions. Figure 2-9 page 53 Serial input determines what goes into leftmost FF. Serial output determines what comes from rightmost FF. 35
Shift Register A shift register shifts its output once every clock cycle. SI is an input that supplies a new bit to shift into the register. For example, if on some positive clock edge we have: SI = 1 Q0-Q3 = 0110 then the next state will be: Q0-Q3 = 1011 The current Q3 (0 in this example) will be lost on the next cycle. 36
Basic data movement in shift registers A register is a digital circuit with two basic functions: Data storage and data movement 37
Bidirectional Shift Register They contains Inputs for clock pulses Shift right operation with a serial input associated with it Shift left operation with a serial input associated with it. Parallel load operation and n input lines associated with it n-output parallel lines A control state that leaves the information unchanged Multiplexers are used to select one of three operation: Shift right (or down) Shift left (or up) No change Parallel load 38
Bidirectional Shift Register 4-bit universal 39
Serial data transfer One application of shift registers is converting between serial data and parallel data. Computers typically work with multiple-bit quantities. ASCII text characters are 8 bits long. Integers, single-precision floating-point numbers, and screen pixels are up to 32 bits long. But sometimes it s necessary to send or receive data serially, or one bit at a time. Some examples include: Input devices such as keyboards and mice. Output devices like printers. Any serial port, USB or Firewire device transfers data serially. 40
Receiving serial data To receive serial data using a shift register: The serial device is connected to the register s SI input. The shift register outputs Q3-Q0 are connected to the computer. The serial device transmits one bit of data per clock cycle. These bits go into the SI input of the shift register. After four clock cycles, the shift register will hold a four-bit word. The computer then reads all four bits at once from the Q3-Q0 outputs. 41
Sending data serially To send data serially with a shift register, you do the opposite: The CPU is connected to the register s D inputs. The shift output (Q3 in this case) is connected to the serial device. The computer first stores a four-bit word in the register, in one cycle. The serial device can then read the shift output. One bit appears on Q3 on each clock cycle. After four cycles, the entire four-bit word will have been sent. 42
Universal Asynchronous transmitter (UART) Receives data in serial format, converts data to parallel format and place them on the data bus Also accepts data from data bus, converts data to serial format and transmits to external device 43
Registers summary A register is a special state machine that stores multiple bits of data. Several variations are possible: Parallel loading to store data into the register. Shifting the register contents either left or right. Counters are considered a type of register too! One application of shift registers is converting between serial and parallel data. Registers are a central part of modern processors. 44
Binary Counter A register that goes through a predetermined sequence of state upon the application of clock pulses. n-bit binary counter contains n FFs. The counter may be controlled with an enable signal (external input) Usually employs JK or T flip flops for complementing capability. After each count the lower bit is always complemented Other bits are complemented if and only if its lower bits are 1. 45
Finite State Machine Specify the problem with words (e.g. Design a circuit that detects three consecutive 1 inputs) Assign binary values to states Develop a state table Use K-maps to simplify expressions Flip flop input equations and output equations Create appropriate logic diagram Should include combinational logic and flip flops 46
Application Used for counting the number of occurrence of an event. Useful for generating timing signals to control the sequence of operations. Control the number of steps in a sequence of fixed actions (a sequencer) Generate timing signals (frequency divider, etc.) 47