Nano-Imprint Lithography Infrastructure: Imprint Templates John Maltabes Photronics, Inc Austin, TX 1
Questions to keep in mind Imprint template manufacturability Resolution Can you get sub30nm images? Image Placement Can you place them where you want? Defectivity Can you meet the necessary defect spec Inspection Can you verify 2
Outline Introduction Building a nano-imprint template Processing/Inspection Defect Characterization Outlook Summary 3
Current use and capabilities Template quality today is able to be used for many applications LED, diffractive optics, MEMS, CMOS unit process development, dual damascene structures CD and depth control better than 10% Short term strategy is to build defect tolerant parts Imprint user development Template manufacturing development Vehicles for process and defect learning Drivers for improvements in cleaning, inspection and repair 4
Background: Added to a digital camera s CMOS/CCD image chip to improve optical collection efficiency Challenge: Patterning of high packing density aspheric lens arrays requiring no etching Micro Lens Arrays Template Imprinted Lens Array 5
What affects template quality Three main issues to template production Lithography resolution Quartz etch uniformity Backend verification Additional issues include pedestal etch platform and template dicing/polishing Ultimate GOAL CMOS quality templates 6
4 templates on a standard 6025 photomask substrate (top-down view) 6025 Fused Silica Substrate 65 mm x 65 mm Template Active Imprint Area: 25 mm x 25 mm 7
Typical Template process flow Binary Mask, 1st Resist Chrome Quartz Expose Develop Etch Blank - STD Binary Material -Expose E-Beam or ALTA 3500 DRY CR Etch 2nd Level Write Write Template Self Aligned transfer -Re-Coat resist -Expose Develop Depth CD Spec -Chrome Etch to remove Field Chrome -Pedestal and Moat Etch -Quartz Dry Etch 200 nm +/- 25 nm -I-Line Resist non-critical -ALTA 3500 expose non-critical +/- 0.5 um -Wet Chrome etch -Wet or Dry Qtz Etch 15 um deep, +/- 0.1 um -Final Chromeless S-FIL Template -Strip Resist and Chrome -Dice to final Template dimensions 8
CMOS logic pattern Thru quartz etch LER transfers from resist to quartz Commercially available mature PCAR 9
Photronics Contacts Test vehicle designed to have range from fully dense to fully isolated contacts and SRAM and DRAM arrays Designed for VSB tool @ 60, 70 and 80nm 10
Minimum Contact Experiments 50nm 65nm 70nm Contacts etched into 15nm Chrome, Etched to 100nm depth in quartz 11
Imprinted Features This space measures ~56nm The line measures ~95nm DNP Imprint Results M1 70nm Logic 80nm 12
Faithful Qz etch profiles 13
Imprint results Contact Test 50, 60, 65nm etched contacts 14
Image Placement Template: 25 mm x 25 mm Uncorrected Corrected Materials: Thin PCAR/15 nm Cr Writing Tool: NuFlare 4500 15
Cleaning Current process for templates Similar to AAPSM clean process Spin/spray process Using standard clean chemistry New fixtures designed for 65mm form factor Limit of cleaning capability for templates not known yet May require adoption of new clean techniques developed for EUV blank cleaning Must be able to remove particles << MFS on template 16
Current Status of Inspection KLA 5XX system used to inspect templates through the manufacturing process 6x6 form factor Cr etch, quartz etch, mesa etch 65mm form factor dice and polish, clean, use Feature sizes inspected are on the order of standard reticle defect sizes 17
Template defects (KLARITY Defect) 18
SEM Images of Template Defects found on 576 inspection 19
Defect Characterization and reduction Tomcat test vehicle Approach 270nm minimum feature size rule out false defects Inspect using KLA SLF 150nm pixel at each fabrication step to map defectivity Post Cr etch, Qz etch, Mesa etch, dice and polish, imprint As defectivity improves, move to smaller pixel sizes 20
Tomcat Process Route Template defect inspection ordered at four steps 1 st or Primary write (imprint pattern) 2 nd Level write (mesa) Dicing Prep Resist Cr Quartz/SiO 2 1000Å 5000Å NTAR7 6.35 mm 15μm Litho PEB DEV Cr Etch Resist Strip Quartz Etch Coat Litho DEV Cr Strip BOE (Mesa) Resist Strip Coat Dice Resist Strip/Clean Cr Strip Clean Imprint Inspection Inspection Inspection Inspection Inspection 21
Tomcat Inspection after BOE etch Cause: pinholes in 2 nd level resist 22
es32 E-beam Inspection es32 released, in volume production Key features for potential imprint inspection application: Smaller pixel size (25nm) Configurable low beam current (1-25nA) with higher resolution MRI (master reference inspection aka golden die) Allows 2-die per template random inspection Stepping stone to possible D:DB MxB: context-based binning of defects Allows hot-spot areas to be binned and studied in more detail 23
Low-res review images of defects on Al-coated wafer 24
Low-res review images of defects on Al-coated wafer 25
High-res review images of defects on Al-coated wafer 26
High-res review images of defects on Al-coated wafer 20nm 20nm 27
Resist wafer: Inspection defect map and swath image 28
Resist defects: low-res review es32 E-beam Inspection 29
Resist defects: high-res review es32 E-beam Inspection 30
E-beam Die-to-Database Inspection Imprinted Test Patterns Tight spaces begin to bridge at 80 nm and 70 nm Clean 70 nm Metal 1 Pattern Pixel Pixel Address: 3 nm nm Threshold Criteria: 20 20 nm nm 70 nm Logic Pattern 31
NGR2100 Inspection Results: Metal1 Logic -9.95 5.65-5.6-5.55-5.5-5.45-5.4-5.35-5.3-5.25-5.2-5.15 100 nm 90 nm -10-10.05 80 nm 70 nm -10.1-10.15-10.2-10.25-10.3-10.35-10.4 102nm -10.45-5.15 0.45-10.4-10.35-10.3-10.25-10.2-10.15-10.1-10.05-10 -9.95 100 nm 90 nm -5.2-5.25 80 nm 70 nm -5.3-5.35-5.4-5.45-5.5-5.55 102nm -5.6-5.65 32
Direct Inspection of Fused Silica SEM 40 nm Metal 1 Test Pattern GDS Overlay Pixel Pixel Address: 3 nm nm Threshold Criteria: 20 20 nm nm 40 nm Programmed Defect 33
Direct Inspection of Fused Silica: Short SEM With GDS overlay 5 nm programmed defect and a 20 nm short 34
Before repair Rave LLC: Subtractive Repair Quartz Line Quartz defect After AFM repair 300 nm defect 50 nm defect 50 nm trench 35
NaWoTec: Additive SiO 2 Repair 200 nm 100 nm Before Repair After Repair 36
Questions to keep in mind Imprint template manufacturability Resolution Can you get sub30nm images? Yes with spot beam tools Image Placement Can you place them where you want? Yes -shown on current generation tools Defectivity Can you meet the necessary defect spec More work necessary must use techniques already developed for other technologies Inspection Can you verify -Yes Secondary and direct inspection quality needs to be quantified. Improvements in inspection speed 37
Summary Quartz templates are being built today Resolution on VSB tools ~ 50nm available Gaussian beam ~ 20nm Work has started on defect source analysis From binary write thru imprint and clean Defect reduction methodology will improve overall process Inspection and cleaning remain the biggest challenges KLA and NGR have demonstrated early e-beam inspection capability Quartz repair both additive and subtractive has been demonstrated 38