CS302-Digal Logic Design Leture wise Questions& Answers Prepared By Virtualians.pk. Lecture no 23:

CS302-Digal Logic Design Leture wise Questions& Answers Prepared By Virtualians.pk Q) What is Edge-Triggered Flip-Flop? Lecture no 23: Flip-Flops are synchronous bi-stable devices, known as bi-stable multivibrators. Flip-flops have a clock input instead of a simple enable input as discussed earlier. The output of the flip-flop can only change when appropriate inputs are applied at the S and R inputs and a clock signal is applied at the clock input. Flip-flops with enable inputs can change their state at any instant when the enable input is active. Digital circuits that change their outputs when the enable input is active are difficult to design and debug as different parts of the digital circuit operate at different times. In Synchronous systems, the output of all the digital circuits changes when a clock signal is applied instead of the enable signal. The change in the state of the digital circuit occurs either at the low-tohigh or high-to-low transition of the clock signal. Since the transition of the clock signal is for a very short a precise time intervals thus all digital parts of a Digital system change their states simultaneously. The low to high or high to low transition of the clock is considered to be an edge. Three different types of edge-triggered flip-flops are generally used in digital logic circuits. S-R edge-triggered flip-flop D edge-triggered flip-flop J-K edge-triggered flip-flop Q)Define Master-Slave Flip-Flops? Master-Slave flip-flops have become obsolete and are being replaced by edge-triggered flip-flops. Master-Slave flips have two stages each stage works in one half of the clock signal. The inputs are applied in the first half of the clock signal. The outputs do not change until the second half of the clock signal. As mentioned earlier the use of edge-triggered flip-flip is to synchronize the operation of a digital circuit with a common clock signal. The master-slave setup also allows digital circuits to operate in synchronization with a common clock signal. The Master-Slave flip-flop is composed of two parts the Master and the Slave. Both the Master and the Slave are Gated S-R flip-flops. The Prepared By:Irfan Khan(Chief Admin) Page 1

Master-Slave flip-flop is not synchronised with the clock positive or negative transition, rather it known as a pulse triggered flip-flop as it operates at the positive and negative clock cycles. Q)List the Names of Flip-Flop Operating Characteristics? The performance of the flip-flop is specified by several operating characteristics mentioned in the data sheets of the flip-flops. The important operating characteristics are Propagation Delay Set-up Time Hold Time Maximum Clock frequency Pulse width Power Dissipation Q)What is meant by Maximum Clock Frequency? A flip-flop can be operated at a certain clock frequency. If the clock frequency is increased beyond a certain limit the flip-flop will be unable to respond to the fast changing clock transitions, therefore the flip-flop will be unable to function. The maximum clock frequency f max is the highest rate at which the flip-flop operates reliably. Q) What is Master-Slave flip-flop with some examples? Basically Master Slave flip-flop is composed of two parts the Master and the Slave and it has two stages each stage works in one half of the clock signal. Both the Master and the Slave are gated S-R flip-flops and it is not synchronized with the clock positive or negative transition rather it known as a pulse triggered flipflop as it operates at the positive and negative clock cycles. For example The outputs from Q and Q from the "Slave" flip-flop are fed back to the inputs of the "Master" with the outputs of the "Master" flip-flop being Prepared By:Irfan Khan(Chief Admin) Page 2

connected to the two inputs of the "Slave" flip-flop. This feedback configuration from the slave's output to the master's input gives the characteristic toggle of the JK flip-flop. Q)What is Flip-flop? Lecture no24: A flip-flop or latch is a circuit that has two stable states and can be used to store state information. Flip Flop is a bitable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs D flip-flop The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change Q)What is Synchronizing Asynchronous inputs using D flip-flop? In synchronized digital systems all the circuits change their state with respect to a common clock and all the input and output signals are synchronized. However, external inputs that are applied to digital circuits through switches and keypads are not synchronized with the clock. The asynchronous inputs can occur at any instant of time.an asynchronous input applied through the switch can cause incomplete or partial pulses at the output of the AND gate.a D-flip-flop synchronizes the input asynchronous signal such that the output of the AND gate has complete clock pulses Prepared By:Irfan Khan(Chief Admin) Page 3

Q)Difference between D flip flop and Jk? The D Flip-Flop captures the data on the D-input at the rising edge of the clock and propagates it to the Q and Q-Bar outputs. The JK is more flexible. At the clock edge it can SET, CLEAR, HOLD, or TOGGLE. Since it hat 2 inputs labeled J and K it can do four things instead of two for the D-Flip-Flop (SET and CLEAR). Lecture no25: Propagation Delay It is the interval of time when the input is applied and the output changes. Set-up time The minimum time required for the input logic levels to remain stable before the clock transition occurs is known as the Set-up time. Hold Time The minimum time for which the input signal has to be maintained at the input is the Hold time of the flip-flop. What is Power Dissipation? A flip-flop consumes power during its operation. The power consumed by a flipflop is defined by P = Vcc x Icc. Q)What is Mono-stable Device? A mono-stable device only has a single stable state and it remains in its stable state. It temporarily changes to its unstable state when it is triggered. It remains in its unstable state for a predetermined length of time and then it Prepared By:Irfan Khan(Chief Admin) Page 4

Q)Difference b/w Nonretriggerable One-Shot and Retrigger able One- Shot? Nonretriggerable One-Shot It is triggered to its unstable state. The One-Shot output remains in the unstable state for a fixed period of time on each trigger input. The One-Shot will have to return to its stable state before it can be triggered again Retrigger able One-Shot This operation is very similar to that of the Nonretriggerbale One-Shot except that the retrigger able One-Shot will retrigger even if it is in its unstable state. Q) Compression Of Edge Triggered, Triggered D, Triggered J-K flip Flops? Edge Triggered Flip Flops Edge Triggered Flip Flop : Changes its state either at the posutive edge or negative edge of the clock pulse on the control input Edge Triggered D Flip Flops; The Operations of a D Flip Flop is much simpler.it has only one input addition to the clock.it is very useful when a single data bit is to be stored,if ther is high on the input when a clock pulse is applied the flip flop sets nd stored a 1.if there is a low on the D input when a clock pulse is applied,the flip flop Resets nd stores a 0 Edge Triggered J-k Flip flop: This Flip flop has no invalid state, The output Change to the positive state when both J and K inputs are high. Q)what is transparent mode? explain it? Prepared By:Irfan Khan(Chief Admin) Page 5

D-latch operates in the two modes one is transparent mode and second is latched mode, it is basically switching mode of circuit and D-latch operates in the transparent mode when the enable signal is activated and latched mode when the enable signal is inactive. Q)How timing graph is made? Basically the timing diagram of any gate operation is made according to the value which is given in truth table and it describes the response of the any gate in a certain period of time with respect to the changing input. The timing diagram describes the operation of J-K flip-flops for multiple interval of time (t1 to t8) and It is operated according to the inputs (Clock input) and output F0 and F1. Lecture no26: Q)What u know about "The 555 Timer"? The 555 Timer is a versatile and widely used device which can be configured as a mono-stable One-Shot or as an Astable multivibrator. An Astable multivibrator is known as an Oscillator which does not have any stable state. Therefore it continuously changes from one unstable state to the other without any external trigger. Q)What are Counters? Counter circuits based on flip-flops are widely used in Digital Systems. Besides counting, these counters are used as frequency dividers and with minor changes in the circuit they are used as shift registers. Counters are classified as Asynchronous and Synchronous counters. Asynchronous counters as the name indicates are not Prepared By:Irfan Khan(Chief Admin) Page 6

triggered simultaneously. The multiple flip-flops that are connected together to form a counter circuit do not receive the triggering clock signal simultaneously. The flip-flop that represents the least significant count bit of the n-bit counter is connected to the clock signal, the remaining flip-flops receive their clock signals form the outputs of the preceding flip-flops connected in the counter circuit. The clock signal thus ripples through successive flip-flops. Synchronous counters on the other hand have all the clock inputs of the multiple flip-flops connected to a common clock signal. All the flipflops in a Synchronous counter receive clock signals simultaneously Q)In Down Counter which ic are used in circut? 4 bit Synchronous Decade Counter use AND, OR gate for connecting 4 flip flop when we connect 4th flip flop we use combination of two AND gate and One OR gate instead of only AND gate kindly define.? Up and down counter are the part of asynchronous and synchronous counter and it counts depend upon the sequence. It is further categorized into number of states. It can increment output count value at each clock transition or decrement its count value at each clock transition. Q) Explain Asynchronous Counters and his Application in real life? Up and down counter are the part of asynchronous and synchronous counter and it counts depend upon the sequence. It is further categorized into number of states. It can increment output count value at each clock transition or decrement its count value at each clock transition. Prepared By:Irfan Khan(Chief Admin) Page 7

Q)how can we get the value of latches when q is initial set to 1?what is meant bt Qt and Qt+1? Basically an active high input S-R latch is formed with two cross-coupled NOR gate and an active low input S-R latch is formed with two cross-coupled NAND gates. The latches have two states Set and Reset, Set means that Q output is high (active low) and Reset means that Q output is low (active low). Q t+1 means the next state output and Q t means the previous state output. The Truth-Table of NAND based S-R Latch shows this operation Set Reset Output 0 0 Invalid (It is invalid to have low state for both Set and Reset for NAND latches, produces Q=Q =1 0 1 Q=1 1 0 Q-0 1 1 No change (the next state output Qt+1 remains the same as the previous state output Qt.) The Truth-Table of NOR based S-R Latch shows this operation Set Reset Output 0 0 No change 0 1 Q=0 1 0 Q-1 Invalid (It is invalid to have high state for both Set and Reset for NOR latches), produces Q=Q =0 1 1 Q)What is Latches and Flip flop? Latches are used as temporary buffers whereas flip flops are used as registers. A D latch is level triggered and it will follow the input as long as the gate is true. Once the gate goes false, the output will stay at the last known value. A D flip flop is edge triggered and the output will not change until the edge of the gate. Prepared By:Irfan Khan(Chief Admin) Page 8

At that point, the output will go to the state of input and then it will stay at that value. Lecture no27: Q)Down Counter with truncated sequence? A down counter can be configured to count down a truncated sequence, similar to an up-counter which can count up to any truncated sequence. A down counter counts down from the maximum count value to some predefined count value which is the last count value in the truncated sequence. On reaching the last count value the downcounter is preset to the maximum count value instead of clearing the counter to zero count value as done in the case of an up-counter Q)What is 4-bit Synchronous Decade Counter? Earlier, an Asynchronous Decade counter has been discussed, which counts from state 0000 to 1001. The Asynchronous counter is cleared to state 0000 when the counter counts from 1001 to 1010. Synchronous counter can be implemented which counts from 0000 to 1001. In the synchronous counter, all the four flip-flops are connected to a common clock and are triggered simultaneously. However, instead of using the clear asynchronous inputs to clear the counter to the initial state, logic gates are used to reset the decade counter to state 0000 after it reaches state 1001. The implementation of Prepared By:Irfan Khan(Chief Admin) Page 9

the Synchronous Lecture no28: Q)What is Integrated Circuit Synchronous Counters? Instead of connecting a large number of flip-flops together to form large Synchronous counters, counter circuits available in Integrated Circuit form can be quickly connected to form large counters. The 74HC163 is a 4-bit Synchronous Counter. Figure 28.2. The counter has the following pins. 1. Parallel data inputs D0, D1, D2 and D3 2. Data outputs Q0, Q1, Q2 and Q3 3. Positive edge-triggered CLOCK signal 4. Active-low CLR input which resets the Counter output to 0000 5. Active-low LOAD input which loads the 4-bit data applied at the counter inputs 6. Active-high ENT and ENP enable inputs. For the counter to operate both the enable inputs have to be high 7. The Ripple Clock Output RCO goes high when the Counter reaches the terminal count 1111. The RCO output along with ENT and ENP enable input pins are used to cascade multiple counter ICs for implementing larger counters Q)What is Cascading Counters? It is very convenient to cascade Integrated Circuit counters together to form larger counters instead of connecting together flip-flops to implement a large counter. The enable inputs and Ripple Clock Outputs of the Integrated Circuit counters allow cascading of multiple counters together. Two, 74HC160 decade counters are Prepared By:Irfan Khan(Chief Admin) Page 10

shown connected together to divide the input frequency by 10 and 100 Q) what is Up-Down Counter? An up-down counter can increment its output count value at each clock transition or decrement its count value at each clock transition, depending upon the count mode it is configured in. The counter can be reconfigured to count in the opposite direction during its count sequence. Lecture no 29: Q) What is Integrated Circuit Up/Down Decade Counter? Implementing a 4-bit Up/Down counter by connecting flip-flops and logic gates increases the circuit size and requires many connections. The 74HC190 is a 4-bit Up/Down Synchronous Counter available in an Integrated Circuit form. Figure 29.3. The counter has the following pins. 1. Parallel data inputs D 0, D 1, D 2 and D 3 2. Data outputs Q 0, Q 1, Q 2 and Q3 3. Positive edge-triggered CLOCK signal 4. Active-low LOAD input which loads the 4-bit data applied at the counter inputs 5. Active-low CTEN counter enable input 6. The count down/up input. When the input is set to logic 1, the counter counts down and when the input is set to logic 0, the counter counts up 7. The MAX/MIN output that is set to high when the terminal count 1001 is reached when counting up or when the terminal count 0000 is reached when counting down. The MAX/MIN output is logic high for one complete cycle when a terminal count is reached. 8. The Ripple Clock Output RCO goes low when the Counter reaches the terminal count 1001 or 0000 when counting up or down respectively. The RCO output remains low during the negative half of the clock cycle. The RCO, the MAX/MIN output along with CTEN input is used to cascade multiple counter ICs for implementing larger counters. Prepared By:Irfan Khan(Chief Admin) Page 11

Q) What is Counter Decoding? In digital circuits the counter outputs are decoded using decoders or logic gates to determine when the counter is in a certain state in its counting sequence. For example, a 4-bit Modulus-16 counter counts from state 0 to state 15. A digital circuit is enabled when the count reaches count value 4, a second circuit is enabled when the count value reaches 8 and a third circuit is enabled when the count value reaches 12. A decoder using AND or NAND gates logic gates can be implemented. Q) What is Sequential Circuit (State Machine)? A general Sequential circuit consists of a combinational circuit and a memory circuit (flip-flop). In a clocked Sequential circuit the memory element has a clock input. At any given instant the memory element is in its present state. On a clock transition the output of the memory element changes to the next state. The next state is determined by the inputs applied at the memory input at the time of clock transition. The inputs to the memory which allow the memory to change its state on a clock transition are known as excitation inputs or excitation variables. The present state of the memory is represented by state variables Q)What is Timing diagram and where it is used? Yes, you have to prepare all concepts and diagrams and it will be included in exams from different logics. Basically the timing diagram of any gate operation is made according to the value which is given in truth table and it describes the response of the any gate in a certain period of time with respect to the changing input. e.g The timing diagram describes the operation of XNOR gate for 7 interval of time (t0 to t6).this operation is performed with the help of XNOR gate table which is given the inputs (A and B) and output (F), F = A B is the expression describing the operation of the two inputs XNOR Gate. Please see the figure 6.13 of handouts which indicates first inputs (both A and B are 1) and F indicates output which is 1. Prepared By:Irfan Khan(Chief Admin) Page 12

The binary pattern assigned to the symbolic states is called as the state assignment. Basically Moore and Mealy machines are used for implementing Finite State Machines which are used for the implementation of algorithms. These are used for the validation of different algorithms. We run an algorithm on these machines, and check whether it validates all the required rules or not. These are used in integrated circuits for algorithm implementation. For example Serial Bus Transfer protocols like power management and USB applications. Lecture no30: What is Frequency Counter? A frequency counter is used to measure the frequency of an input signal. The basis for the operation of a frequency counter is counting of the clock pulses in a predetermined time interval. The frequency of periodic signal is the number of cycles in a time period of one second. The frequency of the unknown signal can be calculated by counting the number of clock pulses of the unknown signal and dividing the count number by the time interval in which the clock pulses are counted. Q) What is Clocked Synchronous State Machines? The Synchronous Counters are the simplest forms of Clocked Synchronous State Machines. State Machine is a generic name given to Sequential circuits. The Sequential circuits use a clock signal to change from one state to the other and all the flipflops are connected to a single clock signal, therefore it is a Clocked Synchronous State Machine. Q)WHat quine maclacy method from basic to advance.? Karnuagh map method becomes difficult to manage when numbers of variables exceed 4.so quine-mccluskey method is used. Prepared By:Irfan Khan(Chief Admin) Page 13

In table 12.4 when comparing minterms the rule is to compare each minterm in one group with each minterm in the other group.basically comparison is used to eliminate common variables.for example Please see given below table to compare 1 with 6 In this table three values are different but we want only to eliminate single variable which is different and all rest values should be commonso ignore this camparison and it will get only those camparison which has only single value eliminate like So terms 1 and 3 forms a single term eliminating variable C,forming the product term A B D. The comparison terms 1 and 3 are marked as used in table 12.3. Similarly, terms 1 and 9 form a single term eliminating variable A, forming the product term B C D. Minterm A B C D 1 0 0 0 1 6 0 1 1 0 In table 12.5 there are 6 product terms of two variables each. Therefore the terms B D,AC,CD,BC,AD and AB are considered to be Prime Implicants. Exhaustive search for finding prime implicants has not completed. The three variable terms in table 12.4 are compared to eliminate another single variable. All terms that combine to eliminate a variable are represented in table 12.5. In table 12.6,circles are marked in cells having x, which represent minterms covered by only a single Prime Impicant (means single cross represent in column).thus the minterms 1, 6 and 8 are covered by only the Prime Implicants B D, AC and BC respectively. You may also visit the following links for detailed information Lecture no 31: Q) Concept of J-K flip flop input with explain of every 0, 1 and don`t care states in J-K flp flop. when we put a don`t care states in J-K flip flop? Apply all the possible combinations of 0 and 1 (00, 01, 10, 11) at the inputs of J-K flip flop, shown in figure 23.14 at page 232, and you will get the next output states Prepared By:Irfan Khan(Chief Admin) Page 14

by following the logic of the circuit. Explanation of every case is described at this point in the handouts. If you still face some problem, you may ask again the specific problem. We put don't care for those variables whose value does not effect the output at that particular point (The variable can have any value either 0 or 1). Q)What is Digital clock? A digital clock is a type of counter where we have to make sure that each count time is equal to a standard time like second, micro second. It displays the seconds, minutes and hours. A 60 Hz sinusoidal AC voltage is converted to 60 Hz pulse wave form. The counter counts from 0 to 59 second and then recycles to 0. Q) What is Flip-flop Transition Table? The Memory element of the Sequential circuit is implemented using flip-flops. The number of flipflops used is determined by the total number of states. When there is a clock transition at the clock input of the flip-flops they change from their present state to the next state. The Flip-flop transition table lists all the possible flip-flop input combinations which allow the present state to change to the next state on a clock transition. The flip-flop transition table is based on the flip-flop used (D, S-R or J-K). Q) how to simplify the Boolean expression of J-K input in karanugh map? Firstly draw the k-maps according to values given in Table 31.3, for example see the J2 k-maps of table 31.4a,only one group made according to only J 2 inputs of Table 31.3 and Don t care Conditions values are used and it can be considered as 0 or 1. J 2 Q2Q1/Q0 0 1 00 0 0 01 0 1 10 x x 11 x x Prepared By:Irfan Khan(Chief Admin) Page 15

J 2 =Q 1 Q 0 Lecture no32: Q)What is Sequential Circuit Implementation? The first D flip-flop is connected to toggle at each clock transition. The second flip-flop sets its output depending on the D input. The input to the second flip-flop is determined by the expression, thus at intervals t 1, t 4, t 5 and t 8 the input D 1 is at logic 1 therefore on the clock transition the output Q 1 is also set to logic 0. At intervals t 2, t 3, t 6 and t 7 the output Q 1 is set to logic 1 as the input D 1 is at logic 1. The input to the second flip-flop is determined by the expression, thus at intervals t 1, t 2, t 3 and t 8 the output Q 2 is set to 0 as D 2 input is at logic 0. At intervals t 4, t 5, t 6 and t 7 the output Q 2 is set to logic 1 as D 2 input is at logic 1 Q) What is State Diagram? The state diagram of a 3-bit Up/Down Synchronous Counter is shown in the figure. 32.2. X=0 and X =1 indicates that the counter counts up when input X = 0 and it counts down when X =1. X is used as input variable to configure the counter as up or down counter. Q)What is State Reduction? Prepared By:Irfan Khan(Chief Admin) Page 16

The number of states in a sequential circuit is closely related to the complexity of the resulting circuit. It is therefore desirable to know when two or more states are equivalent in all aspects. The process of eliminating the equivalent or redundant states from a state table/diagram is known as state reduction. Lecture no33: Q)What is Flip Flop Implementation? In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. Lecture no34: Q) Define ring counter? A ring counter is a type of counter composed of a type circular shift register. The output of the last shift register is fed to the input of the first register. The hamming distance of a Johnson counter is 1, the hamming distance of an Overbeck counter is 2. There are two types of ring counters: A straight ring counter or Overbeck counter connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring. For example, in a 4-register one-hot counter, with initial register values of 1000, the repeating pattern is: 1000, 0100, 0010, 0001, 1000.... Note that one of the registers must be pre-loaded with a 1 (or 0) in order to operate properly. A twisted ring counter, also called Johnson counter or Möbius counter (also Moebius), connects the complement of the output of the last shift register to the input of the first register and circulates a stream of ones followed by zeros around the ring. For example, in a 4-register counter, with initial register values of 0000, the repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000.... Prepared By:Irfan Khan(Chief Admin) Page 17

Q)what a Johnson counter is but how exactly does it work? A Johnson counter (aka a twisted ring counter) is a variant of the rotate left or rotate right instruction available on many processors. Instead of taking the MSB and inserting it in the LSB you take the COMPLEMENT of the MSB and insert it in the LSB. Since there is generally no concept of a carry flag in higher level languages like C, you have to test the value of the MSB, then shift, then copy the complement of the MSB back to the LSB. If you want to do it in reverse with a right shift then you test the LSB, then shift right, then copy the complement of the LSB into the MSB. What good is it you ask? Well for an n-bit counter it has a period of 2n, and it is self initializing. For a 3-bit counter with an initial value of zero the sequence of states is {000,001,011,111,110,100}*. Many designers prefer counters like this because only one bit changes for each clock pulse. If you decode the outputs, there are no hazards that occur when multiple bits change at different times as in a ripple counter, where the ouput depends on the speed of carry propagation. Now if the initial condition is either 010 or 101 then the counter will alternate between those two states so if you want the six state sequence you need to do a proper RESET. Q)What is Up and DOwn counter? Up and down counter are the part of asynchronous and synchronous counter and it counts depend upon the sequence. It is further categorized into number of states. It can increment output count value at each clock transition or decrement its count value at each clock transition. Q)What is Timing diagram? The timing diagram of any gate operation is made according to the value which is given in truth table and it describes the response of the any gate in a certain period Prepared By:Irfan Khan(Chief Admin) Page 18

of time with respect to the changing input. for example the timing diagram describes the operation of J-K flip-flops for multiple interval of time (t1 to t8) and It is operated according to the inputs (Clock input) and output F0 and F1. Q) How we can use counter as shift register? Basically shift register that allows each of the flip-flops to pass the stored information to its adjacent neighbor and shift register counter that goes through a predetermined sequence of states. There are two of the most common types of shift register counters are the Ring counter and the Johnson counter. They are basically shift registers with the serial outputs connected back to the serial inputs in order to produce particular sequences. These registers are classified as counters because they exhibit a specified sequence of states. Q) What is up and down counter? Lecture no 35: Up and down counter are the part of asynchronous and synchronous counter.it counts depend upon the sequence and it is further categorized into number of states. It can increment output count value at each clock transition or decrement its count value at each clock transition. Please visit following website for better understanding of up/down counter examples with simulation. Q) Explain Registered mode and Software mode.? Registered Modes are used in sequential logic with PLD devices and It is further categorized into active-low and active high modes.in software mode,declaration part of the input file and the logic descriptions are written. Registered Modes are selected by programming statements. The ISTYPE statement is used in the declaration part with the statements assigning PIN numbers to output variables. Lecture no 36: Q)What is besically timing diagram is? Prepared By:Irfan Khan(Chief Admin) Page 19

The timing diagrams are just a graphical (Pulse shape) representations of the inputs and the outputs just like the truth table of logical expression or circuit. Q) What is asyncronous and syncronous with example? The main difference between synchronous counter and asynchronous counter is that the 1 st one follows for the whole time of its operation a single global clock i.e. its clock input is connected to an independent clock you can see all the synchronous counters discussed in the lectures. While the asynchronous counters do not follow this at the start the clock is connected to the 1 st flip flip s clock input while for the next flip flops the clock input will be from previous flip-flops output. Q) What is tougle? Toggle is to switch from one effect, feature, or state to another by using a toggle. The example is "the play/pause button toggles between those functions". You may also take the example of auto replay of a sound track at the time when it sound track is going to end it is toggled to start of the same sound track instead of the next new sound track. Lecture no 37: Q)How to take j-k flip- flop inputs(j2,k2,j1,k1,j0,k0)? we are not using all the J-K flip-flops independently but instead you can see the 1 st flip-flop s inputs j and k both are set to 1 and then Q of the 1 st flip flop is connected to the next j and k. So the 1 st inputs are both 1 and then the next depends upon 1 st flip flops output Q and the third j and k are taken from both flip-flop 1 and flip-flop 2 s output after doing an AND operation. Q)What out the 1,2,3 repesent in timing diagram? Basically timing signals 1, 2 and 3 represent the outputs of the OR gates 1, 2 and 3 and timing signal F represents the overall output of the circuit. Prepared By:Irfan Khan(Chief Admin) Page 20

For example: In this diagram, at interval t0 the input ABCD to the circuit is 0000, the outputs of the three OR gates is 0, 0 and 0 and the circuit output is also 0. At the interval t3 the input ABCD to the circuit is 0011, the outputs of OR gates 1, 2 and 3 are 111. The output F is also a 1, which indicates adjacent 1s. At interval t6 the input ABCD to the circuit is 0110, the outputs of OR gates 1, 2 and 3 are 111. The output F is again 1 indicating adjacent 1s. Lecture no 38: Q)what is a dld and citcutes flip flop or we cane say its dld electronic? A flip-flop is a circuit that has two stable states and can be used to store state information. A flip-flop is usually controlled by control signals that can include a clock signal. The outputs usually include the complement as well as the normal output. Q) What is THE 555 TIMER expliene with example? The 555 timer IC is an integrated circuit used in a variety of timer, pulse generation, and oscillator applications. The 555 can be used to provide time delays as an oscillator and as a flipflop element. Q) diffrence bt Master-Slave Flip-Flops? Basically Master Slave flip-flop is composed of two parts the Master and the Slave and it has two stages each stage works in one half of the clock signal. Both the Master and the Slave are gated S-R flip-flops and it is not synchronized with the clock positive or negative transition rather it known as a pulse triggered flip-flop as it operates at the positive and negative clock cycles. Prepared By:Irfan Khan(Chief Admin) Page 21

For example The outputs from Q and Q from the "Slave" flip-flop are fed back to the inputs of the "Master" with the outputs of the "Master" flip-flop being connected to the two inputs of the "Slave" flip-flop. This feedback configuration from the slave's output to the master's input gives the characteristic toggle of the JK flip-flop. Lecture no 39: Q)What is Edge-Triggered Flip-Flop explian? An edge-triggered flip-flop changes states both at the positive edge or rising edge and at the negative edge or falling edge of the clock pulse on the control input. There are three basic types S-R, J-K and D edge-triggered flip-flop.the S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop's output only on the triggering edge of the clock pulse. On the other hand, the direct set (SET) and clear (CLR) inputs are called asynchronous inputs as they are inputs that affect the state of the flip-flop independent of the clock. For the synchronous operations to work properly these asynchronous inputs must both be kept LOW. Q)Explain Gated S-R Latch exaplien? (Set-Reset) Latch is temporary storage device that has two stable states and its output can change from one state to the other by applying appropriate inputs. In NAND based SR latch active low inputs and only one can be active and NOR based active high inputs. Four inputs are applied on both of these and one of input gives Storage State, other are Reset,Set, Indeterminate State on the base of gate functionality. Please visit following site for better understanding of output table. Q) what is latch explian with example? Prepared By:Irfan Khan(Chief Admin) Page 22

Latches are used as temporary buffers whereas flip flops are used as registers. For example A D latch is level triggered and it will follow the input as long as the gate is true. Once the gate goes false, the output will stay at the last known value. A D flip flop is edge triggered and the output will not change until the edge of the gate. At that point, the output will go to the state of input and then it will stay at that value. Q)Explain State reduction using Kmaps? Lecture no 40: In sequential circuit, state diagram shows the sequence of current and next states. The basic requirements are clock transition and external state. The transition from a current state to the next state is determined by current state and the inputs. The advantage of state diagram is to reduce number of flip flop and it is reduced through if equivalent states exist then one of the equivalent states is removed, For this reason circuit reduction in the number of state results in fewer flip-flops and a simpler circuit.. Basically the Next-State table is derived from the State diagram. The binary pattern assigned to the symbolic states is called as thestate assignment. It is assigned value of states, In page no:335 the first State Assignment and next state is determined through state diagram of figure 32.4. In design procedure-maps made with Don t care Conditions.e.g Firstly draw the k-maps according to values given in Table 31.3, for example see the J2 k-maps of table 31.4a,only one group made according to only J 2 inputs of Table 31.3 and Don t care Conditions values are used and it can be considered as 0 or 1. J 2 =Q 1 Q 0 Q2Q1/Q0 J 2 0 1 00 0 0 01 0 1 10 x x 11 x x Q) What is Shieft Register and its use? Prepared By:Irfan Khan(Chief Admin) Page 23

SHIFT REGISTERS: The need to storage binary data was discussed earlier. In digital circuits multi-bit data has to be stored temporarily until it is processed. A flipflop is able to store a single binary bit of information. Multiple bits of data are stored by using multiple flipflops which have their clock inputs connected together. Thus, by activating the clock signal multiplebits of data are stored. Technically, a register performs two basic functions. It stores data and it moves or shifts data. The shifting of data involves shifting of bits from one flipflop to the other within the register or moving data in and out of the register. The shift operation of the binary data carried out by applying clock signals. Several different kinds of shift operations can be identified. The different shift operations are described using a 4-bit shift register. 1. Serial In/Shift Right/Serial Out Operation Data is shifted in the right-hand direction one bit at a time with each transition of the clock signal. Figure 34.1. The data enters the shift register serially from the left hand sid e and Prepared By:Irfan Khan(Chief Admin) Page 24

after four clock transitions the 4-bit register has 4- bits of data. The data is shifted out serially one bit at a time from the right hand side of the register if clock signals are continuously applied. Thus after 8 clock signals the 4bit data is completely shifted out of the shift regi ster. 2. Serial In/Shift Left/Serial Out Operation Data is shifted in the left-hand direction one bit at a time with each transition of the clock signal. Figure 34.2. The data enters the shift register serially from the right hand si de and after four clock transitions the 4-bit register has 4- bits of data. The data is shifted out serially one bit at a time from the left hand side of the register if clock signals are continuously applied. Thus after 8 clock signals the 4-bit data is completely shifted out of the shift register. The Serial Shift register has been discussed earlier, implemented using J-K flip-flops. Serial shift registers can be implemented using any type of flipflops. A serial shift register Prepared By:Irfan Khan(Chief Admin) Page 25

implemented using D flip-flops with the serial data applied at the D input of the first flipflop and serial data out obtained at the Q output of the last flip-flop is completely shift out the 4-bit data. As the data is shifted out 1-bit at a time, a logic 0 value is usually shifted in to fill up the vacant bits in the shift register. Q)Applications of shieft Register? APPLICATIONS OF SHIFT REGISTERS The major application of a shift register is to convert between parallel and serial data. Shift registers are also used as keyboard encoders. Q) What is Address Signals? Lecture no 41: Address Signals Address signals are required to specify the location in the memory from which information is accessed (read or written). A set of parallel address lines known as the address bus carry the address information. The number of bits (lines) comprising the address bus depends upon the size of the memory Q) what is data Signals? Data Signals Data lines are required to retrieve the information from the memory array during a read operation and to provide the data that is to be stored in the memory during a write operation. As the memory reads or writes one data unit at a time therefore the data lines should be equal to the number of data bits stored at each addressable location in the memory Prepared By:Irfan Khan(Chief Admin) Page 26

Q) Types of Memoryies? 1)RAM Static RAM Dynamic Ram 2)ROM 3)Volatile and Non Volatile Lecture no 42: Q) what is SRAM? Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM (DRAM) which must be periodically refreshed. SRAM exhibits data remanence,[1] but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. Characteristics: SRAM is more expensive and less dense than DRAM and is therefore not used for highcapacity, low-cost applications such as the main memory in personal computers. Q) Define Dynamic Ram? A type of physical memory used in most personal computers. The term dynamic indicates that the memory must be constantly refreshed (reenergized) or it will lose its contents. RAM (random-access memory) is sometimes referred to as DRAM (pronounced dee-ram) to distinguish it from static RAM (SRAM). Static RAM is faster and less volatile than dynamic RAM, but it requires more power and is more expensive. Prepared By:Irfan Khan(Chief Admin) Page 27

Lecture no 43: Q) Define LAST IN-FIRST OUT (LIFO) MEMORY? Last In-First Out Memory finds applications in computer systems where it is used to implement a stack. The operation of a stack can be understood by viewing a stack of plates. In a stack of plates the first plate is placed at the bottom the next plate placed is placed on the top, the third plate is placed on the top of the second plate and so on. Plates are removed one at a time from the top of the stack, thus the last plate placed on the stack top is the first to be removed followed by the second plate and then the plate at the bottom which was placed first. In a register based LIFO memory implementation a set of Parallel In/Parallel Out registers are connected together such that data is pushed down or pulled up when data is stored or removed from the memory respectively Q)Define memory Map? Memory Map The Memory Map of any digital system specifies the total memory space that can be accessed by the microprocessor and the distribution of the total addressable space amongst RAM, ROM, stack and buffers. The memory map shown in the figure shows the division of 1 MByte of addressable space into ROM, RAM for storage of data, RAM for storage of program code, vacant space which can be used in the future and a stack. Q)Define Dual AD? Lecture no 44: An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude. The conversion involves quantization of the input, so it necessarily introduces a small amount of error. Instead of doing a single conversion, an ADC often performs the conversions ("samples" the input) periodically. The result is a sequence of digital values that have converted a continuous-time and continuous-amplitude analog signal to a discrete-time and discreteamplitude digital signal. Prepared By:Irfan Khan(Chief Admin) Page 28

Q) Define FAD? Flash Analogue-to Digital Converter The Flash A/D converter is based on a resistor potential divider, where multiple resistors of identical value form a voltage divider. A reference voltage is applied at one end of the potential divider which divides the voltage equally across all the resistors. The input analogue voltage is applied at the non-inverting inputs of a set of Op-Amp based comparators. The inverting input of each comparator is connected to the resistive voltage divider which provides reference voltages for all the comparators. If the input voltage is larger than the reference voltage the output of the comparator is logic high otherwise it is logic low. The outputs of all the comparators are connected to the input of a priority encoder which converts the comparator outputs to a binary coded equivalent value. Lecture no 45: Q)Explain Performance characteristics of Digital-to-Analogue Converters? Performance characteristics of D/A converters are determined by five parameters. 1. Resolution 2. 2. Accuracy 3. 3. Linearity 4. 4. Monotonicity 5. 5. Settling Time Q) The R/2R Ladder Digital to Analogue Converter?Explain A resistor ladder is an electrical circuit made of repeating units of resistors. Two configurations are discussed below, a string resistor ladder and a R-2R ladder. Prepared By:Irfan Khan(Chief Admin) Page 29

An R-2R Ladder is a simple and inexpensive way to perform digital-to-analog conversion, using repetitive arrangements of precisionresistor networks in a ladder-like configuration. A string resistor ladder implements the non-repetitive reference network. Prepared By:Irfan Khan(Chief Admin) Page 30