Radiation Effects and Mitigation Techniques for FPGAs Fernanda Lima Kastensmidt Universidade Federal do Rio Grande do Sul (UFRGS) Contact: fglima@inf.ufrgs.br
Field Programmable Gate Arrays A type of gate array that is programmed in the field rather than in a semiconductor fab. It contains programmable logic components called "logic blocks", and a hierarchy of configurable interconnects that allow the blocks to be "wired together. Logic blocks: can be configured to perform complex combinational functions (combinational logic) include memory elements (sequential logic) It may contain embedded memories and microprocessors SERESSA 2 Fernanda Kastensmidt
FPGA Design Flow Design Synthesis optimizations Logic mapping Placement Routing configuration bitstream User s design mapped into the FPGA SERESSA 2 Fernanda Kastensmidt
FPGA Summary Programmable Element ANTIFUSE FLASH SRAM Characteristics electrically programmable switch forms a low resistance path between two metal layers. electrically programmable transistors hold the configuration that controls a pass transistors or multiplexers connected to predefined metal layers the state of a static latch controls pass transistors or multiplexers connected to predefined metal layers Configuration is NO volatile Configuration is NO volatile Configuration is volatile One-time configurable Re-configurable Re-configurable Example of Fabricants
SERESSA 2 Fernanda Kastensmidt
Effects of ionizing radiation Single Event Effects (SEE) Soft Errors Single Event Transient (SET) Single Event Upset (SEU) Hard Errors Functional Interrupt (SEFI) Single Event Latchup (SEL) Gate Rupture (SEGR) Single Event Burnout (SEB) Total Ionizing Dose (TID) Displacement Damage (DD) 6 SERESSA 2 Fernanda Kastensmidt
Radiation effects in FPGA Single Event Effects (SEE) Soft Errors Single Event Transient (SET) Single Event Upset (SEU) Hard Errors Functional Interrupt (SEFI) Single Event Latchup (SEL) Gate Rupture (SEGR) Single Event Burnout (SEB) Total Ionizing Dose (TID) Displacement Damage (DD) 7 SERESSA 2 Fernanda Kastensmidt
OFF OFF OFF OFF SEU in Memory Elements SRAM cell WL WL BIT-FLIP gnd P N N P ionization 8 SERESSA 2 Fernanda Kastensmidt
OFF SET in Logic Gates Inverter cell gnd P N N P ionization 9 SERESSA 2 Fernanda Kastensmidt
SET in Combinational Circuits Not all SETs are captured by a memory cell. They can be: Logical masked Electrical masked Latch window masked Logical masked e e e2 a3 Q SERESSA 2 Fernanda Kastensmidt
SET in Combinational Circuits Not all SETs are captured by a memory cell. They can be: Logical masked Electrical masked Latch window masked Electrical masked e e e2 a3 Negligible pulse Q SERESSA 2 Fernanda Kastensmidt
SET in Combinational Circuits Not all SETs are captured by a memory cell. They can be: Logical masked Electrical masked Latch window masked Latch window masked e e e2 a3 clk edge Q 2 SERESSA 2 Fernanda Kastensmidt
TID Effects in CMOS circuits Effects: shifts in the NMOS transistor Voltage Threshold (Vth) increase of leakage current in transistors Flash transistors: lost of gate charge Because oxide dimensions reduce with the advance of technology, TID effects have been reduced. SERESSA 2 Fernanda Kastensmidt
Using FPGA under Radiation Analyze SEU and SET effects in FPGA architecture and your configured design Use hardening techniques if needed Qualify FPGA and your design under radiation User implementation: Hardening techniques at hardware description language (your configured design): VHDL or Verilog design Vendor implementation: Hardening techniques at the FPGA matrix logic gates and flip-flops FPGA SERESSA 2 Fernanda Kastensmidt
Synthesis Tool Synthesis attributes must be set on your design tool. For example by using Synplify, Mentor or Synopsys. According to the tool and vendor there are: tmr attributes can be turned on or off and it can be local or global. Examples: Module br_core (...) /* synthesis syn_radhardlevel="tmr" */; reg hdw_loss_arb /* synthesis syn_radhardlevel="tmr" */; SERESSA 2 Fernanda Kastensmidt
Common used SEE Mitigation Techniques Localized TMR: Only flip-flops are TMR with voters By the user (HDL level description) By the vendor (in the silicon FPGA matrix) Global TMR (also known XTMR) All logic and flip-flops are TMR and voted Clk tree can be also triplicated IOBs can also be triplicated By the user (HDL level description) Reconfiguration SET filtering Usually by the user (HDL level description) Be very aware about synchronization EDAC and other redundancy methods Can be used in by user (HDL description) depending on the FPGA and cases.
One time Configurable FPGAs 7
Antifuse FPGA from Actel (Microsemi) RTAX S/SL.5 µm CMOS antifuse process technology, 7 metal layer.5v core Embedded memory 35 MHz Antifuse FPGAs SERESSA 2 Fernanda Kastensmidt
RAM CT RAM RAM RAM RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD HD HD HD HD HD HD HD HD HD HD HD HD HD [Actel, RTAX-S RadTolerant FPGAs 27] C R RX TX RX TX RX TX RX TX B C C C R Super Cluster RTAX-S device Antifuse FPGAs
D2 D DB A A Y D2 D DB A A FCO Y D D3 B B CFN FCI D D3 B B CFN RTAX-S device C C R C-CELL Susceptible to SET C-CELL R-CELL Robust to SEU X X X ERROR [Actel, RTAX-S RadTolerant FPGAs 27] Antifuse FPGAs SERESSA 2 Fernanda Kastensmidt
RTAX-S device Control Logic Logic redundancy design Clock Network Eliminate small leaves in the clock tree User flip-flop Hard-wired triple redundant latch for master and slave Embedded SRAM EDAC macro in FPGA design software (ACTgen) Hamming code detect two error bits, correct one error bit Bit separation: mitigate charge sharing [Wang et al, NSREC, 3] Antifuse FPGAs SERESSA 2 Fernanda Kastensmidt
D2 D DB A A Y D2 D DB A A Y D D3 B B FCI CFN D D3 B B FCI CFN RTAX-S: SEU Hardened Techniques [Wang et al, NSREC, 3] C C R Hardened flip-flop (TMR) C-CELL C-CELL comb logic comb logic VHDL / Verilog directly to the FPGA with no modifications as all flip-flops are already hardened by the vendor. Antifuse FPGAs SERESSA 2 Fernanda Kastensmidt
D2 D DB A A Y D2 D DB A A Y D D3 B B FCI CFN D D3 B B FCI CFN RTAX-S: SET mitigation by User [Wang et al, NSREC, 3] C C R Hardened flip-flop (TMR) C-CELL C-CELL comb logic SET Filter VHDL / Verilog must be modified to add SET filtering. Antifuse FPGAs
Antifuse FPGA from Aeroflex UT6325 RadTol Eclipse FPGA.25μm, five-layer metal, ViaLinkTM epitaxial CMOS 2 MHz 2.5V core supply voltage Embedded memory Antifuse FPGAs SERESSA 2 Fernanda Kastensmidt
RadHard Eclipse FPGA ERROR X hardened flip-flops Robust to SEU ViaLink connections Antifuse FPGAs
SEU hardened Technique Hardened flip-flop by vendor: based on DICE DICE Memory Cell [Calin, 96] Vdd Vdd Vdd Vdd MP MP MP2 MP3 A B C D MN MN MN2 MN3 Vss Vss Vss Vss clk MN4 MN5 MN6 MN7 D /D Embedded memory: EDAC code by user Combination logic: SET filtering by user Antifuse FPGAs
One-time configurable FPGA Summary Configuration cells are not sensitive to SEE. Flip-flops are not sensitive to SEU Actel and Aeroflex provides one solution where all flip-flops are hardened. No modifications at HDL is needed for SEU mitigation Logic are susceptible to SETs in high frequency (>Mhz) The user may protect the logic by using high level mitigation techniques in the HDL description of the design. Redundancy or EDAC is more appropriate than SET filtering, or SET filtering with TMR in flip-flops. Embedded memory EDAC codes implemented by user Antifuse FPGAs SERESSA 2 Fernanda Kastensmidt
Reconfigurable FPGAs 28
Reconfiguration in space: why? To gain flexibility Resource optimization due to time sharing Extend the lifetime by adding new functions Bug fixing Updates Reconfiguration has been there for years: Download of new software Enabling/disabling of spare modules Reconfigurable FPGAs can bring new possibilities! SERESSA 2 Fernanda Kastensmidt
FPGA structure/technology SERESSA 2 Fernanda Kastensmidt
What about space? Reconfigurable FPGAs: Configuration memory must be changeable on-the-fly Multiple configuration images must be stored Space environment can alter configuration information Challenges: Understand the problem Identify suitable error mitigation techniques SERESSA 2 Fernanda Kastensmidt
Xilinx Virtex-4QV SRAM-based FPGA Architecture BRAM Lookup Table CLB (LUT) A B C D PowerPC PowerPC Boolean Function F(A,B,C,D) DSP SRAM-based FPGAs 32
SEU in SRAM-based FPGAs: CLB slice LUT I I 2 I 3 I 4 CLB slice Transient Effect (corrected at next ffp load) routing Persistent effect (corrected by scrubbing) LUT Configuration memory bits SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt 33
SET in SRAM-based FPGAs : CLB slice LUT I I 2 I 3 I 4 X CLB slice SET may be captured by the ffp. routing Transient Effect (corrected at next ffp load) SRAM-based FPGAs LUT Configuration memory bits 34
SRAM-based FPGA General Routing Matrix (GRM) Xilinx Virtex-4QV Direct lines Long lines CLB CLB CLB CLB CLB CLB CLB Hex connections CLB Hex lines CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB Direct connections Fast connect Double lines CLB CLB CLB SRAM-based FPGAs 35
Xilinx Virtex-4QV SEU in SRAM-based FPGAs: Routing configuration cells Direct connections: Hex connections: open short open short short open Persistent effect (corrected by scrubbing) SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt 36
Other sensitive structures Power-on Reset (POR) Low probability of occurrence Signature: done pin transitions low, I/O becomes tristated, no user functionality available Solution: reconfigure device SelectMAP and JTAG controllers Low probability of occurrence Signature: loss of communication, read access to configuration memory returns constant value. Solution: reconfigure device Input and Output Blocks (IOB) Power-PC Hard IP Single-Event-Functional Interrupts (SEFI) Digital Clock Manager (DCM) Multi-Gigabit Transceivers (MGT) SRAM-based FPGAs 37
Flash-based FPGA ProAsic3 /RT3P Flash-based FPGAs
SEE sensitivity Configurable Logic Block called VersaTile VersaTile logic Effect : SET in the logic Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEE sensitivity Configurable Logic Block called VersaTile VersaTile X Effect 2: SEU in the ffp ffp Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEE sensitivity Floating Gate (FG) switch Effect 3: SET in the logic path SET in the routing path Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEE Mitigation Techniques Design-level solutions: Use non rad-hard FPGAs (military / COTS): Design-level and architectural-level mitigation Place and route mitigation Device-level solutions: Use rad-hard FPGAs by construction (Virtex-5QV, ATF28), based on 2T memory elements, plus glitch filtering and ECC Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEE Mitigation Techniques Different types of mitigations according to the FPGA sensitivity Implemented by user: SEE mitigation techniques at design and architecture level: VHDL or Verilog; and at EDA level: place&route design Soft FPGAs (COTS/Military) SRAM-based FPGAs: Virtex families [Xilinx] - Virtex-4QV (Space-grade) FLASH-based FPGAs: ProASIC families [Actel] FPGA Flash-based FPGAs SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Design Flow Mitigation for SRAM-based FPGAs HDL design TMR by hand ISE tool Placement Routing configuration bitstream ISE tool Synthesis optimizations Logic mapping Placement Routing Scrubbing (full or partial reconfiguration).. output Fault Injection (fault tolerance verification) SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEE mitigation for SRAM-based FPGAs Scrubbing: full or partial reconfiguration BOOT RUB XQR8V4 DATA[7:] OE/RESET CE GND CLK EEPROM Original bitstream XQR8V4 DATA[7:] OE/RESET CE GND CLK FPGA DATA[7:] INIT Configuration bits DONE CS WR I/O I/O RUB Controller I/O I/O O CCLK SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Scrubbing Method Scrubbing can be performed: from outside the FPGA by another FPGA controller from inside the FPGA: Hardware Internal Configuration Access Port (HWICAP) SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEE mitigation for SRAM-based FPGAs Global TMR (also known XTMR) All logic and flip-flops are TMR and voted clk tree triplicated IOBs triplicated Implemented by the user (HDL level description) or by tool FPGA INPUT REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR flip-flop REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR flip-flop REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR Output Voter OUTPUT package PIN package PIN granularity SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
FPGA INPUT REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR flip-flop REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR flip-flop REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR Output Voter OUTPUT package PIN package PIN tr tr tr2 TMR flip-flop X clk MAJ OK clk MAJ OK clk2 MAJ OK OK OK The recovery path is mandatory to correct the state of the flipflops, specially in FSM. R R R2 MAJ LUT: _ SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt 48
FPGA INPUT REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR flip-flop REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR flip-flop REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) TMR Output Voter OUTPUT package PIN package PIN REF R R R2 MAJ : it allows the data to pass to the output pad. LUT: _ : it blocks the data R R R2 X OK OK O_voter O_voter O_voter 3-state_ R 3-state_ R 3-state_2 R2 X OK OK SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt 49
Embedded Memory (BRAM): EDAC Virtex5: XQR5VFX3 s from Xilinx BRAM blocks are configurable as 52 64-bit RAM with 8-bit error correcting code (ECC) bits for every 64-bit word. The 8-bit ECC parity checksum detect and correct single-bit errors, and detect (but not correct) double-bit errors. For every word read, the 72-bits are fed into an ECC decoder which generates status bits indicating: no error, single-bit error detected and corrected, or double-bit error detected. [Allen et al., TNS 2] SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Embedded memory (BRAM): TMR Upsets in BRAMs are not corrected by scrubbing. OK X OK TMR with refreshing can be used to mitigate upsets. Need to use Dual Port BRAMs. Mechanism to refresh the memory contents Counter Voters SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEE in Embedded Processor PowerPC Software-based techniques Duplication of variables with comparisons (data fault effects) Basic block signatures (control flow fault effects) Watch-dog and self-checking blocks (improve control flow fault effects) Two Power-PCs for detection and recomputation [Bernardi, et al,, TNS, 26] [Azambuja, et al, TNS, 2] SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Problem: Domain Crossing Events Bit-flips in the routing can generate short cut connections among different blocks of the TMR (tr, tr and tr2). INPUT package PIN FPGA upset REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) X OK OK TMR register with voters and refresh OK OK OK tr tr tr2 TMR Output Majority Voter package PIN OUTPUT Upset affects only the redundant logic tr, consequently, the majority voter choose the correct result (two out of three outputs). SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Problem: Domain Crossing Events Bit-flips in the routing can generate short cut connections among different blocks of the TMR (tr, tr and tr2). INPUT package PIN FPGA upset REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr) REDUNDANT LOGIC (tr2) X OK X TMR register with voters and refresh X X X tr tr tr2 TMR Output Majority Voter package PIN OUTPUT Upset affects two redundant logic modules, consequently, the majority voter may choose the wrong result (two out of three outputs). SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Problem: Domain Crossing Events Bit-flips in the routing can generate short cut connections among different blocks of the TMR (tr, tr and tr2). Signal: tr_comp/n$32 Redundant upset Signal: counter6/counter/i$26/tr2_count() Redundant 2 SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Problem: Domain Crossing Events According to the location of the upsets, more than one CLB or routing connections can be affected generating error in more than one TMR redundant part. ~5% of the upsets in the routing may result on this type of fault Multiple bit upsets due to: High density and small dimensions of the configuration memory cells. Charge sharing SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Solution for Domain Crossing Events Use dedicated placement and routing to minimize domain cross-section and vulnerable bit upsets. RoRa: Reliability-Oriented Place and Route Algorithm RORA [Sterpone, L. Electronics System Design Techniques for Safety Critical Applications Publisher Springer, 28] SRAM-based FPGAs
SEE Mitigation in Flash-based FPGAs Considering only SEU effect: Local TMR EDAC (hamming code) ProAsic3 /RT3P Considering SET and SEU effects: Global TMR SET filtering System redundancy and checkers Etc User can protect the design at HDL level as in a ASIC! Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEU mitigation for FLASH-based FPGAs Local TMR: Only flip-flops are TMR with voters Implemented: By the user (HDL level description) By the vendor (in the silicon FPGA matrix) ProAsic3 /RT3P FPGA INPUT LOGIC TMR flip-flop LOGIC TMR flip-flop LOGIC TMR Output Voter OUTPUT Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
FPGA INPUT package PIN REDUNDANT LOGIC (tr) TMR flip-flop REDUNDANT LOGIC (tr) TMR flip-flop REDUNDANT LOGIC (tr) TMR Output Voter OUTPUT package PIN TMR flip-flop clk clk clk X OK OK MAJ OK R R R2 MAJ Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt 6
SEU&SET mitigation for FLASH-based FPGAs TMR & SET filtering Implemented usually by the user (HDL level description) Be very aware about performance degradation Added delay is proportional to the SET pulse width intended to be filtered. FPGA INPUT LOGIC Delay x Delay x2 TMR flip-flop LOGIC Delay x Delay x2 TMR Output Voter OUTPUT Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
FPGA INPUT LOGIC Delay x Delay x2 TMR flip-flop LOGIC Delay x Delay x2 TMR Output Voter OUTPUT clk logic clk X MAJ OK logic logic2 Delay x clk OK ffp ffp Delay x2 clk OK ffp2 MAJ Frequency penalty is proportional to Delay Flash-based FPGAs 62
SEU & SET mitigation in Flash-based FPGA VersaTile logic VersaTile logic VersaTile ffp VersaTile MAJ VersaTile VersaTile delay ffp VersaTile VersaTile VersaTile delay delay ffp VHDL / Verilog must be modified to add SET filtering and TMR Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
SEE Mitigation Techniques Different types of mitigations according to the FPGA sensitivity RadHard SRAM-based FPGAs Virtex-5QV (Space-grade) - SIRF [XILINX] ATF28E [ATMEL] design Implemented by vendor: Device level and Hardening by Design (RHBD) techniques at the FPGA matrix logic gates and flip-flops FPGA Flash-based FPGAs SERESSA 2 Fernanda Kastensmidt
ATF28 Reprogrammable RadTol FPGAs From Atmel SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Mitigation Techniques in ATF28 Layout rules to mitigate charge sharing SEU hardened Memory cells (2T) Core cell Flip-Flops, embedded memory, configuration memory based on radiation hardened Flip-Flops Controller protected by classical TMR RAM address decoders, clock and reset trees Protected by DMR (resistive isolation path based on N and P isolated path carrying the same signal) Isolation path to filter SET [BANCELIN, MAPLD 29] SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Device-level SEE Mitigation in ATF28E FPGA SEU Hardened Flip-flop Isolation path for SET [BANCELIN, MAPLD 29] SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Xilinx SIRF FPGA Virtex-5QV (Space-grade) 65nm CMOS process SEU hardened flip-flops: All configuration SRAM cells All user flip-flops (CLB) SET filtering structure that can be configured on or off when configuring the FPGA. BRAMs have EDAC with refreshing to avoid accumulation of errors. SRAM-based FPGAs SERESSA 2 Fernanda Kastensmidt
Resource Comparison SEU Equiv. Gates (4-LUT) FFps ANTIFUSE.5 K 4 K 3 K 2 K FLASH 75 K or 75 K SRAM 8 K 4 K 8 K 4 K Dist. Mem (bits) - - -, K - Emb. Mem (bits) DSP modules 55 K 54 K 54 K 6, K - 2-96.25μm.5μm.3μm.9μm 5 K -.8μm [From Vendor Datasheets] SERESSA 2 Fernanda Kastensmidt
SEE Mitigation techniques ANTIFUSE FLASH SRAM SET SEU SET filtering or global TMR None SET filtering with localized TMR / EDAC / global TMR / others Global TMR None* None Config. bits None None None Scrubbing None SERESSA 2 Fernanda Kastensmidt
SEE Summary SEU ANTIFUSE FLASH SRAM Satured cross- Section (cm 2 /ffp) Embedded memory 2E-7 4E-9 4E-8 3E-8 Flip-flop 5E-7 E-9 2E-7 7E-7 LETth MeV-cm 2 /mg Embedded memory 64 3.2 Flip-flop 42 37 6.5.25μm.5μm.3μm.9μm *With mitigation: SEE immunity < 43 MeV-cm2/mg
SEE Summary SEU ANTIFUSE FLASH SRAM Error Rate per bit Embedded memory 4.8E- 4.4E-2 4E-8 7E-7 Flip-flop 2.8E- 7.E-3 5E-9 2E-6.25μm.5μm.3μm.9μm The final Error Rate depends on your final design!
TID and SEL effects in FPGAs ANTIFUSE FLASH SRAM TID 3 krad (si) 3 krad (si) < 4 krad (si) 3 krad (si) SEL free < 2 Mev-cm2/mg < 7 Mev-cm2/mg < 96 Mev-cm2/mg < 25 Mev-cm2/mg < 7 Mev-cm2/mg SERESSA 2 Fernanda Kastensmidt
TID Effects in ProASIC3 / RT3P Logic is fabricated in 3nm and it presents electrical degradations that follows ASIC degradation. Floating gate (FG) transistor show degradation in: Vth shifts Leakage current Lost of charge Degradation in Charge-pump and control circuits. 27/9/2 ESTEC
TID Test: Co-6 source ProAsic3 FPGA Rate:.749 krad(si)/h.48 rad(si)/s At IEAv in São Jose dos Campos, Brazil
Temperature (Celsius) Power supply DC current (A) Current & Temperature x krads(si).6.55.5.45.4.35.3.25.2 5 5 2 25 3 35 4 45 5 55 6 65 7 75 8 Accumulated dose (krad(si)) 29. 28.8 28.6 28.4 28.2 28. 27.8 27.6 27.4 27.2 27. 26.8 5 5 2 25 3 35 4 45 5 55 6 65 7 75 8 Accumulated dose (krad(si))
TID effect Propagation Delay Degradation in ProASIC3 (3nm technology) [Kastensmidt et al, TNS, 2] SERESSA 2 Fernanda Kastensmidt
% Propagation-delay Degradation Avg (casea & caseb) - measured Avg2 (casec) - measured Avg3 (cased) - measured Avg (all) - measured 3 6 3 7 2 24 27 3 34 38 4 45 48 52 55 59 62 69 Acummulated dose (krad(si)) 27/9/2 ESTEC
Conclusions Reconfigurable computing could be a breakthrough for certain space applications However, space is a very conservative business and may deem reconfigurable computing as too risky Sensitivity of devices to radiations Complexity of the design and validation process Enabling technology still not mature enough: Virtex 5 QV is ITAR and unknown AT28 is too small and low performing RT3P is not yet as capable as high-end SRAM FPGAs SERESSA 2 Fernanda Kastensmidt
Thank You! Fernanda Lima Kastensmidt Universidade Federal do Rio Grande do Sul (UFRGS) Contact: fglima@inf.ufrgs.br