CD FOR VLSI DESIGN - I Lecture 32 V. Kamakoti and Shankar Balachandran
Flip-flops with synchronous Preset and Clear Inferring a flip-flop with synchronous Preset and Clear comes out of a combination of clocked and non-clocked events inside an always block s sensitivity list. There is one clocked event, say, posedge clk or negedge clk
Cont d The remaining events are posedge or negedge, where can be any boolean expression. The always loop looks like always @(posedge or negedge B or posedge C or negedge D or posedge clk) if () <expression1> else if (!B) <expression2> else if (C ) <expression3> else if (!D) <expression4> else <expression5> Note that the conditions posedge in sensitivity list appears in the corresponding if as and similarly negedge in sensitivity list appears as! in the corresponding if.
Cont d <expression1>,,<expression4> forms the asynchronous part of the nested if while <expression5> forms the synchronous part (the default case). ny variable that is assigned both in the synchronous and asynchronous part becomes a flip-flop with asynchronous preset/clear. The logic that drives it in the asynchronous part drives the asynchronous preset/clear port of the corresponding flip-flop, while the logic that drives it in the synchronous part is assigned to the D- input
Cont d The variable that forms the Clocked event, (the default case) drives the clock input of the flip-flop.
n Example module synpreclrcounter(clock,preset,updown,clear,presetdata,counter); parameter NUM_BITS = 2; input Clock, Preset, UpDown, Clear; input [NUM_BITS 1:0] PresetData; output [NUM_BITS 1:0] Counter; reg [NUM_BITS-1:0] Counter; always @(posedge Preset or posedge Clear or posedge Clock) if (Preset) Counter <= PresetData; else if (Clear) Counter <= 0; else begin if (UpDown) Counter <= Counter + 1; else Counter <= Counter 1; end endmodule
B B 1 2 B1 B2 1 2 B1 B2 1 2 B1 B2 O122 O122 ND2 ND2 Preset Datel Preset INRBH INRBH PLLS3CX PLLS3CX 0 ON Preset Dateil PD CD PD CD Counter1 Clock Clock Up Down D1 D0 S0 D1 D0 S0 ON B
Caution When Preset is 1 and Presetdata changes, this will NOT be reflected in Verilog HDL but will be propogated to the flip-flops in the synthesized netlist. Be careful while using synchronous Inputs to flip-flops for functional mismatch.
nother Example module synflipflop(clk,reset,set,currentstate,nextstate); input Clk, Reset, Set; input [3:0] CurrentState; output [3:0] NextState; reg [3:0] NextState; always @(negedge Reset or negedge Set or negedge Clk) if (!Reset) NextState <=12; else if (!Set) NextState <= 5; else NextState <= CurrentState; endmodule
Current State0 0 PD NextState0 Set Reset B NR2 CD FD1S2CX INRBH 0 PDN NextState3 Current State3 FD1S2CX CDN FD1S2CX Current State1 INRBH 0 NextState1 B CD FD1S2CX Current State2 ND2 0 PD NextState2 FD1S2CX
Some Interesting facts Second flip-flop has only preset and third has only clear, while the others have both.
Flip-flops with Synchronous Preset/Clear Define the preset and clear logic inside a Clocked lways Statement. module SyncPresetCounter(Clock,Preset,UpDown,PresetData,Counter); input Clock, Preset, UpDown; input [0:NBITS-1] PresetData; output [0:NBITS-1] Counter; reg [0:NBITS-1] Counter; always @(negedge Clock) if (Preset) Counter <= PresetData; else if (UpDown) Counter <= Counter + 1; else Counter <= Counter 1; endmodule
Two pproaches Direct the PresetData input to synchronous preset input of the synthesized flip-flops Direct the PresetData input to the data input of the flip-flops. The following circuit is got using the latter option.
Preset Date1 Preset Clock D1 D0 S0 1 2 0 D1 0 D0 B B1 0122 B2 XDR2 S0 ON ON FL1S2X FL1S2X Counter0 Counter1 INRBH Preset Date0
nother Example module SyncFlipFlop (ClkB, Reset, Set, CurrentState, NextState); input ClkB, Reset, Set; input [3:0] CurrentState; output [3:0] NextState; reg [3:0] NextState; always @(negedge ClkB) if (!Reset) NextState <= 12; else if (!Set) NextState <= 5; else NextState <= CurrentState; endmodule
The Values The value 12, 5 and CurrentState are to be multiplexed and directed to the D inputs.
The Circuit Current State3 0 0 NextState3 B ND2 B ND2 0 0 ON FD1S2X NextState1 Reset Set B C ND3 ON NextState0 0 0 1 2 INRBH O121 INRBH ON INRBH B C NR3 0 0 NextState2 ON FD1S2X
Reference Chapter 2, Verilog HDL Synthesis, by J. Bhasker.
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