igitl Logic/esig. L. 10 My 2, 2006 10 Registers d couters 10.1 Registers The simplest -bit register is collectio of flip-flops triggered by commo clock. I wou prefer to cll it just -bit flip-flop, sice it performs oly lod opertio o ech risig edge of the clock. d 1 d 1 d0... q 1 q 1 d q The simplest -bit register shou perform t lest two opertios lod d ho This c be implemeted i two wys: blockig/gtig the clock (typiclly bd ide for umber of resos) ddig iput multiplexer. gted clock: gc ho lod gc d q ho lod A.P. Ppliński 10 1 igitl Logic/esig. L. 10 My 2, 2006 10.1.1 A -bit prllel lod register Lod I 0 I 1 I 2 A 0 A 1 A 2 = 1 0 d p q q A 3 I 3 lock 2002 Pretice Hll, Ic. M. Morris Mo IGITAL ESIGN, 3e. Fig. 6-2 4-Bit Register with Prllel Lod The opertio tble of the -bit register with prllel lod: The timig digrm: lod ho lod 0000000 00000000 11111111 00000000000000 11111111111111 01 11111111 00000000000000 11111111111111 01 lod opertio 0 q <= q ho 1 q <= lod A.P. Ppliński 10 2
igitl Logic/esig. L. 10 My 2, 2006 The VHL rchitecture cosists of three cocurret sttemets describig the iput multiplexer, the flip-flop process d ssigmet of iterl outputs from the flip-flops to the output port: LIBRARY ieee; USE ieee.std_logic_1164.ll; USE ieee.std_logic_rith.ll; ENTITY plreg IS GENERI ( N : iteger :=4 ) ; PORT (, : IN std_logic ; A : IN std_logic_vector(n-1 dowto 0) ; : OUT std_logic_vector(n-1 dowto 0) ) ; EN ENTITY plreg; ARHITETURE rtl OF plreg IS SIGNAL P, : std_logic_vector(a RANGE) ; -- the iput multiplexer: <= A WHEN = 1 ELSE P ; -- iterl sigl o output port <= P ; -- the flip-flop process PROESS () IF EVENT AN = 1 THEN P <= ; EN IF ; EN PROESS ; EN rtl ; A.P. Ppliński 10 3 igitl Logic/esig. L. 10 My 2, 2006 10.1.2 A simple shift register I geerl, shift register llows the biry words stored i the register to be shifted left or right by oe positio, with dditiol bit beig shifted i. The simplest shift register performs oly oe opertio, sy shift-right, t ech risig edge of the clock, tht c be described s (4-bit register hs bee ssumed): s q 3 q 2 q 1 s3 s shr q <= shr(s, q), or (q 3, q 2, q 1, ) <= (s, q 3, g 2, q 1 ), or q[3 : 0] <= (s, q[3 : 1]) Fig. 6-3 4-Bit Shift Register The timig digrm illustrte how 4-bit biry 1000000 111111 0000000 111111 1000000 111111 0 word (0, 1, 0, 1) preseted bit-by-bit t the seril s 00 11 000000 111111 000000 111111 000000 111111 iput s hs bee shifted ito the register durig q3 0 0000000000 1111111111 the four cosecutive risig edges of the clock. q 2 1 00000000000000000 11111111111111111 2002 Pretice Hll, Ic. Such opertio c be referred to s seril M. Morris Mo q 1 0 IGITAL ESIGN, 3e. 0000000000000000000000000 1111111111111111111111111 lod. 1 Seril iput LK SI 0000000000000000000000000 1111111111111111111111111 SO Seril output 000 111 000 111 A.P. Ppliński 10 4
igitl Logic/esig. L. 10 My 2, 2006 10.1.3 A bi-directiol shift register A bidirectiol shift register c be cosidered s the most typicl sequetil compoet. The register performs both shift-right d shift-left opertios d i dditio lod d ho opertios. Opertio to be performed is selected by 2-bit opcode word. Note tht we hve three types of sigls: dt (e.g. A, ), cotrol sigls, (op), d sychroizig (clockig) sigl (clock). sn op[1:0] shreg [3:0] s0 Specifictio of the register is give i the form of the followig fuctio tble (4-bit structure is ssumed): As usul, opertios re performed o the risig edge of the clock. Note tht there re two sigle-bit seril iputs, sn d s0 from which the bits re shifted i o the vcted positio durig the respective shift opertio. Shift register, op opertio 0 ho 1 (sn, [3:1]) shiftr 2 ([2:0], s0) shiftl 3 A lod A.P. Ppliński 10 5 igitl Logic/esig. L. 10 My 2, 2006 s0 sn The iterl structure of the register cosists of two mi prts: set of N = 4 edge-triggered flip-flops with outputs P ideticl to the port sigls, d iputs, i. The flip-flops esure the positive-edge sesitivity, op[1:0] 3 2 1 Multiplexer 0 4-bit 4-to-1 iput multiplexer which effectively implemets opertios s specified i the fuctio tble, selectig pproprite sigls to be loded ito the flip-flops. Timig digrm: i[3:0] Flip Flops P[3:0] op lod shr shr ho shl 3 1 1 0 2 shl 2 [3:0] sn A 5 6 s0 U 5 A (1010) (1101) B (1011) 7 A.P. Ppliński 10 6
igitl Logic/esig. L. 10 My 2, 2006 VHL code follows from the specifictio give i the blockdigrm d the opertio tble. Two versio of the code differs i the wy the multiplexer is specified. ARHITETURE rtla OF shreg IS SIGNAL P, i : std_logic_vector(a RANGE) ; ONSTANT op : std_logic_vector(op RANGE) := "00" ; ONSTANT shr : std_logic_vector(op RANGE) := "01" ; ONSTANT shl : std_logic_vector(op RANGE) := "10" ; ONSTANT d : std_logic_vector(op RANGE) := "11" ; --- op rge must be sttic eg. (1 dowto 0) WITH op SELET i <= P WHEN op, sn & P(P LEFT dowto 1) WHEN shr, P(P LEFT-1 dowto 0) & s0 WHEN shl, A WHEN OTHERS ; LIBRARY ieee; USE ieee.std_logic_1164.ll ; USE ieee.std_logic_rith.ll; ENTITY shreg IS GENERI ( N : iteger := 4 ; M : iteger := 2 ) ; PORT (, sn, s0 : IN std_logic ; op : IN std_logic_vector(m-1 dowto 0) ; A : IN std_logic_vector(n-1 dowto 0) ; : OUT std_logic_vector(n-1 dowto 0) ) ; EN shreg ; ARHITETURE rtlb OF shreg IS SIGNAL P, i : std_logic_vector(a RANGE) ; TYPE rrvec IS ARRAY (turl rge <>) OF std_logic_vector(a RANGE) ; SIGNAL YMUX : rrvec(0 to 2**M-1) ; YMUX <= ( P, sn & P(P LEFT dowto 1), P(P LEFT-1 dowto 0) & s0, A ); i <= YMUX(cov_iteger(usiged(op))) ; -- flip-flop process PROESS () IF EVENT AN = 1 THEN P <= i ; EN IF ; EN PROESS ; <= P ; EN rtla ; EN rtlb ; A.P. Ppliński 10 7 igitl Logic/esig. L. 10 My 2, 2006 Both codes re similr d cosists of three cocurret sttemets: oe for multiplexer, oe for flip-flops P d the oe which ssigs iterl sigl P to output port sigl. I the rtla rchitecture we hve specified memoic mes of costts, which icreses code redbility. The selected sigl ssigmet expressio is bit more limited becuse the select sigl size must be sttic. I the rtlb rchitecture, the multiplexer is specified s rry (tble) of 2 m -bit words. The words i the rry re equivlet to the multiplexer iputs. The opcode op selects the -bit word from the rry A.P. Ppliński 10 8
igitl Logic/esig. L. 10 My 2, 2006 Figure 6-4: Seril Trsfer from Register A to Register B from Mo osider bi-directiol seril trsfer of dt iscuss tri-stte lie driver. A.P. Ppliński 10 9 igitl Logic/esig. L. 10 My 2, 2006 10.2 outers outers re sequetil circuits tht icremet or decremet biry umber stored i the flip-flops i respose to the risig edge of the clock. The me couter is used rther th icremeter/decremeter becuse i the first pplictio of the couters ws coutig the umber of pulses comig to its clock iput. 10.2.1 A ripple couter The simplest couter, kow s ripple couter, is bui from simplified T flip-flops hvig oly the clock iput, tht is, the toggle iput is lwys o, T = 1. q 3 Tff R q 2 Tff R q1 Tff R Tff R rst Note tht the flip-flops toggle o the fllig edge of the clock. I dditio the reset sigl rst sets the iitil stge of the flip-flops to q = (0000) Timig digrm demostrte the dely problem ssocited with the ripple couter. The chge of the sttes does ot occur strictly o the clock edge, but there is growig dely betwee stges. q 1 q 2 0 1 2 3 4 5 6 7 0 A.P. Ppliński 10 10
igitl Logic/esig. L. 10 My 2, 2006 10.2.2 Sychroous couter The bsic sychroous couter is improvemet o the ripple couter d is typiclly bui from the stdrd T flip-flops R T R T R T R T c The q i flip-flop is toggled oly whe the previous flip-flop q i 1 = 1 All flip-flops toggle sychroously o the risig edge of the clock. rst rst q 3 q 2 couter q[3:0] c q 1 Timig digrm: 0 1 2 3 4 5 6 7 0 q 1 q 2 There re three feture tht c be dded to the bove couter: We might wt to strt coutig from set umber rther th from zero A sigl tht idictes tht the fil stge q = 2 1 hs bee reched. We might wt to cout both up d dow. A.P. Ppliński 10 11 igitl Logic/esig. L. 10 My 2, 2006 10.2.3 Uiversl up-dow couter The uiversl up-dow couter performs four opertios ho, lod, cout up (icremet) d cout dow (decremet) Opertios re selected by 2-bit opcode word op[1:0]. I dditio sigl cr idicted the mximum (ll oes) or miimum (ll zeroes) couter cotets depedig o the directio of coutig. The bove descriptio is formlized by the followig opertio tble: As usul, opertios r performed o the risig edge of the clock. For the ho d lod opertios cr hs do t cre vlue. cr op[1:0] udt [3:0] Up-dow couter op opertio cr 0 ho 1 A lod 2 + 1 ic = mx 3 1 dcr = mi A.P. Ppliński 10 12
igitl Logic/esig. L. 10 My 2, 2006 Such uiversl couter is implemeted usig flip-flops to store dt d pproprite excittio circuit. The first implemettio of the excittio circuit c cosist of 4-to-1 -bit multiplexer proceeded by combitiol icremeter d decremeter. cr IN E op[1:0] 1 2 3 Multiplexer i[3:0] Flip Flops 0 P[3:0] [3:0] A.P. Ppliński 10 13 igitl Logic/esig. L. 10 My 2, 2006 A possible VHL descriptio closely follows the block digrm I order to be ble to use simple rithmetic sttemets to describe icremet/decremet opertios, the relevt sigls re specified s beig of the usiged type Fort the usiged sigls we c write sttemets like Y <= P ± 1 Implemettio of the multiplexer is ideticl to tht discussed for the uiversl shift register. Note tht the rchitecture rtl does ot specify detils of the implemettio of the icremet/decremet circuits levig these detils to the sythesizer to decide. -- pp, up-dow couter LIBRARY ieee; USE ieee.std_logic_1164.ll ; USE ieee.std_logic_rith.ll; ENTITY udt IS GENERI ( N : iteger := 4 ; M : iteger := 2) ; PORT ( : IN std_logic ; op : IN std_logic_vector(m-1 dowto 0) ; A : IN std_logic_vector(n-1 dowto 0) ; : OUT std_logic_vector(n-1 dowto 0) ; cr : OUT std_logic ) ; EN udt ; ARHITETURE rtl OF udt IS SIGNAL AA, P, i : usiged(a RANGE) ; TYPE rrvec IS ARRAY (turl rge <>) OF usiged(a RANGE) ; SIGNAL YMUX : rrvec(0 to 2**M-1) ; AA <= usiged(a) ; YMUX <= (P, AA, P + 1, P - 1) ; -- multiplexer i <= YMUX(cov_iteger(usiged(op))) ; cr <= 1 WHEN ((op(0) = 0 ) AN (P = 2**N-1)) OR ((op(0) = 1 ) AN (P = 0)) ELSE 0 ; -- flip-flop process PROESS WAIT UNTIL EVENT AN = 1 ; P <= i ; EN PROESS ; <= std_logic_vector(p) ; EN rtl ; A.P. Ppliński 10 14
igitl Logic/esig. L. 10 My 2, 2006 Simultio wveforms for the uiversl up-dow couter re show below: /udct/ /udct/op 1 2 0 2 3 /udct/ 12 9 /udct/q X 12 13 14 15 0 1 2 1 0 15 14 /udct/cr 0 50 100 Etity: udct Architecture: rtl Ispect the wveforms d verify tht ll opertios re performed s specified i the couter opertio tble. A.P. Ppliński 10 15 igitl Logic/esig. L. 10 My 2, 2006 I this rchitecture of the up-dow couter we specify detils of implemettio of the icremeter/decremeter circuit. Followig cosidertios from sec. 7.2 we observe tht iput d output sigls of the icremeter d decremeter re relted through the followig rithmetic equlities: Icremeter: ecremeter: c + p = 2 d + y c + p = 2 d + y If we deote by d sigl to cout dow, the the rithmetic equlities result i the followig logic equtios: y = p c d = c (d p) c i+1 d d d p i p c c i The 1-bit icremet/decremet compoet c be ow coected ito -bit compoet s discussed i sec. 7.2. The iitil crry c 0 must be set up to 1 for icremet d to 0 for decremet opertio. Otherwise the output will be equl to iput. We c use this property to implemet the ho opertio. c P[ 1:0] ic/dec/ho Y[ 1:0] y y i c 0 d A.P. Ppliński 10 16
igitl Logic/esig. L. 10 My 2, 2006 If we use the followig icremet/decremet circuit, the excittio circuits for the uiversl up-dow couter c be much simplified: From the followig truth tble we c specify the required cotrol sigls: op op 1 op 0 cd c 0 ho 0 0 0 0 lod 0 1 ic 1 0 0 1 dec 1 1 1 0 cd = op 0 c 0 = op 1 op 0 = op 1 op 0 The modified VHL rchitecture c be writte i the followig wy ( flip-flops hs bee omitted): P[3:0] Y[3:0] cr c0 ic/dec/ho cd 0 1 i[3:0] ARHITETURE rtlb OF udt IS SIGNAL P, Y, i : std_logic_vector(a RANGE) ; SIGNAL c : std_logic_vector(n dowto 0) ; c(0) <= op(1) ; grt: FOR i IN 0 TO N-1 GENERATE -- IN/E Y(i) <= P(i) XOR c(i) ; c(i+1) <= c(i) AN (op(0) XOR P(i)) ; EN GENERATE grt ; cr <= c(n) ; i <= A WHEN op = "01" ELSE Y ; -- flip-flop process EN rtlb ; A.P. Ppliński 10 17