Sequential Logic Circuit

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ` 4 Sequential Logic ircuit hapter-4(hours : Marks: )(269 Principle of Digital Electronics) SEUENTIL LOGI IRUIT 4. Introduction to Sequential Logic ircuit Difference between combinational and sequential circuit. 4.2 Triggering methods (edge & level Trigger). 4.3 One bit memory cell - RS latch using NND & NOR. 4.4 Flip Flops - S R Flip flop, locked SR flip flop with preset and clear, Drawbacks of SR Flip flop, locked Flip flop with preset & clear, Race around condition in flip flop, Master slave flip flop. 4.5 D and T flip flop. 4.6 Excitation table of flip flops. 4.7 Study of I 7474 and 7475. 4.8 pplications of flip flops - synchronous counter: up/down, decade, 3 bit synchronous counter design, ring counter, twisted ring counter with wave forms, 4 bit shift register (SISO, SIPO, PISO, PIPO) with waveforms, Study of I 749 (mod 6, mod 2).. What is Sequential ircuit?explain with the help of block diagram ns.there are many applications in which digital output are required to be generated in accordance with which the input signal are received. These requirements are not fulfilled by combination logic system. These applications require output to be generated that are not only dependent on the present output to be generated, but they are also dependent on the on the history of these inputs. The past history is provided by feedback from the output back to the input. External Input ombinational ircuit Output from ombinational ircuit Memory Element Figure shows block diagram of sequential logic circuit

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) sequential circuit consists of combinational circuit, which accepts digital signal from external input and from output of memory elements and generates signals from external outputs and for inputs to memory elements. memory is a same medium in which one bit of information can be or retained until necessary and thereafter it contents can be replaced by new value. The contents of the memory elements can be changed by the output of combinational circuit, which are connected to its input. Hence output of sequential circuit is dependent on external input and present content of memory element. The new content of memory element is referred to as NEXT STTE. Hence the output of a sequential circuit is function of the time sequence of input and the internal states. 2. List different types of Sequential ircuits ns.sequential circuits are classified in two main categories known as ) synchronous sequential circuit 2) Synchronous sequential circuit synchronous Sequential ircuit sequential circuit whose behavior depends upon the sequence of which input signal change is referred to as synchronous Sequential ircuits. Such circuits are generally used to provide time delays in memory elements. They operate without a common clock. Synchronous Sequential ircuit sequential circuit whose behavior can be defined from knowledge of its signal at discrete instant of time is referred to as Synchronous ircuits. In these systems the memory elements are affected only at discrete instant of time. The synchronization is achieved is affected by timing device known a SYSTEM LO. They require the common clock. The memory elements used are flip-flop, which are capable of storing binary information. 3. Define FlipFlop? ns. basic digital memory is known as flip-flop (FF). It has two stables, which are known as logic state and logic state. These devices remain in one of these states until triggered into the other state. The flip-flop is a basic element of a sequential logic system. Using flip-flop and combinational logic circuit any sequential circuit can be designed. 2

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ny device or circuit that has two stable states is said to be bistable for instance, a toggle switch has two states i.e. open or closed. flip-flop is basically a bistable multi-vibrator type circuit other name of this circuits are trigger circuit, two toggle circuit, one bit storage cell or latch. The different names of flip-flop are RS, clocked RS, -, (master-slave), D-type flip-flop & T-type flip-flop. 4. Describe RS Flip Flop using NOR gate, List is truth table ns.rs flip flop R Inputs Outputs R S Last State Forbidden Status No hange Reset Set Race S Figures : RS FlipFLop with NOR Gate. In figure output of one NOR gates drives one of the input of the other NOR gate. The S and R inputs are used to set and reset the flip flop respectively. Note : For the NOR gate, if any input of the NOR gate is its output will be irrespective of other inputs. Operation of RS FlipFLop ase : When R = and S = and =, = When S =, R = and =, = a comes out from the upper NOR gate corresponding to =. Now the lower NOR gate has both input and hence a comes out from the lower NOR gate corresponding to =. Hence when R=, S = Flip Flop remain in last state or No change State ase 2: When R = and S = and =, = 3

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) When S =, R = and =, = a comes out from the upper NOR gate corresponding to =. Now the lower NOR gate has one input and other input as (=, S=),hence a comes out from the lower NOR gate corresponding to =. This = is fed as input to upper NOR gate making R = and =, this time a come upper NOR gate. Now the lower NOR gate has both input as (=, S=),hence a comes out from the lower NOR gate corresponding to =. This process repeats till the output is fixed or settled.hence at the end when R=, S = Flip Flop out = and =. Hence when R=, S = Flip Flop goes in Set state ase 3: When R = and S = and =, = When S =, R = and =, = a comes out from the upper NOR gate corresponding to =. Now the lower NOR gate has both input as (=, S=),hence a comes out from the lower NOR gate corresponding to =. This = is fed as input to upper NOR gate making R = and =, this time a come upper NOR gate. Now the lower NOR gate has both input as (=, S=),hence a comes out from the lower NOR gate corresponding to =. This process repeats till the output is fixed or settled.hence at the end when R=, S = Flip Flop out = and =. Hence when R=, S = Flip Flop goes in Reset state ase 4: When R = and S = and =, = If S = and R = a comes out of both NOR gates giving = =. This is condition is forbidden. Figure shows the timing diagram. The output goes high 4

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) when S goes low returns to low when R goes high and stays low after R return to low. 5

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Reset Set Timing diagram for RS Flip-Flop. 5. Describe RS Flip Flop using NND Gate, Draw its symbol and TruthTable 6

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ns.rs Flip Flop using NND gate S Inputs Outputs R S Last State F orbidden Status No hange R eset S et Race R Truth Table SR Flip-Flop using NND Gate In figure output of one NND gates drives one of the input of the other NND gate. The S and R inputs are used to set and reset the flip flop respectively. Note : For the NND gate, if any input of the NND gate is its output will be irrespective of other inputs. ase : S=, R = =, = ( Race ondition ) When S =, R = and =, = a comes out from the upper NND S gate corresponding to =. Now the lower NND gate has one input and Other input as and hence a comes out from the lower NND gate corresponding to =. Hence when R=, S = Flip Flop both R outputs try to become one, this undefined or illegal or Forbidden state. This condition is called as RE condition. ase : S=, R = =, = ( SET ondition ) When S =, R = and =, = S a comes out from the upper NND gate corresponding to =. Now the lower NND gate has both input,hence a comes out from the lower NND gate corresponding to =. This state remains as its, Hence when R R=, S = Flip Flop, output = and =, and the state is called as Set State ase 2 : S=, R = =, = ( RESET ondition ) 7

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) When S =, R = and =, = a comes out from the S upper NND gate corresponding to =. Now the lower NND gate has both input,hence a comes out from the lower NND gate corresponding to =.This is fed as input to upper gate, now R this time upper NND gate both input as, due to which output is. Now this output is fed as input to lower NND gate, whose both input are, making output.this state remains as its, Hence when R=, S= Flip Flop, output = and =, and the state is called as Reset State ase 4: When R = and S = and =, = When S =, R = and =, = a comes out from the upper NND gate corresponding to S =. Now the lower NND gate has both input and hence a comes out from the lower NND gate corresponding to =. Hence when R=, S = Flip Flop remain in last state or No change R State Note : The asic NND gate circuit operation is opposite to that of the NOR gate circuit i.e it needs the input active low for the operation. Hence to have the operation with active high input the R and S input are passed through the NOT gate. The truth table and ircuit is as shown in the figure. 6. What is triggering and Describe its different type ns. In the latches and flip-flops, we use the additional signal called clock signal. Depending on which portion of the clock signal the latch or flip-flop responds to, we can classier them into two types. Level triggered circuits 8

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) 2. Edge triggered circuits oncept of Level Triggering The latch or flip-flop circuits which respond to their inputs, only if their enable input (E or l) held at an active HIGH or LOW level are called as level triggered latches or flip-flops. Fig. shows the symbol of a level triggered SR flip flop and Fig. shows the clock signal applied at its input Types of Level Triggered Flip-flops There are two types of level triggered flip-flops: Positive level triggered. Negative level triggered. Positive Level Triggered FF if the outputs of SR flip-flop respond to the input changes, for its clock input at HIGH (), level then it is called as the positive level triggered S- R flip-flop. The circuit shown in Fig. is a positive level triggered S-RFF. Negative level triggered FF if the outputs of an SR flip-flop respond to the input changes, for its clock input at LOW () level, then it is called as the negative level triggered S - R flip-flop. oncept of Edge Triggering The flipflops which change their outputs only corresponding to the positive or negative edge of the clock input are called as edge triggered flipflops. These flip-flops are therefore said to be edge sensitive or edge triggered rather than being level triggered. The rectangular signal applied to the clock input of a flip-flop is shown in Fig. If the same signal is applied as the clock signal to the flip flop, then its outputs will change only at either rising (positive) edge or at the falling (negative) edge of the clock. There are two types of edge triggered flip flops 9

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Positive edge triggered flip flops. Negative edge triggered flip flops. Positive edge triggered flip flops will allow its outputs to change only at the instant corresponding to the rising edges of clock (or positive spikes). Its outputs will not respond to change in inputs at any other instant of time. Negative edge triggered flip flops will respond only to the negative going edges (or spikes) of the clock. 7. Describe the operation of locked RS flip-flop with NND gate, Draw its circuit diagram and List its truth table S Inputs Outputs R S Statu s lock lock R X X Last State Forbid den Last State No hange Reset Set Race No h ange Figure locked RS Flip-Flop It is often required to set or reset the memory cell in synchronism with a train of the pulse known as lock. Such circuit is referred to as clocked SR (set-reset flip-flop) The clock is a square wave signal because the clock drives both NND and prevents S and R from controlling the latch. Operation is as Follows ase : S =, R= (Set ondition) If S = and R = the output of gate = and =. Now with clock =, S =, R = and flip-flop set = and =. I.e Set ondition ase 2 : S =, R= (Reset ondition) If S = and R = the output of gate = and =. Thus with clock =, S =, R = and flip-flop set = and =. I.e Reset ondition

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ase 3 : S =, R= (Illegal/Forbidden ondition) With S = and R = the output of both gates will be it is a forbidden condition state or a race condition. I.e Illegal ondition or Forbidden State ase 4 : S =, R= (Last State ondition) When both S =, R = and clock = the output & gate = which keep the flip-flop in last state. I.e Last State The above circuits are activated by high level of square wave i.e. why they are called as level triggered flip-flop. Timing diagram lock S R Timing Diagram of locked RS Flip Flop 8. Draw the Logical Symbol for RS FlipFlop and Write its truth table ns.

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Logical Symbol Forbidden / Illegal Race ondition Truth Table 9. Describe the operation of RS flip-flop With Preset and lear, with its symbol and truth table ns.when power is switched ON the state of flip-flop is uncertain i.e. it may be in either set or reset state. In many applications it is necessary to set or reset the flip-flop initially i.e. initial state is to be assigned. This is accomplished by using direct or synchronous inputs referred to as preset (Pr) and clear (r) input. These inputs may be activated at any instant of time and are not used in Synchronism with clock. PR PR S S lock lk R R R R 2

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) PR and R are ctive low inputs. To make preset or clear Inactive they are connected to Logic. Preset & lear When PR =, R = then the NND output of () will be i.e. set the flip-flop Pr = Preset the flip-flop. When PR =, R = then the output of NND gate () will be i.e. Y = i.e. reset the flip-flop. Therefore r = Reset the flip-flop. When Pr =, r = not to be used since it lead to uncertain state. During normal operation Pr = r = i.e. should be connected to logic. In logic symbol bubbles are used for Pr and r input which means these are active low i.e. the intended function is performed when the signal for Pr and r is low. The operation of above circuit is summarized in form of truth table as shown Input Inputs Output lock S R PR R Status X X X X Last State No hange X X For idden Race X X Preset X X lear X X Last State No hange Last State No hange Reset Set For idden Race Figure : Truth Table. State disadvantages of SR Flip Flop, how it is avoided ns.disadvantages of SR flip-flop. Main disadvantage of SR flip-flop is that when R =, S = this state is called as forbidden or illegal state which must be avoided. This is done by modifying SR flip-flop into flip-flop. 2. In flip-flop the outputs & are cross-coupled back at the input through a nd gate. ross-coupled means is connected to S input and is connected to R input with a clock such that S =..clk R =.R.clk. 3

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com). Describe the operation of flip-flop With Preset and lear, with its symbol and truth table ns. Flip-Flop: (Edge triggered) PR Inputs S R R Diagram FLIP FLOP lock X Outputs X Status Last State Last State Last S tate Truth Table flip-flop is improvement over RS flip-flop in which forbidden condition is defined, figure shows flip flop using RS flip flop. & are called control inputs. When =, = irrespective of the clock pulse both the ND gate are disabled resulting S =, R =. Therefore output -remains in the last state. If =, = the lower ND gate is disabled, i.e. S =, R = which sets the flip-flop as soon as clock edge comes since upper ND gate is enabled. If =, = the upper ND gate is disable, hence it is impossible to set the flip-flop, but the flip-flop can be Reset provided if it is not already in Reset condition i.e. if =, the lower ND gate produce a reset trigger as soon as clock edge comes therefore output will reset to '' If =, = it is possible to set or reset the flip-flop if = in last state will be and the upper ND gate produce a set trigger to force =. On the other hand if = in the last state the lower ND gate produce a reset trigger to force =. In either way always changes in opposite state. This is known as toggling meaning switching to opposite state. 4 No h ange Reset Set Toggle No hange

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) PR PR lk lk R R -ve edge triggered FlipFlop with inverted PR and R +ve edge triggered flipflop with PR and R 2. Describe the operation of flip-flop With Preset and lear using NND gate, with its symbol and truth table ns. flip-flop using NND gate Figure one way to build flip-flop. In this flip-flop the output of flip-flop & are cross-coupled to input by means of ND gate. The flip-flop is triggered with +ve level clock i.e. clock should go high & remain high for some time. PR Lock R Fig shows Flip-Flop Timing Diagram Operation :. Reset condition: ( =, = ): When =, =, = & Ǭ =, the lower NND gate passes a reset trigger as soon as clock becomes +ve. This forces to become O and Ǭ =. Hence = & = means reset the flip-flop on +ve edge clock 2. Set condition: ( =, = ) When = and = and = and Ǭ = the upper Nand gate passes a set trigger as soon as the +ve clock arrives. This forces to high and Ǭ to low. Hence =, = means that on +ve clock it will flip-flop. 5

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) 3. Inactive ( =, = ) The = = low the circuit is inactive in state including +ve clock and the flip-flop remains in last or previous state. 4. Toggle ( =, = ) When =, = it is possible to set or reset the flip-flop depending on the current state of the output &. If = and =, the lower NND gate passes a reset trigger on the next +ve clock. If = and =, the upper NND gate passes a reset trigger on the next +ve clock. In either way changes to the complement of last state. Therefore = and = means that flip-flop will toggle on next +ve pulse. Operational truth table Data Input Outputs Inputs Last n State Ǭn S Outputs Ǭn + R Final = Ǭn Last state = Set = Reset = Ǭn toggle The difficulty of both Input R = S = which was not allowed in SR flip-flop s eliminated in flip flop by using feedback connections. Truth table of FlipFlop Input lock X Output X Last State Last State Toggle Status No hange No hange Reset Set Toggle 3. What is Racing and Race round ondition in Flip Flop 6

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ns.in RS flip flop the input condition R=S= is not allowed as it leads to a state == i.e. the output oscillates between these two states. In real the circuit,one of the two gates will operate slightly faster than the other and the circuit will not oscillate but will go in of the two state i.e or, but exact state cannot be predicted. In this case the circuit action is intermediate and a race condition is said to be exist. Figure shows clock is applied to Flip-Flop When input == and when after a time interval of t (the delay through two NND gates in series) the output will change to =, after time interval of t the output will again change back to zero (). nd hence at the end of clock pulse the value of is uncertain. This situation is called as Race around ondition. Race arround conditions means toggling more than once on the same clock edge. Leading Edge t Trailing Edge T This condition can be avoided if tp < t < T. This can be done:. Use R differentiator circuit. In which output changes when +ve edge has struck. y the time the new & signal return to the Input gate the +ve delays to and hence we get once toggling in one clock pulse. 2. Other method is to increase the propagation delay time of the flip-flop; this will take some time for the outputs to change after the clock edge has arrived and therefore returning and arrive too late to cause false triggering but this technique decrease the speed of operation. 3. Yet another way to avoid is to make use of Master Slave -flip-flop. 4. Describe the operation of -MS flip-flop, with its symbol and truth table ns.master-slave Flip-Flop The more convenient way to avoid Racing (Race around condition) to make use of Master Slave flip-flop, one is called Master and other is called as Slave. Here the Master is +ve edge triggered and slave is ve edge triggered flip-flop. The output and of master flip flop drivers the & Input of the slave flip flop. 7

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Since Master is +ve edge triggered it responds to & inputs before slave. Inputs lock lock X X Last State Last State Toggle Last State PR PR lk lk lk Outputs R R Operation ase : If = & = Master set on +ve edge of clock while slave sets on ve edge of the clock. ase 2 : If = & = Master reset on +ve edge of clock while slave reset on ve edge of the clock. ase 3 : If = & = Master toggles on +ve edge of clock while slave toggles on ve edge of the clock. Thus whatever the action of master is on the +ve clock edge will be copied by the slave on the ve clock edge. Hence the name master slave (MS) flip flop. Since & Inputs are taken from slave flip flop there will be no question of toggling more than once on the same clock edge. Hence Racing is avoided. lk Operation 8

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) X Last State Last State Reset Set Toggle Toggle. 5. Draw the waveform MS FlipFlop ns. 6. Describe the operation of Toggle(T) flip-flop, with its symbol and truth table ns. Toggle flip-flop (T-flip flop) Toggle flip flop is similar to flip flop but with & inputs connected together and a common input T. whenever T = ( =, = ). The flip-flop will toggle hence the name toggle flip-flop. If T = ( =, = ). The output will remain in the last state. If T = then the output will toggle. Truth Table : 9

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) lock Input(T) Output(n + ) Status Ǭn Toggle n Last State X n Last State PR 7. T List S lk R R T FlipFlop Using SR F/F PR T T lk lk R R T F/F U sing FlipFlop Symbol pplication of Flip-Flop ns.some of the common uses of flip-flop are ) ounce elimination switch 2) Latch 3) Registers 4) ounters 5) Memory etc. 8. Describe operation of Delay (D) flipflop with its circuit diagram and Truth table ns. D or Delay flip-flop 2

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) The RS flip flop has two data inputs S & R generating two signals to drive a flip-flop is disadvantageous. gain there is possibility of R & S being resulting in forbidden condition of the flip-flop. PR PR D S lk R D lk l k R R D FlipFlop Using SR F/F D FlipFlop Using F/F This results in design of D-flip flop, which requires a single data Input D to drive the flip-flop. Figure shows D-flip flop using RS flip flop. This is design by connecting S to R Input through Inverter. nd Input is labeled as D. PR D lk R Symbol lock input D X Output Y Last State Truth Table This kind of flip flop prevents the value of D from reaching the output until a clock pulse occurs hence it is called as Delay flip-flop. Operation When clock = irrespective of value of D-both ND gate are disabled resulting S=, R = under this condition Y will remain in the Last State. When clock is, D =, the upper ND gate is enabled whereas the lower ND gate is disabled due to Inverter. This results in S =, R =, therefore Y = i.e. the value of Y follows the value of D in presence of clock. When clock = D =, the upper ND gate is disabled whereas the lower ND gate is enabled due to Inverter. This results in S =, R =, 2

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) therefore Y = i.e. the value of Y follows the value of D in presence of clock. D-flip flop if also known as D-latch this is because whenever clock pulse is removed the output Y will Latch ON to its Last State. The DLatch is used to store the binary number. Timing diagram: (for value edge trigger) lock D D-flip-flop using flip flop type using SR Flipflop : figure is shown above along with D 9. List and Describe Important Flip-Flop Timing related to flipflop ns.the circuit components are not ideal components. omponents like diode, transistor etc require some finite amount of time for switching from one state to another i.e. ON to OFF and OFF to ON. This is because of different types of capacitance associated with component for e.g. function capacitance. Generally the switching time is very small in terms of micro and nano second but input has more effect on operation of device at high frequency applications. The different delays associated with flip-flop are:. Propagation delay time (tp) 2. Setup time (ts) 3. Hold time (th) Propagation Delay Time (tp) 22

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Propagation delay time (tp) is the amount of time it takes for output of gate or flip-flop to change its state after input has changed. For Example: if tp = 5 nsec then i.e. it will take 5 nsec to change output to new state after input has changed. Setup Time (ts) The time (ts) required for the input data to settle before the clock arrives. For Example : If ts = msec than input data must because present at least msec ahead of clock pulse otherwise there is possibility of getting wrong output. Hold Time (th) It is the time for which the data must because present stable after clock pulse arrives. For Example: If th = 5 msec then data must because present upto 5 msec after clock pulse has arrived. 2.What is excitation table? Write the excitation table for SR flipflop? ns. The truth table of a FLIP FLOP is also referred to as the characteristic table and specifies the operational characteristic of the FLIP FLOP. In the design of sequential circuits, we usually come across situations in which the present state and the next state of the circuit are specified, and we have to find the input conditions that must prevail to cause the desired transition of the state. y the present state and the next state we mean the state of the circuit prior to and after the clock pulse respectively. The excitation table tells the designer the minimum inputs that are necessary to generate a particular next state when the current state is known. Excitation Table SR FlipFlop 23

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) For example the outputs of an S-R FF before clock pulse are n = and n+ and it is expected that these outputs should remain unchanged after application of clock. Then what must be the values of inputs S and R to achieve this? Refer to the truth table of SR FF to answer this question The answer is, for the following two conditions the outputs remain unchanged at = and = ondition :Sn and Rn= Refer first row of Table. ondition 2: Sn = Rn = Refer third row of Table From the two conditions mentioned above we conclude that Sn input should be equal to and Rn input can be or (don t care) in order to achieve our objective of maintaining = and = before and after clock. Similarly we can find the input conditions for aft the possible situations that may exist on the output side. The table containing all these output situations arid the corresponding input conditions is called as the excitation table of a flip flop. The excitation table of SR flip flop is s in Table. Description of excitation table of SR FF: ase : already discussed case. ase II: should change from to This is set condition. Therefore Sn=l and Rn= should be he input ase III: should change from to This is reset condition. Therefore Sn should be and Rn should be 24

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ase IV : should be. No change For this requirement there are two possible input condition ondition : Sn = Rn = ie No change in output ondition 2 : Sn = and Rn = From these condition we conclude that Sn can be either or ie don t care and Rn =. Hence the input corresponding to this Sn = X Rn = 2.Write Excitation table for FF, SR FF, D FF, T FF ns Excitation Table for SR FlipFlop Excitation Table for FlipFlop Excitation Table for T FlipFlop Excitation Table for D FlipFlop 25

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) 22.Describe the I 7474 Dual D type positive edge triggered flipflop with preset and clear ns. Pin Diagram Truth Table Functional Diagram Logical Diagram ounter 26

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) 23. What is counter? List different types of ounter? Describe each of them? ns. sequential circuit that goes through a prescribed sequence of state upon the application of input clock pulses is called as counter. It is circuit used for counting the pulses is known as counter. Number of state through which counter progresses is called as Modulus of ounter ie MOD of counter. For any digital system especially for computer, counter are most useful and versatile subsystem. counter is driven by a clock can be used to count the number of clock cycles. Since the clock pulses occurs at known intervals the counter can be used as an instrument for measuring time and therefore period or frequency. In a counter the sequence of state may be binary or D or any other count. ounters are found in almost all equipment containing digital logic. The counters are classified as ) synchronous or serial or ripple counter 2) Synchronous or parallel counter. 3) ombination counter. asic components used in counter is flip-flop. ) synchronous or ripple or serial counter These counter are very simple in hardware as well as in operation. It is an series combination of flip-flop, where the output of st flip-flop is connected as clock input of 2nd flipflop, the output of 2nd is connected as the clock input of 3rd and so on, it is called a binary counter, or series counter or ripple counter. Since in the counter in which the output of one flip-flop drives the clock input of another counter are called ripple counter or asynchronous counter. ut these counters have disadvantage of speed limitation because here each flip-flop is triggered by previous flip-flop and the total propagation delay time becomes equal to the sum of the individual propagation delay thereby decreasing the speed of operation. 2) Synchronous or parallel counter In these counter the transition are simultaneous i.e. all the flip-flop change their output simultaneously. This is achieved by connecting all the flip-flop to same clock pulse simultaneously i.e. all the flip-flop are directly clocked by same clock. The increase in speed is usually obtained at the price of increased hardware i.e. hardware is increased. 3) ombinational ounter 27

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Serial and parallel counters are used in combination to compromise between speed of operation and hardware count. Such counters are called as combinational counter. ounters can be designed such that each clock pulses advances the content of the counter by one i.e. it is operating in a count up mode i.e. up counter. The opposite is also possible i.e. the counter operate in the countdown mode called as down counter. Many times counter may be cleared or preset so that every flip-flop contains zero s or one s or can be preset to required binary numbers..24.describe the operation of 4 bit synchronous counter with help of circuit diagram.25.describe the operation of 4 bit Serial counter with help of circuit diagram.26.describe the operation of 4 bit Ripple counter with help of circuit diagram 28

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ns. 4-bit binary asynchronous or serial or ripple counter Logic D D lock Logic Fig. Shows a 4bit binary asynchronous counter. It uses four negative edge triggered flip-flop. ll the flip-flop will operate in the toggle mode because there and input are tied to Vcc. The clock pulse are applied to the flip-flop. The output of flip-flop drives clock input of flip-flop, the output of flip-flop drives clock input of flip-flop and the output of flip-flop drives clock input of flipflop D. Since all flip-flop are negative edge triggered flip-flop they require a transition of to at their clock input to toggle or change the state. lock (Intially) 2 3 4 5 6 7 8 9 2 3 4 5 D ount 2 3 4 5 6 7 8 9 2 3 4 5 6 29

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) 6 7() Truth Table for 4 bit ysnchronous ounter Timing diagram Operation of ounter Initially all the flip-flop are cleared by using a common low clear signal. Therefore D = On the first clock pulse flip-flop will toggle from to this will not trigger flip-flop because it requires a change in to in. Therefore remain in last state and since does change its state also and D remain in last state. Hence on the first clock pulse we get output as, D = On the second clock pulse flip-flop again toggles from to. This now triggers flip-flop, Now FlipFlop toggles from to. This will not affect flip-flop because flip-flop requires a change of to in flip-flop. Therefore remains and so is D flip-flop. Hence on 2 nd clock pulse we get D =. On the 3rd clock pulse flip-flop changes from to, flip-flop remains at and and D flip-flop remain at therefore, D =. th On 4 clock pulse flip-flop changes from to therefore flip-flop now changes from to. Now flip-flop is triggered which will change from to but this will not effect D because it requires a change from to in flip-flop. Hence D remains. Therefore or 4th clock pulse we get, D =. 3

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Thus it is observed that flip-flop toggles with every clock pulse it receives. flip-flop toggles whenever flip-flop changes from to. flip-flop toggles whenever flip-flop changes from to and D flip-flop toggles whenever changes from to. Hence on 5th clock pulse we get D =. On the next clock pulse flip-flop changes from to, flip-flop change from to. Therefore flip-flop changes from to. Hence D changes from to, therefore all flip-flop are cleared again & we get, D = Thus this counter can count from to 5 i.e. totally 6 count (or states). The number of discrete states through which the counter can progress on the application of pulse is given by 2 n where n= number of flip-flop used into the counter. If we connect 5 flip-flop the counter will progress through to i.e. 32 counts ( to 3)..27what is MOD N counter? ns.in a binary ripple counter the number of counts or discrete state through which the counter can progress after application of clock pulses is called as modulus of counter. The number of discrete state is given by 2n where n is number of flip-flop used in counter. Therefore we can easily design a counter which counts through 2,4,8,6,32 by using required number of flip-flop. ut often counters other than module, 2,4,8,6,32 etc are required. For example : Mod7, mod6, mod5 etc. These counters can be designed by nearest highest modulus counter by skipping some of the counts. For example : Mod7 counter can be designed from mod8 counter by skipping one of the state. Similarly a mod6 counter can be designed from mod 8 counter by skipping two of the states..28.describe operation of Mod 7 or divide by 7 counter ns. Logic lock 3

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Fig : Mod-7 ounter 32

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) WaveForms : L 2 3 4 5 6 7 r ount State 2 3 4 5 6 7() Mod 7 counter can be constructed from nearest highest modulus counter i.e. mod8 but skipping of state. Fig. Shows mod7 counter with some feedback to skip one of the state. It is convenient to skip last state i.e. = in natural count sequence of the counter. The arrangement is shown in fig. Truth table lock 2 3 4 5 6 7 () () () Working During count 7 =, if are connected to NND gate, whenever occurs at the input of NND gate the output of NND gate is low(). If the output of NND gate is connected to all clear inputs of all the flip-flop, as soon as = occurs immediately all the flip-flop will 33

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) clear. Therefore the counter progress from to and count is skipped. Since remaining states are only 7 it is called as mod7 counter. fig. Shows the waveform for mod7 counter..29.how to design Different MOD counters. ns.mod 6 ounter To design mod6 counter we require 3 flip-flop or mod8 counter which is nearest highest modulus. Hence a mod6 counter can be formed by tieing(connecting) input to the NND gate. When = then output of NND gate becomes how which clears all the flip-flops. Therefore counter progress from directly and here count and are skipped. Mod 5 TO ll lear input of the Flip Flop counter s mod7 and mod6 counter is designed mod5 can also be designed using mod8 counter. In this design the inputs are tied to NND gate. In this counter progress from to because when = the output of NND gate is low thus clearing all flip-flop. In this counter states, and are skipped. Mod3 TO ll lear input of the Flip Flop counter Mod3 counter is design by mod4 counter which utilizes 2 flip-flop. In mod3 state is skipped. This done by following gating circuitry. Logic lock 34

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Truth table L 2 3() when = the NND gate produce low output which clears flip-flop and counter from state moves to state..3.describe operation of MOD 8 ounter or Parallel ounter.3.describe operation of 3it Synchronous ounter or Parallel ounter Logic Y X lock Logic ns. 3 bit binary synchronous or parallel counter: TruthTable 35

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) L 2 3 4 5 6 7 8 Timing Diagram 2 ount State 2 3 4 5 6 7 8() L 3 4 5 6 7 The speed limitation in the asynchronous counter is over come by using parallel counter. The difference here is that every flip-flop is triggered by clock. Fig. Shows mod8 counter. s mod8 has natural count of 8 it requires 3 flip-flop. gain all flip-flop input are tied to Vcc and the flip-flop will toggle with each negative transition of clock. The output ND gate X is high whenever clock is high and is high. Therefore does not change its state. changes state with every other clock i.e. when output of X ND gate changes from to. Similarly output ND gate Y goes high when clock is high and and are high, therefore flip-flop changes its state with every 4 th clock change from to. The truth table and waveform is as shown in fig..32.describe operation of Mod7 synchronous counter 36

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ns.mod8 counter is taken as basis for building up other modulus counter. The mod8 counter has got 8 discrete states to. If we skip one of the states we get mod7 counter. 37

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Logic lock Logic ircuit Diagram for MOD-7 ounter Truth table L 2 3 4 5 6 7 Fig. Shows a mod7 counter which skip the state. When = during count7 the output of the NND gate Z is. The output of NND gate is connected to k-input of flip-flop. Therefore the input condition for flip-flop after the state is = and =. Therefore when next clock pulse comes is prevented from resetting and continue to remain as whereas and toggles from to as usual. Therefore counter proceeds from to and we get mod7 counter. 38

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com).33.describe operation of Mod6 synchronous counter ns. Logic lock Logic ircuit Diagram for MOD-6 Synchronous ounter Truth Table L 2 3 4 5 6 7 mod7 counter can be easily modified to form mod6 counter by skipping two states &. If the output of NND gate Z is removed from flip-flop and connected to the input of flip-flop and mod6 counter is formed. The arrangement is shown in fig. On the 7 th count the output of NND gate is low corresponding to a low input i.e. for flipflop = & =. Hence flip-flop is prevented from resetting during the transition from 7 to count. The counter progress from count7 to count2 and state & are omitted..34.describe operation of Mod5 synchronous counter ns. The mod5 counter can be implemented by combining the method used to form the mod7 and mod6 counter. If the output of the NND gate Z is connected to the input of both flip-flop and a mod5 counter is 39

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) formed. This is true since the NND gate output is low during count which means that neither flip-flop nor flip-flop is allowed to reset during the natural transition from count7 to count only flip-flop is allowed to reset and thus counter advances from state7 to state3. Fig. Shows mod5 counter. Logic Logic Logic ircuit Diagram for MOD-5 Synchronous ounter Truth Table L 3 4 5 6 7 3.35.Describe operation of Mod3 synchronous counter ns. mod3 counter can be formed by using two flip-flop. If we connect the output of flip-flop to the -input of flip-flop. ount can be skipped. The arrangement is as follows. Logic lock Logic 4

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ircuit Diagram for MOD-3 Synchronous ounter Truth table L 2 3 4() When the first clock pulse occurs the flip-flop will toggle from to. On the next clock pulse changes from to whereas changes from to on the 3 rd clock pulse flip-flop. remain high because = is low [=,=] on the 4th clock pulse remain high toggles from to. Thus the count sequence are,,, etc. and count is skipped. Hence it is a mod3 counter..36.describe operation of Mod6 synchronous counter.37.describe operation of 4 bit synchronous counter.38.describe operation of Divide by 6 parallel counter ns. 4 bit binary synchronous or parallel counter: Logic D lock Logic ircuit Diagram of 4-bit synchronous ounter Truth table 4 D

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) L 2 3 4 5 6 7 8 9 2 3 4 5 6() D.39.Describe Operation of 3 bit /Mod 8 / Divide by 8 Down ounter ns. Logic lock Logic ircuit Diagram of Mod8 Down ounter Truth table 42

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ount 7 6 5 4 3 2 7 nother Figure For Down ounter Logic lock Logic three flip-flop can be used for up as well as down counter. The truth table is as shown in fig. Thus if the output are taken from the true side i.e. it works as up counter and if the output is taken from the false side i.e. it works as down counter. Truth table is shown operation is similar to up counter. true down counter can be formed by triggering the input of each flip-flop with false side of the previous flip-flop instead of true side as shown in fig. Here changes state each time the clock goes low however changes state when goes high. Since this is the time when goes low. Similarly changes state when goes high or goes low. 43

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com).4.describe operation of 3 bit serial Up-Down ounter ns. Logic Up Logic lock Down Logic ircuit diagram of 3bit Serial Up Down ounter If the flip-flop are triggered from true side of previous flip-flop we get up counting. If flip-flop are triggered from false side of previous flip-flop we get down counting. Fig. Shows a 4bit binary serial up down counter line is. The upper ND gates are enabled and lower ND gates. are disabled therefore flip-flop are triggered from true side of previous flip-flop. Hence we get up counting to start up count initially all flip-flop are cleared to Zero If the countdown count line is and count up line, Lower nd gates are enabled and upper ND gates are disabled now the flip-flop are triggered from the false side of previous flip-flop and we get down counting to start down count initially all the flip-flop are preset to..4.describe 3bit Up-down serial counter using NND ns. When the count down line is low and count up line is high the gate X is disabled and gate Y is enabled. Therefore will not pass through X but will pass through Y. In passing through gate X, gets inverted and thus appears at the inputs of next flip-flop as which gives a count up fashion. Fig. Shows on next page shows the diagram of counter. 44

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Logic Logic Up lock Down Logic ircuit of 3-bit Synchronous UP-Down ounter With the count down line is high the count up line is low. Y is disabled and X is enabled. Thus is inverted as it passes through the gate X and appears at the input of the next flip-flop as and this work as up-down counter..42.describe operation of 4bit Synchronous /parallel up/down counter ns.fig. Shows a 4bit parallel up-down counter. It is former by using some technique as in parallel counter. For up counting count up line is made and for down count down count line is made. Logic UP Logic D D lock Down Logic 45

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) ircuit diagram of 4bit Synchronous Up Down ounter ount up operation If count up line is, is the output of NND gate Z is which makes & of flip-flop. Therefore will toggle on next clock pulse where also changes from to. Similarly if count up line is, & are, output of NND gate Z2 is, which makes & input flip-flop. Therefore will toggle on next clock pulse where and change from. Similarly D flip-flop will change whenever, and are all changing from to. Down ount operation If count down line is is the output of NND gate Z is which makes & of flip-flop =. Therefore will toggle on next clock pulse whereas changes from to or changes from to. Similarly will toggle whenever & are changing from to and D will toggle whenever, and change from to. pplication of counter ounters are used to count numbers but in addition they are used in digital system for various purposes s they can be used to count the occurrence of any event, frequency division or generating timing sequence to control operation in digital system. few important applications are ) Precision timer interval meter. 2) Digital clock 3) Digital voltmeter. 4) TV horizontal and vertical timing pulses generator. 5) Measurement of frequency. 6) ounting of objects like in bottling plants. Register.43.What is register?list Different types if register? ns.asically all most all digital signal processing requires the storage of information, however momentary that storage may be. The fundamental storage unit is flip-flop which can store only a bit of information for storing more information group of flip-flops may be used together. Hence flip-flops can store bit of information. It is called as bit register. n array of flip-flop is required to store binary information, the number of flip-flops required are equal to the number of bits in the binary word (-FLIP FLOP for bit) and is referred to as a register. Register find application in variety of digital system including microprocessor. E.g. Intel 885 has 7-8bit register and one-five-bit register called as flag. 46

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Registers are to classified depending upon the way in which data is entered and retrieved. They are as follows: ) Serial in Serial out(siso) register 2) Serial in Parallel out (SIPO) register 3) Parallel in Parallel out (PIPO) register 4) Parallel in Serial out(piso) register. Register can be designed using discrete RS,,MS or D-type flip-flop. 44.Describe Operation of 4 it serial shift register (SISO/SIPO) Serial Input D D Serial Output ircuit Diagram of 4bit Serial Shift Register Fig Shows a 4bit binary serial-in / serial-out shift register. The serial data is applied at serial input at and output can be taken serially at D and parallel output can be taken serially at,, and D. Let a number to be entered into the register. Initially all flipflop are cleared and then LS is applied at serial input on the first clock pulse LS is loaded into the first flip-flop then second LS is applied at serial input and on the second clock pulse second LS is loaded in the first flip-flop and LS is shifted into second flip-flop. Similarly the 3rd LS and MS are applied at serial input and after 4 clock pulses number can be loaded into that register. fter entering the number of clock pulses are stopped. The output can be taken at once at,,,d in parallel and shifted out serially at D one by one by applying clock pulses. Since LS is entered first this operation is called right shift operation. 47

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com).45.describe 4-bit Parallel in Parallel out (Parallel in serial out (PIPO/PISO)) shift register: 3 2 Parallel Input Serial In 3 2 3 2 Serial Output Logic 3 2 Parallel Output Fig. Shows 4bit parallel in parallel out or serial out shift register. It takes the help of preset Input to load the number into register. Hence it is also called as presetable shift register. Initially all flip-flop are cleared by applying a low clear signal at all clear input. The number to be entered is applied at 2 3 22 2 2 then load line is made high and the number is shifted into the register. Let the number to be entered is with load line (high), the output of NND gate are respectively. '' output from NND gate preset the flip-flop where as '' output from NND gate retain '' on the flip-flop. Hence we get 32 =. fter shifting the number the output can be taken parallel or serially by applying clock pulses..46.describe the operation of Ring or circulating counter ns 48

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Logic D D lock Logic Fig. Shows circuit of ring counter. It is a serial shift register with direct feed back i.e. D output of D flip-flop is connected to input of flip-flop and D is connected to input flip-flop. Suppose initially all flip-flop are reset and clock pulse is allowed to run. Nothing will happen since =(D=) and =(D=) and it continue to remain. Therefore to start the counter is made by presetting of flip-flop. Hence on next cycle of clock, in will be shifted to and again resets, since D=; on the 3rd cycle of clock a in shifted to and on 4 th cycle in is shifted to D when D become, = and = for flip-flop therefore on 5th cycle again set to and with every other clock pulse this goes on shifting from flip-flop to other. Since circulates around the counter it is called as Ring counter or circulating counter. lock D Waveforms of Ring ounter 49

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Shift counter or ohnson s counter (Twisted Ring ounter) onsider a 3-stage shift register if connected to input of flipflop and is connected to input of flip-flop result in a counter known as shift counter or ohnson s counter. This type of connection is called as Inverse feedback. Fig. is as shown. ssume that all flip-flop are in reset condition and the clock is allowed to run. Since is, is therefore =,= for flip-flop. Hence will set to on st clock cycle of clock whereas and remains due to shifting operation. Logic lock Logic During 2nd clock cycle remain, since =, in is shifted to and remain. On 3rd cycle of clock remain, in is shifted to and one in is shifted to. Thus on 3 rd cycle of clock all the flip-flop set to. s soon as =,= therefore, =,= for flip-flop. Hence on 4th cycle of clock, will reset where as and remain due to shifting operation. On 5th clock cycle remain. in is shifted to and in shifted to. on 6th cycle of clock remain, in is shifted to, and in is shifted to. Thus all flip-flop reset again. ll the states as Mod 6 counter. Truth table Equivalent decimal count 3 7 6 4 5

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Illegal states In the truth table counts 2 & 5 are missing these are called as illegal states of counter. Suppose the counter starts from (2), when the power is st applied following changes occur when clock pulse are applied. st clock pulse 2nd clock pulse Thus the counter oscillates between illegal states &. On order to avoid this one method is to use NND gate as shown. Preset of flip flop are all one corresponding to illegal state therefore output of NND gate is low. The output of NND gate is connected to preset of flip-flop. Therefore any time occurs will set to. ounter changes from to. Since is one of natural count sequence and therefore counter will operate as desired. lock Waveforms of Twisted Ring ounter 5

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) 4 it shift or ohnson counters Logic D D lock Logic Truth - Table D inary equivalent 3 7 5 4 2 8 ut in this counter the illegal states are 2,4,5,6,9,,,3. inary count State New state New binary 2 5 4 9 5 6 3 9 2 4 6 3 Hence from above table it is seen that when counter is started in any illegal state counter will progress through count 2,5,,6,3,,4,9,2 which are undefined. Thus to care this problem again the inputs are considered. These inputs are true during count 2 and count. 52

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Therefore will start counter with. D onnect to Preset of and D flip flop 47.ompare Register and ounter ns..48. ompare.ripple ounter 2. synchronus and Synchronous counter 3.obinational and Sequential circuits Ripple ounter Ring ounter This counter are designed using T This counter is designed using DFlipFlop i.e. each FlipFlop toggle on FlipFlop i.e. each FlipFlop latch the every clock pulse. data on every clock pulse. Here output of first FlipFlop s given as 2 Here each FlipFlop is simultaneously clock to Next FlipFlop. Diagram driven by Same clock.. Diagram 53

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Here counter output is in sequence. i.e.,2,3,_,_,_ 3 Here counter sequence. output is not in Ripple counter can be up counter or 4 This counter can be multiply by 2 or Down counter. divide by 2 counter. The output of last FlipFlop is not 5 Output of last FlipFlop is connected connected back back to input To make Ring or ohn counter. Ripple counter are used as Divide by N 6 Ring counter are useful as sequence counter. generator. Synchronous counter In synchronous counter all flip flop are Triggered by clock simultaneously. Since all FlipFlop are triggered simultaneously No propagation delay and speed is more ompared to asynchronous counter. Hardware requirement is more. Difficult to construct. Glitches are not present in o/p. It is also called as parallel counter. 2 Diagram. 7 3 4 5 6 Generally while designing synchronous 8 Mod N counter the initial counter are Skipped.i.e. for Mod 3 counts will be,, count is skipped. ombinational synchronous counter In asynchronous counter every flip flop is triggered by previous flip flop output. synchronous counter propagation delay Is more since output of one FlipFlop trigger next Flip flop hence operating speed is slow. Hardware requirement is less. Easy to construct. Glitches are present in output. It is also called as serial or ripple counter. Diagram. Generally while designing asynchronous Mod N counter last count from truth table skipped. i.e. for Mod 3 count will be,,,count is skipped. Sequential 54

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) In combinational logic circuit the output at any Instant of time depend upon the input present at that instant of time. No memory element is needed,since it 2 does not need past information. Diagram. In sequential logic circuit output is depended on present input and the past input s output. There are memory element to store past Information. Diagram. No feedback is needed. In sequential circuit feedback is used to onnect output of combinational logic to Memory and output of memory element to ombinational circuit. In sequential circuit may be synchronous or synchronous.i.e. depending on how clock is connected. Flip flop, ounter, Register, etc are example of sequential logic circuit. In combinational differentiation. there 3 is no such 4 Encoder, Decoder, Mux, Demux, 5 omparator, ode converter are example of combinational logic design. ombinational circuit design is done 6 with Truth table and -Map reduction. Sequential circuit are design using Excitation table and -Map reduction..49.describe I 74754bit bistable latches ns. Pin diagram 55

Prof.Manoj avedia ( 98674297 ) (urallalone@yahoo.com) Truth table.5.describe the I 749 decade ounter ns. Pin diagram Functional Diagram 56