International Journal of Advancements in Research & Technology, Volume 2, Issue5, May-2013 5 Studying Impact of Various Leakage Current Reduction Techniques on Different D-Flip Flop Architectures Anbarasu.W, Udaiyakumar.R 1 PG student, Department of ECE,SCT, Coimbarore, India; 2 HOD of ECE, SCT, Coimbatore,India. Email: anbuwilliamss@gmail.com, udai.skct@gmail.com. ABSTRACT In the present scenario the technology is getting finer. Hence there is an aggressive scaling of CMOS device and abbreviates the device density. Lowering the supply voltage leads to lower threshold voltage and oxide thickness. High device density and lower threshold voltage result in significant increase in the leakage power dissipation. It cannot be neglected anymore. This fact has motivated a lot of researchers and technologists to choose leakage current minimization techniques. Therefore it is necessary to reduce leakage power of portable battery operated devices. The main objective of this paper is study of existing leakage current reduction techniques and different D Flip-Flop architectures, and comparing them in terms of ability to reduce leakage and their associated delay overhead. The further approach is to combine different leakage reduction techniques in a single design. Extensive SPICE simulation results were reported using 16nm process technologies. eywords : DFF, Leakage current, CMOS stacking. 1 INTRODUCTION 2 SOURCES OF LEAAGE CURRENT.wift growth in semiconductor technology has led to S shrinking of features size of transistor. This has allowed for a large circuits with complex functionality fabricated on a single chip to achieve higher density, performance and lower power dissipation in order to abbreviate the CMOS technology feature size. As per this technology trend, transistor leakage power has increased exponentially. The modern portable battery operated devices such as, cell phones, laptops; PDAs are affected by high power dissipation. Due to this power dissipation, the battery life is reduced. However there is no way to neglect tradeoff between power, delay and area. That s why the designers are required to choose appropriate leakage current reduction techniques. Power consumption of CMOS consists of dynamic and static power. The main function of dynamic power is to charging and discharging of load capacitance at an average frequency over any given interval time. An effective power technique to reduce dynamic power dissipation is supply voltage scaling. Thus in deep sub micron process (DSM) we lower the supply voltage in order to increase the leakage power. There are various techniques to reduce the static power dissipation. The remaining of the paper is organized as follows: Section II describes sources of leakage current in DSM. This is followed by previous work regarding existing various leakage current reduction techniques in section III and different D Flip-Flop architectures in section IV. Section V proposes techniques such as, MTSTAC and SCSTAC. Simulation procedure and results are provided and also comparison of results is given in section VI. Section VII concludes this work [1],[2] Leakage current is mainly due to reduction in Vth, oxide thickness and channel length. Among the sources of leakage current this project mainly concentrates on sub threshold leakage current. Figure 1: Leakage current mechanism of deep sub micron transistors In Figure 1, I1 is the reverse-bias p-n junction leakage current, I2 is the sub threshold leakage current and I3 denotes the oxide tunnelling current. I4 is the gate current due to hot-carrier injection and I5 is the Gate- induced drain leakage current. I6 indicates the channel punch through current. The sub threshold leakage current is the current that flows between the source and the drain of a MOSFET when transistor is operated in sub Vth, due to a weak inversion layer [1].
International Journal of Advancements in Research & Technology, Volume 2, Issue5, May-2013 6 3 EXISTING CIRCUIT LEVEL LEAAGE REDUCTION TECHNIQUES The static power CMOS circuit is determined by the leakage current through the transistor. To suppress the power consumption in low voltage circuit, it is necessary to reduce the leakage power in both active and standby modes of operation. Standby leakage current is the current flow through the circuit when the circuit is in idle state. Active leakage current flow occurs, when the device is in use Some of the already proposed leakage current reduction techniques are: 3.1 Power Gating Techniques 3.1.1 MTCMOS techniques: The Multi Threshold technique is the combination of both high V th and low V th. The high V th prevents sub threshold leakage in standby mode. The low V th has high operating speed with small propagation delay [1] [5]. 3.1.2 SCCMOS techniques: Super Cut off CMOS is an alternate to MTCMOS. In this scheme the sleep transistor are under driven (OR over driven) when in standby mode [3] [4]. 3.2 Forced Transistor stacking (FTS) Stacking of transistor is an effective way to reduce leakage current in active mode. A single transistor of width W is replaced by two transistors each of width W/2. Reduction in Figure 2: 9 TSPC D Flip Flop leakage current takes place when multiple transistors are The Flip-Flop consists of 9 transistors as shown in Figure 2. turned off. This is known as, Stacking Effect (or) Self Reverse True Single Phase Clock signals which are never inverted and bias effect. The transistor stacking technique depends upon fit both static and dynamic CMOS circuits are applied. The the source voltage V s. Thus the sub threshold leakage current clocked switching transistors are placed closer to V dd/ ground reduces exponentially [1]-[2], [7]. for higher speed. The state transition of the Flip-Flop occurs at the rising edge of the clock signal. No clock skew exists except 3.3 Sleepy Stack (SS) the clock delay problems [], [13]. The sleepy stack approach has a combination of both sleep and stack approach. Place a sleep transistor in parallel with 4.2 NAND Based D Flip Flop one of the stacked transistors. The stacked transistor suppresses the leakage current and sleep transistor are placed parallel to one of the stacked transistors. It reduces the resistance path from V dd to gnd. So the delay is reduced during active mode [6]. 3.4 Multi Threshold Stacking (MTSTAC) It is a combination MTCMOS and FTS. During standby mode, multiple transistors connected in series are turned off and it saves leakage power. In Active mode with high V th, stacked transistors are turned on, hence normal operation of the circuit occurs [11]. 3.5 Super Cut off Stacking (SCSTAC) It is a combination of SCCMOS and FTS. To stack the sleep transistor are under driven (OR over driven) condition. It reduces the leakage current when the multiple sleep transistor connected in series are turned off [11]. 3.6 Lector This technique introduce two transistors [PMOS and NMOS] called leakage control transistors (LCTs) which are inserted in series between pull-up and pull-down network. In the two transistors, anyone of the transistor is always cut off for the applied input. This increases the resistance path from V dd to gnd and also decreases the leakage current. The main advantage of Lector technique is that it works in both active and standby mode [4], [9], [10]. 4 DIFFERENT D FLIP FLOP ARCHITECTURE 4.1 True Single Phase Clocking (TSPC) D CL V 0.9V +V V 0.9V +V OUTPUT Figure 3: NAND based D Flip Flop
International Journal of Advancements in Research & Technology, Volume 2, Issue5, May-2013 7 It is constructed based on both master and slave latches. In this configuration output of master latch is the input of slave latch and the output of slave is the output of the Flip-Flop. To receive the input data D depending upon the clock signals CL and CLB to use the edge of the circuit shown in Figure 3. 5 PROPOSED TECHNIQUES 5.1 Lector Multi Threshold Stacking Techniques ( MTSTAC) Figure 5: Super Cut off CMOS Stacking It is a combination of lector and super cutoff stacking techniques as shown in Figure 5. During active mode, any one of the LCT is turned on and performs normal operation whereas the LCTS limits the leakage current. In standby mode the stacked transistors which are under driven (or over driven) are turned off. This creates virtual supply/ground rails and cutting off the circuit from supply/ground, causing leakage current reduced by combining of lector and super cutoff stacking. Figure 4: Multi Threshold CMOS Stacking It is a combination of lector and multi threshold stacking techniques as shown in Figure 4. Where the lector technique have leakage control transistor (PMOS and NMOS) if any one of the transistor is always cutoff for whatever input combination is applied. This is increases the resistance path from supply to ground and also reduces the leakage current. The stacked transistor is tuned ON to perform normal operation. If sleep transistor is turned OFF means it creating virtual supply/ground and cutting off the supply. It causing leakage current should be reduced while it maintains high speed in active mode. 5.2 Lector Super Cutoff Stacking Technique (SCSTAC) 6 SIMULATION AND RESULTS Both 9TSPC and NAND based D flip-flop are designed simulated and functionally verified using 16nm CMOS technology files in T-SPICE tool. We have used V th transistors in all designs to show the performance benefits and comparison of different techniques. These techniques are applied to both 9TSPC and NAND-based D flip-flop. Static power for both D flip-flops during active and sleep(idle) mode as well as total (dynamic) power during clocked operation are all measured using T-SPICE tools. Table 1 provides the static power and total power dissipation for 9TSPC. From the power result, it is observed that proposed technique MTSTAC is second most efficient for P AVG. For P STATIC, FTS is the most efficient technique. Where the average power of lector is more leakage when compare to conventional but the static power of lector is efficient than conventional. The proposed techniques are more efficient when compare to lector technique on both average and static power.
International Journal of Advancements in Research & Technology, Volume 2, Issue5, May-2013 8 TABLE 1 COMPARISION TABLE FOR TSPC TABLE 2 COMPARISION TABLE FOR NAND BASED D FLIP-FLOP TECH- NIQUES P AV G (NW) P STATIC DE- LAY PDP (aj) %RE- DUC- TION OF P AVG TECH- NIQUES P AVG P STATIC DELAY PDP (aj) %RE DUC TIO N OF P AVG Conventional 4.29 2.62X1 0-0.82 0.0035 - Conventional 9.15X 5.65X10-10 -9 1.11 0.0010 - MTCMOS 2.40 2.59 X10-1.68 0.0040 44.05 MTCMOS 5.37 5.56X10-1.48 0.0079 41.33 SCCMOS 2.77 2.09 X10-1.27 0.0035 35.43 SCCMOS 4.08 5.50X10-1.22 0.0049 55.40 FTS 3.78 6.13 X10-13 1.2 0.0045 11.88 FTS 9.99 6.13 X10-13 0.84 0.0083 Nil SS 3.06 2.54 0.47 0.0014 28.67 SS 9.82 2.54 X10 - X10 - MTSTAC 2.72 2.70 1.25 0.0034 36.59 MTSTAC 9.23 2.70 X10 - X10 - SCSTAC 3.27 2.44 1.69 0.0055 23.77 SCSTAC 1.04 2.44 X10 - X10-0.84 0.0082 Nil 0.74 0.0068 Nil 0.74 0.0076 Nil 5.30 1.68 X10-1.25 0.0066 Nil 1.17 1.68 X10-1.11 0.0 Nil MTSTAC 2.55 2.27 X10-1.26 0.0032 40.55 MTSTAC 1.08 2.27 X10-1.48 0.015 Nil SCSTAC 3.11 2.46 X10-1.27 0.0039 27.50 SCSTAC 1.05 2.46 X10-1.425 0.014 Table 2 provides information about power dissipation for NAND based D flip-flop. From the power result, it is observed that SCCMOS is efficient for P AVG and for P STATIC, FTS technique is the most efficient. MTSTAC and SCSTAC have low delay. Conventional is efficient for power delay product. MTCMOS only have high percentage to reduces the leakage current all other techniques have less efficient to reduces the leakage current for NAND based D-flip flop. 7 CONCLUSION Thus the studying impact of various leakage current reduction techniques on different D flip-flop architecture is implemented in 16nm technology. The static power is optimized by using various leakages current reduction techniques. It also proposes hybrid power optimization techniques such as MULTITHRESHOLD STACING and SUPER CUTOFF STACING. If this leakage reduction technique is applied to any of the combinational or sequential circuit, some D flip-flop architecture methods are efficient when compared to other method, which can be used for future work.
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