AN EFFICIENT DOUBLE EDGE TRIGGERING FLIP FLOP (MDETFF)

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AN EFFICIENT DOUBLE EDGE TRIGGERING FLIP FLOP (MDETFF) S.Santhoshkumar, L.Saranya 2 (UG Scholar, Dept.of.ECE, Christ the king Engineering college, Tamilnadu, India, santhosh29ece@gmail.com) 2 (Asst. Professor, Dept.of.ECE, Christ the King Engineering College, Tamilnadu, India, saranyalece@yahoo.com) Abstract An efficient double edge triggering flip flop (DETFF) for low-power and high-performance applications is presented in this paper. The aim of the DETFF is to reduce pipeline overhead. In its pulse generator, the four inverters are used to generate the inverted and delayed clock signals. The explicit pulse generator is simple and suitable for Modified double-edge triggering. However, the flip flop latency may be degraded due to the large capacitive loads output nodes. On top of that, MDETFF suffers from high leakage current. This is caused by a high-voltage drop across transistor. when they are off, the pulse generating stage, the sensing stage and the latching stage. The Modified double edge-triggered pulse generatorr produces a brief pulse signal synchronized at the rising and falling clock edges. Therefore, the conditional pre charging technique is applied in the sensing stage of MDETFF, to avoid redundant transitions at major internal nodes. As for output it only needs to be pre charged in the first cycle and remains at its high state for the remaining cycles. Since the pre charging activity is conditionally controlled, the critical pull down path is simplified, consisting of only one signal transistor. This helps to reduce the discharging time significantly. As such, the resulting sensing stage possesses low-power and high-speed feature. IndexTerms- Flip-Flop, High-speed, Leakagee power, Low paper.introduction:- In many digital very large scale integrationn (VLSI) designs, the clock system that includes clock distribution network and flip-flops, is one of the most power consumption components. It accounts for 0% to 60% of the total system power, where 90% of which is consumed by the flip-flops and the last branches of the clock distribution network that is driving the flip-flop [].With the recent trend in frequency scaling and deep pipelining, this clocking system power may be even more pronounced. As the power budget of today s portable digital circuit is severely limited, it is important to reduce the power dissipation in both clock distribution networks and flip- budget at high flops. Moreover, because of the tight timing frequency operation, the latency of the flip-flops should be minimized. Hence, the ability to achieve a design that ensures both power consumption and small latency is essential in modern VLSI technology. The system requirements are also rising up with this continuous advancing process of technology and speed of operation. In synchronous systems, high speed has been achieved using advanced pipelining techniques. In modern deep-pipelined architectures, pushing the speed further up demands a lower pipeline overhead. This overhead is the latency associated with the pipeline elements, such as the flipbeen devoted to flops and latches. Extensive work has improve the performance of the flip-flops in the past few decades[] [2] [] [4]. Hybrid latch flip-flop (HLFF) [] and semi dynamic flip flop (SDFF) [2] are considered as the classic high- architecture that performance flip-flops. They possess a hybrid combines the merits of dynamic and static structures. In addition, SDFF has a distinctive capability of incorporating logic very efficiently, because unlike the true single phase latch (TSPC) in Yuan and Svensson s experiment [], only one transistor is driven by the data input. This greatly helps in reducing the pipeline overhead since the delay and area associated with one or more logic stages preceding the flip- hybrid flip-flop designs have flop can be eliminated. Several been proposed in the past decade, all aiming at reduction of power, delay, and area. Advantage over SDFF and HLFF in both power and speed. It uses a split-dynamic node to reduce the pre charge capacitance, which is one of the most important reasons for the large power consumptionn in most of the conventional designs. But this structure still has some drawbacks, due to redundant power dissipation that results when the data does not switch for more than one clock (CLK) cycles. 2.ANALYSIS ARCHITECTURES :- OF FLIP-FLOP A large number of flip-flops and latches have been published in the past few decades. They can be grouped under the static and dynamic design styles. The category of the flip- includes the modern high flop design, the dynamic flip-flops performance flip-flops [] [2] [] [4]. There are purely dynamic designs as well as Pseudo dynamic structures. The latter, which has an internal pre charge structure and a static output, deserves special attention because of their distinctive performance improvements. They are called the semi-dynamic or hybrid structures, becausee they consist of a dynamic frontend and a static output. HLFF (Fig. ) and SDFF (Fig. 2) fall under this category. They benefit from the CLK overlap to perform the latching operation. SDFF is the fastest classic hybrid structure, but is not efficient as far as power consumption is concerned because of the large CLK load as well as the large pre charge capacitance. HLFF is not the fastest but has a lower power consumption compared to the 9

SDFF. The longer stack of nmos transistors at the output node (Fig. 2) makes it slower than SDFF and causes large hold-time requirement. This large positive hold time requirement makes the integration of HLFF to complex circuits a difficult process. Also it is inefficient in embedding logic. The major sources of power dissipation in the conventional semi-dynamic designs are the redundant data transitions and large pre charge capacitance. Many attempts have been made to reduce the redundant dataa transitions in the flip-flops [] [4]. Fig..HLFF Since there are no added transistorss in the pull-down nmos stack, the speed performance is not greatly affected. But the presence of three stacked nmos transistors at the output node, similar to HLFF, and the presence of conditional structures in the critical path increasee the hold time requirement and D-Q delay of the flip-flop. Also, the additional transistors added for the conditional circuitry make the flip-flop bulky and cause an increase in power dissipation at higher data activities. The large pre charge-capacitance in a wide variety of designs results from the fact that both the output pull-up and the pull-down transistor are driven by this pre charge node. These transistors being driving large output loads contribute to most of the capacitance at this node. Fig.2.SDFF It reduces the power dissipation by splitting the dynamic node into two, each one separately driving the output pull-up and pull-down transistors as shown in Fig. 2. Since only one of the two dynamic nodes is switched during one CLK cycle, the total power consumption is considerably reduced without any degradation in speed. Also XCFF has a comparatively lower CLK driving load. One of the major drawbacks of this design is the redundant pre charge at node X2 and X for data patterns containing more 0 s and s, respectively. In addtion to the large hold time requirement resulting from the conditional shutoff mechanism, a low to high transition in the CLK when the data is held low can cause charge sharing at node X. This can trigger erroneous transition at the output unless the inverter pair INV-2 is carefully skewed. This effect of charge sharing becomes uncontrollably large when complex functions are embedded into the design. If D is zero prior to the overlap period, node X remains high and node X2 is pulled low through NM as the CLK goes high. Thus, node QB is charged high through PM2 and NM4 is held off. At the end of the evaluation phase, as the CLK falls low, node X remains highh and X2 stores the charge dynamically. The architecturee exhibits negative setup time since the short transparency period defined by the overlap CLK of and CLKB allows the data to be sampled even after the rising edge of the CLK before CLKB falls low []. Fig. shows the post-layout timing diagram of the flip- and.2 V supply in 90-nm flop at 2-GHz CLK frequency UMC process technology. Node X undergoes charge sharing when the CLK makes a low to high transition while D is held low. This results in a momentary fall in voltage at node X, but the inverter pair INV-2 is skewed properly such that it has a switching threshold well below the worst case voltage drop at node X due to charge sharing. The timing diagram shows that node X2 retains the charge level during the precharge phase when it is not driven by any transistor. Note that the temporary pull down at node X2 when sampling a one is due to the delay between X and XB. The conditional shutoff mechanism provided in SDFF (Fig. 2) is robust. It is capable of producing smaller sampling window by skewing the inverters and the NAND gate in the conditional shutoff path. Although this method can provide lower hold time requirements, it results in a larger precharge node capacitance and, hence, higher power consumption..ddff:- To analyze the performance of DDFF, other designs were also simulated under similar conditions. Since the D-Q delay reflects the actual portion of the time period consumed by the latching device, we follow the method specified by Stojanovic and Oklobdzija [7] to consider the minimum D-Q delay as the performance metric for speed. Optimum setup-time is the data-to-clk delay when D-Q is at its minimum. As mentioned by Stojanovic and Oklobdzija [7], the power is divided into three parts the latching power, the local CLK driving power, and the local data driving power, to accurately analyze the power-performancee of various designs. The simulations are carried out at various data activities to obtain a realistic performance comparison of various designs. 20

Fig..DDFF The DDFF architecture Node X is pseudo-dynamic, with a weak inverter acting as a keeper, whereas, compared to the XCFF, in the new architecture node X2 is purely dynamic. An unconditional shutoff mechanism is provided at the frontend instead of the conditional one in XCFF. The operation of the flip-flop can be divided into two phases: ) the evaluation phase, when CLK is high, and 2) the pre charge phase, when CLK is low. The actual latching occurs during the overlap of CLK and CLKB during the evaluation phase. If D is high prior to this overlap period, node X is discharged through NM0-2. This switchess the state of the cross coupled inverter pair INV-2 causing node XB to go high and output QB to discharge through NM4. The low level at the node X is retained by the inverter pair INV-2 for the rest of the evaluation phase where no latching occurs. Thus, node X2 is held high throughout the evaluation period by the pmos transistor PM. As the CLK falls low, the circuit enters the precharge phase and node X is pulled high through PM0, switching the state of INV-2. During this period node X2 is not actively driven by any transistor, it stores the charge dynamically. The outputs at node QB and maintain their voltage levels through INV-4. The setup time and hold time of a flip-flop refers to the minimum time period before and after the CLK edge, respectively where the data should be stable so that proper sampling is possible. Here setup time and the hold time depend on the CLK overlap period. If VM is the switching threshold of the inverter pair INV-2 and Tvm is the time required to discharge node X to VM, the hold time required by the flipflop can be expressed as where Tov is the overlap period defined by the low to high transitionn of the CLK and high to low transition of CLKB. It should be greater than Tvm for the proper functioning of the flip-flop Thold and Thold0 represent the hold-time required for sampling a one and a zero, respectively. Also note that Thold and Thold0, respectively are the maximum time period after the CLK transition such that the flip-flop samples a zero and a one, respectively. Since CLKB is high prior to the low to high transition of the CLK, when D is high, the parasitic diffusion capacitors at the drain of NM and NM2 are predischarged, resulting in a low Tvm. Now the overlap period can be chosen such that Thold and Thold0 in () and (2), respectively, are minimized. Tov can be adjusted by setting proper size for the transistors in INV5 as specified in [5]. This leads to a small negative setup time and a positive hold time close to zero. Fig. (a) shows hold time for sampling zero, where D is held low for time-period slightly greater than Tov Tvm after the positive CLK edge. This causes node X to discharge to a voltage greater than VM and INV-2 restores the high levell leading to a proper latching of zero. A similar case for sampling one is shown in Fig. (b). Here, since D is held high for a time-period equal to Tvm, node X properly discharges and one is latched. We measured Tvm to be 8 ps in the pre-layout analysis, where only the frontend of the flipflop was simulated with proper load, and an overlap period of 50 ps was chosen. The pre- at 27 C and.2 V supply layout simulation of the flip-flop voltage measures Thold0 to be 0 ps and Thold to be 5 ps. The slight variation of the results from that of () and (2) is due to the nonzero slopes of CLK and data signals. 4.DDFF-ELM:- Various functions have been embedded into the proposed design to analyze the performance of the structure in terms of power and speed. Since SDFF is considered to be the benchmark of comparison, it was also simulated under similar conditions when embedded with the same functions. SDFF has a fast non inverting output and a slow inverting output, whereas the proposed design has a fast inverting output and a slow non inverting output. In order to have a fair comparison of delay, inverting and non inverting outputs, respectively were considered for SDFF and the proposed design. AND, OR functions and a two-input multiplexer implementing the function A.SELA + B.SELB were embedded into both the designs by replacing the DDFF-ELM performs the function of a flip-flop when no logic is embedded, its performance as a flip-flop is compared with other flip-flops along with DDFF. DDFF-ELM in all the above designs was designed using three inverters for generating sampling window so as to obtain the worst case timing results of the design. In order to depict the advantages of embedding logic in to the flip-flop, the combinations of static logic and flip-flop, performing the same functions, were also designed. The performance of this discrete combination is also provided and compared with the embedded functions. Fig.4.DDFF-ELM In order to magnify the performance improvement of the embedded logic element, a 4-b Johnson up-down counter with asynchronous reset (Fig.4(a) ) has been designed. The counter is designed with a set of 2-input multiplexers and flip- the discrete combination of flops. In the embedded structure, multiplexer and flip-flop is replaced by a multiplexer embedded flip-flop. The ELM and the SDFF with embedded logic were incorporated with asynchronous-reset (rst_n) functionality as explained in Section IV. 2

approach is to increase the clock frequency. However, using high clock frequency has many disadvantages. Power consumption of the clock system increases dramatically and clock uncertainties take significant part of the clock cycle at high frequencies. Moreover the non-ideal clock distribution results in degradation of the clock waveform, power supply noise and cross-talk. About 0%-70% of the total power in the system is dissipated due to clocking network, and the Flip-Flops []. An Fig.4(a). 4-b Johnson up-down counter. alternative clocking approach is based on the use of storage elements which are capable of capturing data on both rising and falling edges of the clock. Such storage elements are termed as Dual-Edge Triggered Flip-Flops (DETFFs). The conventional DETFF circuits and a new proposed architecture of DETFF. the nominal simulation conditions, along with analysis and optimization performed, during simulation. The performance results for proposed design. These results are compared with conventional designs in terms of delay, power, PDP and area and ends with conclusion. ELM:- Fig.4(b). Simulation test bench. As mentioned earlier, the major advantage of the SDFF is the capability to incorporate complex logic functions efficiently. The efficiency in terms of speed and area comes from the fact that an N-input function can be realized in a positive edge triggered structure using a pull-down network (PDN) consisting of N transistors as shown in Fig. 9(a). Compared to the discrete combination of N a static gate and a flip-flop, this embedded structure offers a very fast and small implementation. Although SDFF is capable of offering efficiency in terms of speed and area, it is not a good solution as far as power consumption is concerned. Not too many attempts have been made to design a flip-flop, which can incorporate logic efficiently in terms of power, speed and area. The double-pulsed set-conditional-reset flip-flop (DPSCRFF) [5] is one of the flip-flops capable of incorporating logic. But this structure has an explicit pulse generator to generate two pulses from the global CLK, which can cause large power consumption even when there is no data transition. Also, the three inverter delay between the two pulses, p and p2 [5], causes a direct path between supply rails and a large glitch at the output when the data input remains high for more than one CLK cycle. In addition, the highly asymmetric timing nature of the design and the large hold time requirements prevent it from being directly cascaded without the use of additional buffers. Another flip-flop design aiming at efficient logic embedding is presented in [6] and [7]. But the overlap based logic cell introduced in [7] is similar to the single-phase pulsed flip-flop mentioned in [2]. Since SDFF is proved [2] to outperform this design, we consider SDFFF with emb edded logic for comparative purposes. 5.PROPOSED MDETFF:- Flip-Flops are important timing elements in digital circuits which have a great impact on circuit power consumption and speed. The performance of the Flip-Flop is an important element to determine the performance of the whole synchronous circuit, particularly in deeper pipelined design. For improving the performancee one innovating Modified Double-Edge Triggered Flip-Flop:- In some of the designs DETFF approach is preferred to reduce power dissipation. The data is captured by both edges of the clock. Both positive and negative edges are used to sample the D input at alternate clock edges, and the appropriate sample is selected for the Q output. Fig.5.Proposed MDETFF All simulations are performed on TANNER circuit simulator models at 80nm technology node. Flip-Flops designs can be compared at different parameters like delay, average power dissipation, power delay product (PDP) etc. Generally, for portable systems in which the battery life is of the primary concern PDP-based comparison is appropriate [8]. However, there is always a trade off between propagation delay and power dissipation of a circuit. If we optimize a circuit for power its delay increases and vice-versa. We designed the circuit to achieve minimum power-delay product (PDP). In addition to this delay, power consumption and area of the Flip-Flop designs are also compared. How to sample and store the input data at both clock levels? We consider two related problems. The first problem is to restructure the flip-flop so as to sample and store the input data at both of edge. The second problem is to use the traditional single-edge-triggered (SET) flip-flop (for example, sensitive to clock s falling edge) to compose a new storage 22

system, which can sample the input data on the clock s rising edge as well as its falling edge. 6.SIMULATION RESULTS The proposed DETFF is designed and compared with several conventional Flip-Flops. Each Flip-Flofor power delay product. The proposed DETFF is having is optimized lesser number of clocked transistors than the other discussed DET FFs. Simulation results for power, delay, PDP and area at nominal conditions for the Flip-Flops are summarized in Table. SIMULATION OUTPUT:- 2002. ISCAS 2002. IEEE International Symposium on, vol.5, no., pp.v-05,v-08 vol.5, 2002. [2]Phyu, M.-W.; Goh, W.L.; Yeo, K.-S., "A low-power static dual edge-triggered flip-flopp using an output-controlled discharge configuration," Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, vol., no., pp.2429,242 Vol., 2-26 May 2005. []M. AFGHAHI AND J. YUAN, DOUBLE EDGE-TRIGGERED D- FLIP-FLOPS FOR HIGHSPEED CIRCUITS, IEEE J. SOLID-STATE CIRCUITS, VOL.26, NO.8, PP.68-70, AUG. 99. Fig.6.Waveform RESULT COMPARISON:- Table.. FLIP FLOP MIN POW ER(m illi.w) HLFF.84 SDFF.848 6 DDFF 5.2 5 DDFF- 0.04 ELM 2 MDET 4.2 FF 5 MAX POWE R(w) AVG POW ER(w ) 0.0 0.04 6 0.89.755 0.0776 7.482 8 0. 6.98 0 0.767.752 PDP( milli. w/s) 7.482 5 2.255.046 4.627 0.86 ARE A(um ^2) 880 02 792 968 528 7.CONCLUSION:- In this paper, we proposed a low power, small area MDETFF design which is static & dynamic in nature. The proposed MDETFF has lesser number of clocked transistors with respect to other DETFF. The post layout experimental simulation results shows that proposed MDETFF offers improvement in power dissipation, PDP and area. Therefore the proposed MDETFF is very well suited for low power and small area applications. REFERENCES:- [] Nedovic, Nikola; Aleksic, M.; Oklobdzija, V.G., "Comparative analysis of double-edge versus single-edge triggered clocked storage elements," Circuits and Systems, 2