More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98

More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98

Review: Bit Storage SR latch S (set) Q R (reset) Level-sensitive SR latch S S1 C R R1 Q D C S R D latch Q D Clk D latch D m Q m C m first D flip-flop D latch D s C s Q s Q s second Q Q Feature: S=1 sets Q to 1, R=1 resets Q to 0. S=R=0, Q=Q prev Problem: SR=11, Q=Q =0 Feature: S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden. Feature: SR can t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Feature: Only loads D value present at rising clock edge, so values can t propagate to other flip-flops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR but gate count is less of an issue today. 99

More FF implementations We can implement a J-K FF by using a D FF (see homework problem) We can implement a D FF by using two D Latches and an inverter. D C S R D latch Q D Clk D latch D m Q m C m first D flip-flop D latch D s Q s C s Q s second Q Q 100

Recall: Flip-Flop vs. Latches: Edge-triggered An edge-triggered flip-flop changes values at the clock edge (transition): responds to its input at a well-defined moment (at the clock-transition) ignores the pulse while it is at a constant level Negative edge-triggered Positive edge-triggered Clock ignored In 101

How to detect an edge? Edge detector circuits used in edge-triggered flip-flops (a) PGT (positive going transition); (b) NGT. The duration of the * pulses is typically 2 5 ns.

Using edge-detector to implement J-K Flip-Flop Recall: When J and K are both HIGH, output is toggled to the opposite state. May be positive going or negative going clock trigger.

Positive edge triggered JK FF

Negative edge triggered JK FF

Example Wave Form: A J-K FF that responds to a NGT on its clock input and has active-low asynchronous inputs. Also look at the PRE and CLR of SN74HC74 D-FF, http://eng.umb.edu/~hzhang/e241/datasheets/dff%20-%20sn74hc74.pdf

Recall: SR Latch NOR and NAND implementations S (set) SR latch Q R (reset) Q S=0, R=0, then Q=Q prev S_bar=1, R_bar=1, then Q=Q prev Active low v.s. active high. They can be used for both implementations. Reset can also be called CLEAR. 107

J-K Flip-Flop by edge detector Internal Circuitry Recall: S_bar=1, R_bar=1, then Q=Q prev E.g., when J=1, K=0. Case 1: Q=1 Case 2: Q=0

More on D Flip-Flop - Implementation An edge-triggered D flip-flop can be implemented by adding a single INVERTER to the edge-triggered J-K flipflop.

More Flip-Flop Applications Examples of applications: Storing binary data Counting Transferring binary data between locations Many FF applications are categorized sequential. Output follows a predetermined sequence of states.

Flip-Flop Synchronization Most systems are primarily synchronous in operation in that changes depend on the clock. Asynchronous and synchronous operations are often combined frequently through human input. The random nature of asynchronous inputs can result in unpredictable results. The asynchronous signal A can produce partial pulses at X. Suppose we turn on switch to let clock signal to pass through AND gate

An edge-triggered D flip-flop synchronizes the enabling of the AND gate to the NGTs of the clock. Flip-Flop Synchronization

Detecting an Input Sequence FFs provide features pure combinational logic gates do not in many situations, output activates only when inputs activate in a certain sequence This requires the storage characteristic of FFs. D flip-flop responds to a particular sequence of inputs. E.g., we want to make sure A should be high first before B signal passes through. To work properly, A must go HIGH, prior to B, by at least an amount of time equal to FF setup time.

Data Storage and Transfer FFs are commonly used for storage and transfer of binary data. Groups used for storage are registers. Data transfers take place when data is moved between registers or FFs. Synchronous transfers take place at clock PGT/NGT. Asynchronous transfers are controlled by PRE (or PRE_bar) & CLR (or CLR_bar).

Data Storage and Transfer Synchronous inputs are used to perform the transfer.

Data Storage and Transfer Asynchronous Asynchronous data transfer operation. PRE_bar and CLR_bar inputs are used to perform the transfer. If transfer enable is low, PRE_bar and CLR_bar are high, output of the second JK FF responds to its JK inputs normally. If transfer enable is high, either PRE_bar or CLR_bar is low (the other is high) depending on A and A. Assume A=1, then B is immediately set to 1, which means we asynchronously transfer bit A to bit B.

Data Storage and Transfer Parallel Transferring the bits of a register simultaneously is a parallel transfer.

Serial Data Transfer Shift Register A shift register is a group of FFs arranged so the binary numbers stored in the FFs are shifted from one FF to the next, for every clock pulse. J-K flip-flops operated as a four-bit shift register. Transfer the bits of a register a bit at a time is a serial transfer.

Serial Data Transfer Shift Register Input data are shifted left to right from FF to FF as shift pulses are applied. J-K flip-flops operated as a fourbit shift register. 101 are shifted

Serial Data Transfer Shift Register Two connected three-bit shift registers. The contents of the X register will be serially transferred (shifted) into register Y. The D flip-flops in each shift register require fewer connections than J-K flip-flops.

Serial Data Transfer Shift Register Two connected three-bit shift registers. The complete transfer of the three bits of data requires three shift pulses.

Serial Data Transfer Shift Register Two connected three-bit shift registers. On each pulse NGT, each FF takes on the value stored in the FF on its left prior to the pulse.

Serial Data Transfer Shift Register Two connected three-bit shift registers. On each pulse NGT, each FF takes on the value stored in the FF on its left prior to the pulse.

Serial Data Transfer Shift Register Two connected three-bit shift registers. On each pulse NGT, each FF takes on the value stored in the FF on its left prior to the pulse.

Serial Data Transfer Shift Register Two connected three-bit shift registers. After three pulses: The 1 initially in X2 is in Y2. The 0 initially in X1 is in Y1. The 1 initially in X0 is in Y0. The 101 stored in the X register has now been shifted into the Y register. The X register has lost its original data, and is at 000.

Serial Data Transfer vs. Parallel FFs can easily be connected so that information shifts from right to left. No general advantage of one direction over another. Often dictated by the nature of the application. Parallel transfer requires more interconnections between sending & receiving registers than serial. More critical when a greater number of bits of are being transferred. Often, a combination of types is used Taking advantage of parallel transfer speed and serial transfer the economy and simplicity of serial transfer.

Timing Flip-flop samples D at clock edge D must be stable when sampled Similar to a photograph, D must be stable around clock edge Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <127> 127

Output Timing Constraints Propagation delay: t pcq = longest time delay (after clock edge) that the output Q will become stable (i.e., to stop changing) Contamination delay: t ccq = time delay (after clock edge) that Q might start to change Q t ccq t pcq They represent the fastest and slowest delays through the circuit. Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <128> 128

Input Timing Constraints Setup time: t setup = time before clock edge data must be stable (i.e. not changing) Hold time: t hold = time after clock edge data must be stable Aperture time: t a = time around clock edge data must be stable (t a = t setup + t hold ) D t setup t hold in Digital order Design for the and circuit Computer to Architecture: sample its ARM input Edition at a clock 2015edge correctly. Chapter 3 <129> t a Aperture time is the total time interval during which the circuit has to be stable 129

Dynamic Discipline Synchronous sequential circuit inputs must be stable during aperture (setup and hold) time around clock edge Specifically, inputs must be stable at least t setup before the clock edge at least until t hold after the clock edge We are only concerned about the final values of the inputs at the time they are sampled, so we can treat signals as discrete in time. Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <130> 130

Dynamic Discipline The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements (a) Q1 D2 (b) R1 Q1 C L T c D2 R2 Here we focus on the generic path in the figure. T C is clock period or cycle time. We try to find the timing constraints for R2, in terms of setup time and hold time, the timing characteristics of registers and the combinational logic. Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <131> 131

Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2, in terms of change of the output of R1 which becomes of the input of R2. The input to register R2 must be stable at least t setup before next clock edge Q1 C L D2 T c R1 R2 T c Q1 D2 t pcq t pd t setup Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <132> 132

Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2, in terms of change of the output of R1 which becomes of the input of R2. The input to register R2 must be stable at least t setup before next clock edge Q1 C L D2 T c t pcq + t pd + t setup R1 R2 T c Q1 D2 t pcq t pd t setup Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <133> 133

Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2 The input to register R2 must be stable at least t setup before next clock edge R1 Q1 C L D2 R2 T c t pcq + t pd + t setup t pd T c (t pcq + t setup ) T c Setup time or max-delay constraint Q1 D2 t pcq t pd t setup Digital Design and Computer Architecture: ARM Edition 2015 (t pcq + t setup ): sequencing overhead, it reduces the time interval t pd for Chapter 3 <134> useful computation. 134

Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge Q1 D2 R1 Q1 C L D2 R2 t hold < t ccq t cd t hold Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <135> 135

Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge Q1 C L D2 R1 Q1 D2 R2 t hold < t ccq + t cd t ccq t cd t hold Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <136> 136

Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge Q1 C L D2 Q1 R1 R2 t hold < t ccq + t cd t cd > t hold - t ccq D2 t ccq t cd hold time or min-delay constraint t hold Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <137> 137

Consider an extreme case t hold < t ccq A reliable flip-flop must have a hold time shorter than its contamination delay. Usually t hold is zero, so we ignore it usually. Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <138> 138

T c t pcq + t pd + t setup t pd T c (t pcq + t setup ) t hold < t ccq + t cd t cd > t hold - t ccq Sequential circuits setup time and hold time constraints specifies the max (t pd ) and min (t cd ) delays of the combinational logic between flipflops. Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <139> 139

Timing Analysis Example 1ps= 10^(-12)s A B Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps C D X' Y' X Y per gate t pd t cd = 35 ps = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: T c? Hold time constraint: t ccq + t cd > t hold? Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <140> 140

Timing Analysis Example 1ps= 10^(-12)s A B Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps C D X' Y' X Y per gate t pd t cd = 35 ps = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: T c (50 + 105 + 60) ps = 215 ps f c = 1/T c = 4.65 GHz Hold time constraint: t ccq + t cd > t hold? (30 + 25) ps > 70 ps? No! Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <141> 141

Timing Analysis Example Add buffers to the short paths: A B Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps C D X' Y' X Y per gate t pd t cd = 35 ps = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: T c? Hold time constraint: t ccq + t cd > t hold? Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <142> 142

Timing Analysis Example Add buffers to the short paths: A B Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps C D X' Y' X Y per gate t pd t cd = 35 ps = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: T c (50 + 105 + 60) ps = 215 ps f c = 1/T c = 4.65 GHz Hold time constraint: t ccq + t cd > t hold? (30 + 50) ps > 70 ps? Yes! Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <143> 143

Clock Skew The clock doesn t arrive at all registers at same time Skew: difference between two clock edges Perform worst case analysis to guarantee dynamic discipline is not violated for any register many registers in a system! delay Skew reasons: Wires of different lengths. Noise in wires. Clock gating. 1 2 1 R1 t skew Digital Design and Computer Architecture: ARM Edition 2015 Q1 C L D2 R2 2 Chapter 3 <144> 144

Setup Time Constraint with Skew In the worst case, 2 is earlier than 1 1 R1 Q1 C L T c D2 2 R2 1 2 T c? Q1 D2 t pcq t pd t setup t skew R1 receives the latest skewed clock and R2 receives the earliest Digital skewed Design and clock. Computer Architecture: ARM Edition 2015 Chapter 3 <145> 145

Setup Time Constraint with Skew In the worst case, 2 is earlier than 1 1 R1 Q1 C L T c D2 2 R2 1 2 T c t pcq + t pd + t setup + t skew Q1 D2 t pcq t pd t setup t skew Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <146> 146

Setup Time Constraint with Skew In the worst case, 2 is earlier than 1 1 R1 Q1 C L T c D2 2 R2 1 2 Q1 T c t pcq + t pd + t setup + t skew t pd T c (t pcq + t setup + t skew ) D2 t pcq t pd t setup t skew Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <147> 147

Hold Time Constraint with Skew In the worst case, 2 is later than 1 1 2 Q1 C D2 L R1 R2 1 2 Q1 D2 t ccq t cd t skew t hold R1 receives the earliest skewed clock and R2 receives the latest Digital skewed Design and clock. Computer Architecture: ARM Edition 2015 Chapter 3 <148> 148

Hold Time Constraint with Skew In the worst case, 2 is later than 1 1 2 Q1 C D2 L R1 R2 1 2 Q1 t ccq + t cd > t hold + t skew D2 t ccq t cd t skew t hold Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <149> 149

Hold Time Constraint with Skew In the worst case, 2 is later than 1 1 2 Q1 C D2 L R1 R2 1 2 Q1 D2 t ccq + t cd > t hold + t skew t cd > t hold + t skew t ccq t ccq t cd t skew t hold In summary, clock skew effectively increases both the setup time and hold time, It adds to the sequencing overhead. and reduces useful time of comb. Logic. It increases required minimum delay thru comb logic. Even if t hold =0, two back-toback flip-flops Digital Design will and have Computer hold time Architecture: failure ARM if t ccq Edition <t skew 2015 Chapter 3 <150> 150

Example problem Timing Characteristics t ccq = 50 ps t pcq = 70 ps t setup = 60 ps t hold = 20 ps Each XOR gate t pd = 100 ps = 55 ps t cd If no clock skew, what is the max operating frequency of the circuit? How much clock skew can the circuit tolerate if it must operate at 2 GHz? How much clock skew can the circuit tolerate before it might experience a hold time violation? 151