4- Inputs Outputs ombinational circuit Next state Storage elements Present state Fig. 4- Block Diagram of a Sequential ircuit 2 Prentice Hall, Inc.
4-2 (a) t pd (b) t pd 2 t pd (d) 2 t pd (c) t pd Fig. 4-2 Logic Structures for Storing Information 2 Prentice Hall, Inc.
4-3 Inputs ombinational circuit Flip-flops Outputs lock pulses (a) Block diagram (b) Timing diagram of clock pulses Fig. 4-3 Synchronous locked Sequential ircuit 2 Prentice Hall, Inc.
4-4 R (Reset) S R Set state S (Set) Reset state Undefined (a) Logic diagram Fig. 4-4 SR Latch with NOR Gates (b) Function table 2 Prentice Hall, Inc.
4-5. ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns i i o o S R _B s s s Fig. 4-5 Logic Simulation of SR Latch Behavior 2 Prentice Hall, Inc.
4-6 S (Set) S R Set state R (Reset) Reset state Undefined (a) Logic diagram (b) Function table Fig. 4-6 SR Latch with NND Gates 2 Prentice Hall, Inc.
4-7 S S R Next state of No change No change = ; Reset state R = ; Set state Undefined (a) Logic diagram Fig. 4-7 SR Latch with ontrol Input (b) Function table 2 Prentice Hall, Inc.
4-8 D S R (a) Logic diagram D Next state of No change = ; Reset state = ; Set state (b) Function table Fig. 4-8 D Latch 2 Prentice Hall, Inc.
4-9 D TG TG Fig. 4-9 D Latch with Transmission Gates 2 Prentice Hall, Inc.
4- S S Y S R R Y R Fig. 4- SR Master-Slave Flip-Flop 2 Prentice Hall, Inc.
4-. 5ns ns 5ns 2ns i is ir oy o s s s Fig. 4- Logic Simulation of a Master-Slave Flip-Flop 2 Prentice Hall, Inc.
4-2 J K S R S R (a) J K (b) Next State of Fig. 4-2 Master-Slave JK Flip-Flop 2 Prentice Hall, Inc.
4-3 D D S R Fig. 4-3 D-Type Positive Edge-Triggered Flip-Flop 2 Prentice Hall, Inc.
4-4 J K D S R Fig. 4-4 Positive Edge-Triggered JK Flip-Flop 2 Prentice Hall, Inc.
4-5 S S D D R R SR SR D with ontrol D with ontrol (a) Latches S R S R J K J K Triggered SR Triggered SR Triggered JK Triggered JK (b) Master-Slave Flip-Flops D D J K J K Triggered D Triggered D Triggered JK Triggered JK (c) Edge-Triggered Flip-Flops Fig. 4-5 Standard Graphic Symbols for Latch and Flip-Flops 2 Prentice Hall, Inc.
4-6 TBLE 4- Flip-Flop haracteristic Tables (a) JK Flip-Flop (b) SR Flip-Flop J K (t ) Operation S R (t ) Operation (t) No change (t) No change Reset Reset Set Set t () omplement? Undefined (c) D Flip-Flop (d) T Flip-Flop D (t ) Operation T (t ) Operation Reset (t) No change Set t () omplement Table 4- Flip-Flop haracteristic Tables 2 Prentice Hall, Inc.
4-7 S J K R (a) Graphic symbols S R J K (b) Function table Undefined No change omplement Fig. 4-6 JK Flip-Flop with Direct Set and Reset 2 Prentice Hall, Inc.
4-8 B Y J K lock Fig. 4-7 Implementing Input Equations 2 Prentice Hall, Inc.
4-9 D D B B lock Y Fig. 4-8 Example of a Sequential ircuit 2 Prentice Hall, Inc.
2 Prentice Hall, Inc. 4-2 TBLE 4-2 State Table for ircuit of Figure 4-8 Present State Input Next State Output B B Y Table 4-2 State Table for ircuit of Figure 4-8
4-2 TBLE 4-3 Two-Dimensional State Table for the ircuit in Figure 4-8 Present state Next state Output B B B Y Y Table 4-3 Two-Dimensional State Table for the ircuit in Figure 4-8 2 Prentice Hall, Inc.
2 Prentice Hall, Inc. 4-22 (b) State table Z Output Next state Inputs Y Present state lock D Z Y (a) Fig. 4-9 Logic Diagram and State Table for D Y =
2 Prentice Hall, Inc. 4-23 TBLE 4-4 State Table for ircuit with JK Flip-Flops Present state Input Next state Flip-flop inputs B B J K J B K B Table 4-4 State Table for ircuit with JK Flip-Flops
4-24 / / / / / /, / / (a), / / (b),, Fig. 4-2 State Diagrams 2 Prentice Hall, Inc.
4-25 / B / B / (a) (b) / B / / / D (c) / / / B / / D / / (d) / Fig. 4-2 onstruction of a State Diagram 2 Prentice Hall, Inc.
4-26 TBLE 4-5 State Table for State Diagram in Figure 4-2 Present State Next State Output Z B D D B B Table 4-5 State Table for State Diagram in Figure 4-2 2 Prentice Hall, Inc.
2 Prentice Hall, Inc. 4-27 TBLE 4-6 Sequence Tables for ode onverter Example Sequences in Order of Digits Represented Sequences in Order of ommon Prefixes BD Input Excess-3 Output BD Input Excess-3 Output 2 3 4 2 3 4 2 3 4 2 3 4 Table 4-6 Sequence Tables for ode onverter Example
4-28 Init Init / / / / B= B= B= B= (a) / / / or / B2= B2= B2= (b) Init Init / / / or / / / / or / / or / B= / / B= / or / / or / B= / / B= / or / B2= B2= B2= B2= B2= B2= / or / / / / / B3= B3= B3= B3= (c) Fig. 4-22 onstruction of a State Diagram 2 Prentice Hall, Inc. (d)
4-29 TBLE 4-7 Table 4-5 with Names Replaced by Binary odes Next State Output Z Present State Table 4-7 Table 4-5 with Names Replaced by Binary odes 2 Prentice Hall, Inc.
2 Prentice Hall, Inc. 4-3 TBLE 4-8 State Table for Design Example Present State Input Next State Output B B Y Table 4-8 State Table for Design Example
4-3 / / / / / / / / Fig. 4-23 State Diagram for Design Example 2 Prentice Hall, Inc.
4-32 B B B B B B D = B + B D B = + B + B Fig. 4-24 Maps for Input Equations and Output Y Y = B 2 Prentice Hall, Inc.
4-33 D D B B lock Fig. 4-25 Logic Diagram for Sequential ircuit with D Flip-Flops Y 2 Prentice Hall, Inc.
2 Prentice Hall, Inc. 4-34 TBLE 4-9 State Table for Second Design Example Present State Input Next State B B Table 4-9 State Table for Second Design Example
4-35 B B D = + B + B D B = + B D = Fig. 4-26 Maps for Simplifying Input Equations 2 Prentice Hall, Inc.
2 Prentice Hall, Inc. 4-36 TBLE 4- Flip-Flop Excitation Tables (a) JK Flip-Flop (b) SR Flip-Flop (t ) (t ) J K (t) (t ) S R (c) D Flip-Flop (d) T Flip-Flop (t) (t ) D (t) (t ) T Table 4- Flip-Flop Excitation Tables
2 Prentice Hall, Inc. 4-37 TBLE 4- State Table with JK Flip-Flop Inputs Present State Input Next State Flip-Flop Inputs B B J K J B K B Table 4- State Table with JK Flip-Flop Inputs
4-38 B B B B J = B K = B B B B B J B = K B = + = Fig. 4-27 Maps for J and K Input Equations 2 Prentice Hall, Inc.
4-39 Y ND2 INV ND2 FJK ND2 FJK INV B NOR2 LK R Fig. 4-28 Logic Diagram for Sequential ircuit with JK Flip-Flops 2 Prentice Hall, Inc.
4-4 R: : : * * B: * * Y: * * * These responses are asynchronous with the clock and thus do not w ait for the next positive clock edge. (a) ircuit test and expected results. 2ns 4ns 6ns 8ns ns 2ns 4ns 6ns 8ns 2ns 22ns 24ns 26ns 28ns ilk ir i o o B o Y s s s (b) Simulation results Fig. 4-29 Logic Simulation Verification for the ircuit in Figure 4-28 2 Prentice Hall, Inc.
4-4 -- Positive Edge-Triggered D Flip-Flop with Reset: -- VHDL Process Description library ieee; use ieee.std_logic_64.all; entity dff is port(lk, RESET, D : in std_logic; : out std_logic); end dff; architecture pet_pr of dff is -- Implements positive edge-triggered bit state storage -- with asynchronous reset. begin process (LK, RESET) begin if (RESET = '') then <= ''; elsif (LK'event and LK = '') then <= D; end if; end if; end process; end; Fig. 4-3 VHDL Process Description of Positive Edge-Triggered Flip-Flop with Reset 2 Prentice Hall, Inc.
4-42 -- Sequence Recognize r: VHDL Process Description -- (See Figure 4-2 f or state diagram) library ieee; use ieee.std_logic_ 64.all; entity seq_rec is port(lk, RESET, : in std_logic; Z: out std_logic); end seq_rec; architecture process_3 of seq_rec is type state_type is (, B,, D); signal state, next_state : state_t ype; begin -- Process - state_ register: implements positive edge-triggered -- state storage with asynchronous reset. state_register: process (LK, RESET) begin if (RESET = '') then state <= ; elsif (LK event and LK = '') then state <= n ext_state; end if; end if; end process; -- Process 2 - next_s tate_function: implements next state as -- a function of inpu t and state. next_state_func: process (, state) begin case state is when => if = '' then next_state <= B ; else next_state <= ; end if; when B => if = '' then next_state <= ; else next_state <= ; end if; Fig. 4-3 VHDL Process Description of a Sequence Recognizer 2 Prentice Hall, Inc.
4-43 -- Sequence Recognizer: VHDL Process Description (continued) when => if = '' then next_state <= ; else next_state <= D; end if; when D => if = '' then next_state <= B; else next_state <= ; end if; end case; end process; -- Process 3 - output_function: implements output as function -- of input and state. output_func: process (, state) begin case state is when => Z <= ''; when B => Z <= ''; when => Z <= ''; when D => if = '' then Z <= ''; else Z <= ''; end if; end case; end process; end; Fig. 4-32 VHDL Process Description of a Sequence Recognizer (continued) 2 Prentice Hall, Inc.
4-44 TBLE 4-2 Illustration of generation of storage in VHDL Inputs RESET = LK = LK event ction FLSE FLSE FLSE Unspecified FLSE FLSE TRUE Unspecified FLSE TRUE FLSE Unspecified FLSE TRUE TRUE <= D TRUE <= '' Table 4-2 Illustration of generation of storage in VHDL 2 Prentice Hall, Inc.
4-45 // Positive Edge-Triggered D Flip-Flop with Reset: // Verilog Process Description module dff_v(lk, RESET, D, ); input LK, RESET, D; output ; reg ; always @(posedge LK or posedge RESET) begin if (RESET) <= ; else <= D; end endmodule Fig. 4-33 Verilog Process Description of Positive Edge-Triggered Flip-Flop with Reset 2 Prentice Hall, Inc.
4-46 // Sequence Recognizer: Verilog Process Description // (See Figure 4-2 f or state diagram) module seq_rec_v(lk, RESET,, Z); input LK, RESET, ; output Z; reg [:] state, next_state; parameter = 2'b, B = 2'b, = 2 'b, D = 2'b; reg Z; // state register: im plements positive edge-triggered // state storage with asynchronous reset. always @(posedge LK or posedge RESET) begin if (RESET == ) state <= ; else state <= next_state; end // next state functio n: implements next state as funct ion // of and state always @( or state) begin case (state) : if ( == ) next_state <= B; else next_state <= ; B: if() next_state <= ;else next_state <= ; : if() next_state <= ;else next_state <= D; D: if() next_state <= B;else next_state <= ; endcase end // output function: i mplements output as function // of and state always @( or state) begin case (state) : Z <= ; B: Z <= ; : Z <= ; D: Z <=? : ; endcase end endmodule Fig. 4-34 Verilog Process of a Sequence Recognizer 2 Prentice Hall, Inc.
4-47 TBLE 4-3 Illustration of generation of storage in Verilog Inputs ction posegdge RESET and RESET = posedge LK FLSE FLSE Unspecified FLSE TRUE <= D TRUE FLSE <= TRUE TRUE <= Table 4-3 Illustration of generation of storage in Verilog 2 Prentice Hall, Inc.