Chapter 5 Synchronous Sequential Circuits
Logic Circuits- Review Logic Circuits 2 Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs an operation that can be specified by a set of Boolean functions. Sequential Circuits Employ storage elements in addition to logic gates. Outputs are a function of the inputs and the state of the storage elements. Output depend on present value of input + past input.
Overview 3 Storage Elements and Analysis Introduction to sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Sequential circuit analysis State tables State diagrams
Introduction to Sequential Circuits A Sequential circuit contains: Storage elements: Latches or Flip-Flops Combinatorial Logic: Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. 4 Inputs Storage Elements State Combinational Logic Next State Outputs
5 Introduction to Sequential Circuits Inputs Storage Elements Combinational Logic Outputs State Next State Sequential Logic Output function Outputs = g(inputs, State) Next state function Next State = f(inputs, State)
Types of Sequential Circuits Depends on the times at which: storage elements observe their inputs, and storage elements change their state Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) Asynchronous Behavior defined from knowledge of inputs at any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! 6
5.3 Storage Elements :Latches Storage elements Maintain a binary state ( or ) indefinitely as long as power is delivered to the circuit Switch states ( or ) when directed by an input signal Most basic storage element Used mainly to construct Flip-Flops Asynchronous storage circuit Types of latches: SR Latches S`R` Latches D Latches 7 X = X
Basic (NOR) S R Latch Cross-coupling two NOR gates gives the S R Latch: 8 Graphic Symbol S Q R (reset) Q R Q S (set) Q
9 Basic (NOR) S R Q t+ S R Latch Q t+ =Q No change Reset to Set to undefined S R Q Q t+ Q t+ Q t+ =Q = Undefined undefined
Basic (NAND) Ś Ŕ Latch Cross-Coupling two NAND gates gives the Ś -Ŕ Latch: Graphic Symbol S Q S (set) Q R Q R (reset) Q
Basic (NAND) Ś Ŕ Latch Q t+ Q t+ Q R S???? Q t+ R S Undefined Reset to Set to Q t+ =Q No change
Clocked S - R Latch Adding two NAND gates to the basic Ś - Ŕ NAND latch gives the clocked S R latch: Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high. C means control or clock. S C R S` R` Q Q 2
D Latch(Transparent Latch) Adding an inverter to the S-R Latch, gives the D Latch: Note that there are no indeterminate states! 3 The graphic symbol for a D Latch is: D Q D Q C Q C Q
4 D Latch(Transparent Latch) D Q t+ Q D Q(t+)
Chapter 5: Sequential Circuits 5.4: Flip-Flops 5
6 Flip-Flops The latch timing problem Master-slave flip-flop Edge-triggered flip-flop Other flip-flops - JK flip-flop - T flip-flop
The Latch Timing Problem In a sequential circuit, paths may exist through combinational logic: From one storage element to another From a storage element back to the same storage element The combinational logic between a latch output and a latch input may be as simple as an interconnect For a clocked D-latch, the output Q depends on the input D whenever the clock input C has value 7
The Latch Timing Problem 8 (continued) Consider the following circuit: D Q Y Suppose that initially Y =. Clock C Q Clock Y As long as C =, the value of Y continues to change! The changes are based on the delay present on the loop through the connection from Y back to Y. This behavior is clearly unacceptable. Desired behavior: Y changes only once per clock pulse
9 The Latch Timing Problem (continued) A solution to the latch timing problem is to break the closed path from Y to Y within the storage element The commonly-used, path-breaking solutions replace the clocked D-latch with: a master-slave flip-flop an edge-triggered flip-flop
2 Master-Slave Flip-Flop Master Slave D C D C Y D C Q Q Consists of two clocked D latches in series with the clock on the second latch inverted What happened when c=? The data from D input is transferred to the master. The slave is disabled. Any change in the input change the master output ( Y ) but can t effect the slave output.
2 What happened when C=? The master is disabled. The slave is enable. The value of ( Y ) is transferred to the slave as input. The output ( Q ) is equal ( Y ). Conclusion: The output of the F.F. can change only during the transition of clock from to or at Trigger. D C D C Master Y D C Slave Q Q
Timing 22
Timing A trigger: The state of a latch or flip-flop is switched by a change of the control input. 23
24 Graphic Symbols
25 Graphic Symbols
26 Other flip-flops Other F-Fs can be built using D F-F There are four operation on a F-F - set to - Reset to - toggle ( complement ) of Q - nothing There are tow F-F - JK F-F - T F-F
JK Flip-Flops 27
28 JK Flip-Flops D = JQ + K Q J K Q t+ No change Q t+ = Q Reset to Set to Complement Q t+= Q
T Flip-Flops 29 T Flip-Flops
T Flip-Flops 3
Characteristic Table 3
Characteristic Table 32
Characteristic Equations 33
34
State Equation 35
State Equation 36
37
38
39 Analysis This circuit consist of : 2 D F-F A and B Input x Output Y Q t+ = D A= D A B = D B
4
4
State Table 42
43
State Diagram 44
45 Input / output state
46
47
Analysis 48 D F-F ( A ) 2 Input X, Y Q t+ = D D = A X y
49
5
5
Analysis 52 2 JK F-F (A, B) Input x Q t+ = JQ + K Q
53
54
55
56
57
58
Analysis 2 T F-F ( A, B ) input X output Y Q t+ = T Q The input equations are T_A = BX T_B = X The out put equation is Y = AB The characteristic equations are : A t+ = T_A A = BX A = BX(A ) + (BX) A = A BX + AB + AX B t+ = X B 59
6
6