Synchronous Sequential Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/
Outlines Sequential Circuits Storage Elements: Latches Storage Elements: Flip-Flops Analysis of Clocked Sequential Circuits State Reduction and Assignment Design Procedure HDL Description DCD-05-2
Sequential Circuits Sequential Circuits a feedback path the state of the sequential circuit (inputs, current state) (outputs, next state) synchronous: the transition happens at discrete instants of time asynchronous: at any instant of time DCD-05-3
Sequential Circuits Synchronous sequential circuits a master-clock generator to generate a periodic train of clock pulses the clock pulses are distributed throughout the system clocked sequential circuits most commonly used no instability problems the memory elements: flip-flops binary cells capable of storing one bit of information two outputs: one for the normal value and one for the complement value maintain a binary state indefinitely until directed by an input signal to switch states DCD-05-4
Synchronous Clocked Sequential Circuit Digital Circuit Design DCD-05-5
SR Latch with two NOR gates S-R Latch 1->0 0->1->0->1 1->0 0->1->0->1 DCD-05-6
S-R Latch SR latch with two NAND gates an asynchronous sequential circuit (S,R)= (1,1): no operation (S,R)=(1,0): reset (Q=0, the clear state) (S,R)=(0,1): set (Q=1, the set state) (S,R)=(0,0): indeterminate state (Q=Q'=0) consider (S,R) = (0,0) (1,1) DCD-05-7
SR latch with control input En=0, no change En=1, see the function table S-R Latch DCD-05-8
D Latch eliminate the undesirable conditions of the indeterminate state in the RS flip-flop D: data gated D-latch D Latch D Q when C=1; no change when C=0 DCD-05-9
Graphic Symbols DCD-05-10
Flip-Flops A trigger: The state of a latch or flip-flop is switched by a change of the control input. Level sensitive latches Edge triggered flip-flops Clock response in latch and flip-flop DCD-05-11
Negative Edge-Triggered D Flip-Flop Master-Slave D flip-flop Two separate flip-flops A master flip-flop (positive-level triggered) A slave flip-flop (negative-level triggered) The most economical and efficient Digital Circuit Design DCD-05-12
Positive Edge-Triggered D Flip-Flop A D-type positive-edge-triggered flip-flop Digital Circuit Design Three basic flip-flops (S,R) = (0,1): Q = 1 (S,R) = (1,0): Q = 0 (S,R) = (1,1): no operation (S,R) = (0,0): should be avoided D-type positive-edge-triggered flip-flop DCD-05-13
Positive Edge-Triggered D Flip-Flop Operations of D-type positive-edge-triggered flip-flop The S and R inputs of the output latch are maintained at the logic-1 level when Clk=0. If D=0 When Clk becomes 1, R changes to 0. This causes the flip-flop to go to reset state making Q=0. If there is a change in the D input while Clk=1, terminal R remains at 0, terminal S remains at 1, and Q=0. Thus, the filp-flop is locked out and is unresponsive to futher changes in the input. When the Clk returns to 0, R goes to 1, placing the output latch in quiescent condition without changing the output. Digital Circuit Design DCD-05-14
Positive Edge-Triggered D Flip-Flop Digital Circuit Design Clk D S R Q DCD-05-15
JK flip-flop D=JQ'+K'Q J-K Flip-Flop J=0, K=0: D=Q(t) Q(t+1) =Q(t): No change J=0, K=1: D=0 Q(t+1) =0: Reset J=1, K=0: D=1 Q(t+1) =1: Set J=1, K=1: D=Q (t) Q(t+1) =Q (t): Complement DCD-05-16
T Flip-Flop D = T Q = TQ'+T'Q T=0: D=Q Q(t+1) =Q(t): No change T=1: D=Q' Q(t+1) =Q (t): Complement DCD-05-17
Characteristic Table Characteristic equations D flip-flop Q(t+1) = D JK flip-flop Q(t+1) = JQ'+K'Q T flip-flop Q(t+1) = T Q DCD-05-18
Direct Inputs Asynchronous set and/or asynchronous reset 1 1 D flip-flop with asynchronous reset DCD-05-19
Analysis of Clocked Sequential Ckts State equation A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A'(t)x(t) Output equation y(t) = (A(t)+B(t))x'(t) DCD-05-20
State Table First Form DCD-05-21
State Table Second Form A(t + 1) =Ax + Bx B(t + 1) = A x y = Ax + Bx DCD-05-22
State Diagram State transition diagram a circle: a state a directed lines connecting the circles: the transition between the states Each directed line is labeled 'inputs/outputs a logic diagram a state table a state diagram DCD-05-23
Flip-Flop Input Equations The part of circuit that generates the inputs to flipflops Also called excitation functions D A = Ax + Bx D B = A'x The output equations y = (A+B)x' DCD-05-24
Analysis with D flip-flops The input equation D A =A x y The state equation A(t+1)=A x y DCD-05-25
Analysis with JK flip-flops Determine the flip-flop input function in terms of the present state and input variables Use the corresponding flip-flop characteristic table to determine the next state DCD-05-26
Analysis with JK flip-flops J A = B, K A = Bx' J B = x', K B = A'x + Ax derive the state table DCD-05-27
Analysis with JK flip-flops State transition diagram ' A( t 1) J A' K A A A ' B( t 1) J B' K B B B State diagram A( t 1) BA' ( Bx')' A AB ' AB' Ax B( t 1) x' B' ( A x)' B B' x' ABx A' Bx' DCD-05-28
Analysis with T flip-flops The characteristic equation Q(t+1)= T Q = TQ'+T'Q DCD-05-29
Analysis with T flip-flops The input and output functions T A =Bx T B = x y = AB The state equations A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx B(t+1) = x B DCD-05-30
Analysis with T flip-flops State table T A T B 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 DCD-05-31
Mealy and Moore Models Mealy model: the output is the function of both the present state and inputs. the outputs may change if the inputs change during the clock pulse period Moore model: the output is the function of the present state only. The outputs are synchronous with the clocks. DCD-05-32
Mealy and Moore Models DCD-05-33
State Reduction and Assignment Digital Circuit Design State Reduction reductions on the number of flip-flops and the number of gates An example state diagram state a a b c d e f f g f g a b d f input 0 1 0 1 0 1 1 0 1 0 0 1 1 1 output 0 0 0 0 0 1 1 0 1 0 0 0 0 1 DCD-05-34
Algorithm: equivalent states Two states are said to be equivalent. For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state One of them can be removed State Reduction g=e DCD-05-35
State Reduction Reducing the state table based on g=e f=d DCD-05-36
The final sequence list: state a a b c d e d d e d e a input 0 1 0 1 0 1 1 0 1 0 0 output 0 0 0 0 0 1 1 0 1 0 0 State Reduction DCD-05-37
Reduced State Diagram Checking of each pair of states for possible equivalence can be done systematically The unused states are treated as don't-care condition fewer combinational gates DCD-05-38
State Assignment Minimize the cost of the combinational circuits Three possible binary state assignments DCD-05-39
State Assignment Any binary number assignment is satisfactory as long as each state is assigned a unique number use binary assignment 1 DCD-05-40
Design Procedure From the word description and specification of the desired operation, derive a state diagram for the circuit. Reduce the number of states if necessary. Assign binary values to the states. Obtain the binary-coded state table. Choose the type of flip-flops to be used. Derive the simplified flip-flop input equations and output equations. Draw the logic diagram. DCD-05-41
Specification: Design a circuit that detects a sequence of three or more consecutive 1 s in a string of bits coming through an input line (i.e., the input is a serial bit stream). State Diagram: Sequence Detector Using D Flip-Flops Starting with state S 0, the reset state Digital Circuit Design If the input is 0, the circuit stays in S 0, but if the input is 1, it goes to state S 1 to indicate that a 1 was detected. If the next input is 1 (i.e., two consecutive 1s), the change is to state S 2 to indicate the arrival of two consecutive 1 s, but if the input is 0, the state goes back to S 0. If the next input is 1, (i.e., three consecutive 1s), the change is to state S 3 to indicate the arrival of three consecutive 1 s, but if the input is 0, the state goes back to S 0. If more 1s are detected, the circuits stays in S 3. Any 0 input sends the circuit back to S 0. Moore machine!! DCD-05-42
Sequence Detector Using D Flip-Flops Sequence detector state diagram and state table Digital Circuit Design 00 01 11 10 DCD-05-43
Sequence Detector Using D Flip-Flops Digital Circuit Design DCD-05-44
The flip-flop input equations A(t+1) = D A (A,B,x) = S(3,5,7) B(t+1) = D B (A,B,x) = S(1,5,7) The output equation y(a,b,x) = S(6,7) Logic minimization using the K map D A = Ax + Bx D B = Ax + B'x y = AB Sequence Detector Using D Flip-Flops Digital Circuit Design DCD-05-45
Sequence Detector Using D Flip-Flops The logic diagram Digital Circuit Design DCD-05-46
Excitation Tables A state diagram flip-flop input functions straightforward for D flip-flops we need excitation tables for JK and T flip-flops DCD-05-47
Synthesis Using JK Flip-Flops The state table and JK flip-flop inputs DCD-05-48
Synthesis Using JK Flip-Flops DCD-05-49
Synthesis Using JK Flip-Flops DCD-05-50
3-Bit Binary Counter Using T Flip-Flops An n-bit binary counter the state diagram no inputs (except for the clock input) DCD-05-51
3-Bit Binary Counter Using T Flip-Flops The state table and the flip-flop inputs 0 DCD-05-52
3-Bit Binary Counter Using T Flip-Flops DCD-05-53
Logic simplification using the K map T A2 = A 1 A 0 T A1 = A 0 T A0 = 1 Digital Circuit Design 3-Bit Binary Counter Using T Flip-Flops The logic diagram DCD-05-54
Synthesizable HDL Models of Sequential Circuits Behavioral Modeling Example: Two ways to provide free-running clock Example: Another way to describe free-running clock 5-55
always statement Behavioral Modeling Examples: Two procedural blocking assignments: Two nonblocking assignments: 5-56
HDL Models of Flip-Flops and Latches HDL Example 5.1 5-57
HDL Example 5.2 Flip-Flops and Latches 5-58
Characteristic Equation Q(t + 1) = Q T For a T flip-flop Q(t + 1) = JQ + K Q For a JK flip-flop HDL Example 5.3 5-59
HDL Example 5-3 (Continued) 5-60
HDL Example 5-4 (JK Flip-Flop) Functional description of JK flip-flop 5-61
State Diagram-Based HDL Models (1/3) HDL Example 5.5 Mealy Machine: Zero Detector Digital Circuit Design 5-62
State Diagram-Based HDL Models (2/3) Digital Circuit Design 5-63
State Diagram-Based HDL Models (3/3) Digital Circuit Design 5-64
Mealy_Zero_Detector 5-65
HDL Example 5-6 Moore Machine: Zero Detector Digital Circuit Design 5-66
Simulation Output of HDL Example 5-6 Digital Circuit Design 5-67
Structural Description of Clocked Sequential Circuits HDL Example 5.7 Binary Counter_Moore Model Digital Circuit Design 5-68
Structural Description of Clocked Sequential Circuits Digital Circuit Design 5-69
Structural Description of Clocked Sequential Circuits Digital Circuit Design 5-70
Structural Description of Clocked Sequential Circuits Digital Circuit Design 5-71
Simulation Output of HDL Example 5-7 Digital Circuit Design 5-72
Conclusion From this lecture, you have learned the follows: Storage Elements: SR Latch, D Latch Storage Elements: D Flip-Flop, JK Flip-Flop, T Flip- Flop Analysis of Clocked Sequential Circuits State Reduction and Assignment Design Procedure Verilog Design DCD-05-73