Spring 2015 Week 6 Module 33 Digital Circuits and Systems Timing Sequential Circuits Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay
Sequential Circuit Timing Once the functionality of a sequential network is designed, its timing parameters must be determined. Timing problems can be very subtle because timing parameters can vary with device age and other operating conditions. Analysis and Design of Sequential Logic Circuits 2
Timing Parameters Global setup time (T su ) Global hold time (T h ) Maximum clock frequency Clock skew. These parameters are derived using the circuit (known) delays described below. t io delay from input of IFL to output of OFL t if delay from circuit inputs of flip-flop inputs t fo delay from flip-flop outputs to circuit outputs delay from flip-flop outputs to flip-flop inputs t c-q clock to Q propagation delay of flip-flops t su setup time of flip-flops t h hold time of flip-flops t c clock delay; time required for clock to reach all flip-flops Analysis and Design of Sequential Logic Circuits 3
Global Setup and Hold Times Changes that occur at inputs can be delayed by as much as maximum t if by the time they reach the flip-flop inputs. Hence, we want to setup circuit inputs relative to clock edge appearing at the flip-flops. T su T h t c CLK (at clock source) t h CK (at FF clock input) t if t su X (at sequential circuit input) T s t t t u su if c max max min Similarly, hold time of the circuit inputs relative to the system clock at the source is given by T t t t h t if h if c max min max D (at FF input) Analysis and Design of Sequential Logic Circuits 4
Maximum Clock Frequency D j Q j CLK Comb. logic Λ CK j D i Λ Q i Q i D j t su t C-Q T ck (=T clk ) Edge Triggering For an edge-triggered circuit: minimum clock period is, Maximum Clock Frequency: T clk t t t C Qmax ffmax sumax f clk 1 T clk Analysis and Design of Sequential Logic Circuits 5
Timing Violations T t t t ck l C Q ff su max max max The clock period (T clk ) has a lower bound of.max. If the clock period is equal to (.max + t C-Q.max ) then the flip-flop state changes can violate setup times. Remedy : Use faster flip-flops (decrease t C-Q ) Use faster gates (decrease ) Use a slower clock (increase clock period, T clk ) Analysis and Design of Sequential Logic Circuits 6
Clock Skew The previous discussion assumes that clock signals arrive at all flip-flops simultaneously - this is not a good assumption since it is not true in practice. Because of different wire lengths over which the clock signals travel and the load at the destination, there is a slight difference in clock arrival times at different flip-flop inputs. Clock skew, t skew, is the difference in time between triggering edges seen at different flip-flops. Clock skew affects minimum T clk. Analysis and Design of Sequential Logic Circuits 7
Max. Clock Frequency with Skew D j Q j t skew Comb. logic Λ CK j CK j t C-Q D i Λ Q i t skew Q j t su CLK D i T ck (=T clk ) Therefore, for an edge-triggered circuit with clock skew, T t t t t clk skew C Q ff su max max max max Clock skew is a significant factor in determining the speed of highperformance synchronous circuits. The larger the skew, the slower the circuit will operate. Analysis and Design of Sequential Logic Circuits 8
Timing Analysis Example For the circuit given below determine all the sequential circuit timing parameters. For a D flip-flop use: t su = 2ns, t h = 15ns and t C-Q = 20ns For a NAND gate use: t p,max = 10ns and t p,min = 3ns Analysis and Design of Sequential Logic Circuits 10
t t. t t t t if,max if,min ff,max ff,min c,max c,min 3t 2t 2t 2t 2t 2t p,max, nand p,min, nand p,max, nand p,min, nand p,max, nand p,min, nand 30ns 6ns 20ns 6ns 20ns 6ns For a D flip-flop use: t su = 2ns, t h = 15ns, t C-Q = 20ns For a NAND gate use: t p,max = 10ns, t p,min = 3ns T t t t 2 30 6 26ns su su,max if,max c,min T t t t 20 15 6 29ns h h,max if,min c,max T t t t 20 20 2 42ns clk C Q,max ff,max su,max f 1/ 42ns 23.8MHz clk,max Analysis and Design of Sequential Logic Circuits 11
Sequential Systems Using Latches Latches can be used to create sequential systems. However, since these are level-triggered clocking must be done carefully must ensure that state changes only once per clock cycle. t w <.min + t D-Q.min D j Q j Comb. logic CK j CLK D i Q i > (t D-Q.max +.max + t su.max ) CLK Use narrow-width clock whose pulse width is less than the fastest possible path through the combinational logic. To guarantee correct next state, make sure that the clock period is longer than the worst-case propagation delay through the combinational logic. Analysis and Design of Sequential Logic Circuits 12
Clocking Frequency with Latches T clk t skew Comb. logic D j CK j D i Q j Q i t skew CK j D j t w t su t D-Q CLK Q j t su D i T t t t t t t clk skew w su D Q ff su max min max max max Analysis and Design of Sequential Logic Circuits 14
End of Week 6: Module 33 Thank You Intro to State Machines 15