ECEN454 igital Integrated Circuit esign Sequential Circuits ECEN 454 Combinational logic Sequencing Output depends on current inputs Sequential logic Output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in CL out CL CL Finite State Machine Pipeline ECEN 454 10.2 1
Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones ECEN 454 10.3 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence ECEN 454 10.4 2
: Level sensitive Sequencing Elements a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Flop Opaque Edge-trigger (latch) (flop) ECEN 454 10.5 : Level sensitive Sequencing Elements a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Flop Opaque Edge-trigger (latch) (flop) ECEN 454 10.6 3
esign Pass Transistor Pros + + Cons ECEN 454 10.7 esign Pass Transistor Pros + Tiny + Low clock load Cons V t drop nonrestoring Used in 1970 s backdriving output t noise sensitivity dynamic diffusion input ECEN 454 10.8 4
esign Transmission gate + - ECEN 454 10.9 esign Transmission gate +No V t drop - Requires inverted clock ECEN 454 10.10 5
esign Inverting buffer + + + Fixes either ECEN 454 10.11 esign Inverting buffer + Restoring + No backdriving + Fixes either Output noise sensitivity Or diffusion input Inverted output ECEN 454 10.12 6
esign Tristate feedback + ECEN 454 10.13 esign Tristate feedback + Static Backdriving risk Static latches are now essential ECEN 454 10.14 7
esign Buffered input + + ECEN 454 10.15 esign Buffered input + Fixes diffusion input + Noninverting ECEN 454 10.16 8
esign Buffered output + ECEN 454 10.17 Buffered output esign + No backdriving Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading ECEN 454 10.18 9
esign atapath latch + - ECEN 454 10.19 esign atapath latch + Smaller, faster - unbuffered input ECEN 454 10.20 10
Metastability A A Stable A=B=0 B A=> B =>B Metastable A=B=V m A, B Stable A=B=V ECEN 454 10.21 Flip-Flop esign Flip-flop is built as pair of back-to-back latches ECEN 454 10.22 11
Enable Enable: ignore clock when en = 0 Mux: increase latch - delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en 1 0 en en en Flop 1 0 en Flop en ECEN 454 10.23 Flop Reset Force output low when reset asserted Synchronous vs. asynchronous Symbol Flop reset reset Synchronous Reset reset reset Asynchronous Reset reset reset reset reset ECEN 454 10.24 12
Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset set reset reset set ECEN 454 10.25 Flip-flops 2-Phase es Sequencing Methods ECEN 454 10.26 13
Timing iagrams Contamination and Propagation elays A Combinational Logic Y A Y t cd t pd t pd t cd Logic Prop. elay Logic Cont. elay t setup thold t pcq /Flop Clk-> Prop. elay Flop t ccq /Flop Clk-> Cont. elay t ccq t pcq t pdq -> Prop. elay t cdq t setup t hold -> Cont. elay /Flop Setup Time /Flop Hold Time h t ccq t pcq t setup t hold t cdq t pdq ECEN 454 10.27 Max-elay: Flip-Flops F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 t pd < T c ( t setup + t pcq ) sequencing overhead ECEN 454 10.28 14
Max elay: 2-Phase es 1 2 1 t pd = t pd1 + t pd2 < T c 2t pdq sequencing overhead 1 1 Combinational 2 2 Combinational 3 Logic 1 Logic 2 1 L1 L2 L3 3 2 T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 ECEN 454 10.29 Min-elay: Flip-Flops t cd F1 1 CL 2 F2 1 t ccq t cd 2 t hold ECEN 454 10.30 15
Min-elay: Flip-Flops t t t cd hold ccq F1 1 CL 2 F2 1 t ccq t cd 2 t hold ECEN 454 10.31 Min-elay: 2-Phase es 1 t t cd 1, cd 2 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! 1 2 t nonoverlap 1 2 t ccq t hold t cd ECEN 454 10.32 16
Min-elay: 2-Phase es t t t t t cd1, cd 2 hold ccq nonoverlap 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! 1 2 t nonoverlap 1 2 t ccq t hold t cd ECEN 454 10.33 Time Borrowing In a flop-based system: ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system ata can pass through h latch while transparent t Long cycle of logic can borrow time into next As long as each loop completes in one cycle ECEN 454 10.34 17
Time Borrowing Example 1 2 1 1 2 (a) Combinational Logic Combinational Logic Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Combinational Logic Combinational Logic Loops may borrow time internally but must complete within the cycle ECEN 454 10.35 How Much Borrowing? 2-Phase es T c borrow setup nonoverlap t t t 2 1 1 2 L1 1 2 Combinational Logic 1 LCombinational L2 2 1 2 t nonoverlap T c T c /2 Nominal Half-Cycle 1 elay t borrow t setup 2 ECEN 454 10.36 18
Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay requirement Increases minimum contamination delay requirement ecreases time borrowing ECEN 454 10.37 Skew: Flip-Flops F1 1 Combinational Logic 2 F2 T c t pd < T c ( t setup + t pcq + t skew ) 1 t pcq t pdq t setup t skew sequencing overhead 2 t cd > t hold t ccq + t skew F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd ECEN 454 10.38 19
Skew: 2-Phase es 1 2 1 1 1 Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 1 2 t pd = t pd1 + t pd2 < T c 2t pdq sequencing overhead: not influenced by skew t cd1, t cd2 > t hold t ccq t nonoverlap + t skew t borrow < T c /2 ( t setup + t nonoverlap + t skew ) ECEN 454 10.39 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) ECEN 454 10.40 20
Flip-Flops: Summary Very easy to use, supported by all tools 2-Phase Transparent es: Lots of skew tolerance and time borrowing ECEN 454 10.41 21