Fundamentals of omputer Systems Sequential Logic Martha A. Kim olumbia University Spring 2016 1/1
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Bistable Elements Equivalent circuits; right is more traditional. Two stable states: 0 1 1 0 3/1
S Latch S S S 0 0 0 1 1 0 1 1 4/1
S Latch 0 1 S S 1 0 S 0 0 0 1 1 0 Set ( = 1) 1 0 1 1 4/1
S Latch 1 0 S S 0 1 S 0 0 0 1 1 0 Set ( = 1) 1 0 0 1 eset ( = 0) 1 1 4/1
S Latch 0 (0 + )= S S 0 (0 + )= S 0 0 Hold previous value 0 1 1 0 Set ( = 1) 1 0 0 1 eset ( = 0) 1 1 4/1
S Latch 1 0 S S 1 0 S 0 0 Hold previous value 0 1 1 0 Set ( = 1) 1 0 0 1 eset ( = 0) 1 1 0 0 Bad. o not use. 4/1
S Latch S S S 0 0 1 1 Bad. o not use. 0 1 0 1 eset ( = 0) 1 0 1 0 Set ( = 1) 1 1 Hold previous value 5/1
Latch 0 X 1 0 0 1 1 1 1 0 6/1
A hallenge: Build a traffic light controller Want the lights to cycle green-yellow-red. Y G oes this work? 7/1
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Positive-Edge-Triggered Flip-Flop M Master S Slave M 0 S transparent opaque 10 / 1
Positive-Edge-Triggered Flip-Flop M Master S Slave M 0 S transparent opaque 10 / 1
Positive-Edge-Triggered Flip-Flop M Master S Slave M 0 S transparent opaque opaque transparent 10 / 1
Positive-Edge-Triggered Flip-Flop M Master S Slave M 0 S transparent opaque opaque transparent 10 / 1
Positive-Edge-Triggered Flip-Flop M Master S Slave M transparent opaque transparent 0 S opaque transparent opaque 10 / 1
Positive-Edge-Triggered Flip-Flop M Master S Slave M transparent opaque transparent opaque 0 S opaque transparent opaque transparent 10 / 1
The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
The Traffic Light ontroller: A second try Let s try this again with flip-flops. Y G Y G 11 / 1
The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
The Traffic Light ontroller with eset ESET Y G ESET Y G 12 / 1
Flip-Flop with Enable 0 1 E E " 0 X " 1 0 0 " 1 1 1 0 X X 1 X X E What s wrong with this solution? 13 / 1
Asynchronous Preset/lear PE L PE L 14 / 1
The Traffic Light ontroller w/ Async. eset ESET PE L PE L Y PE L G 15 / 1
The Synchronous igital Logic Paradigm Gates and flip-flops only INPUTS OUTPUTS Each flip-flop driven by the same clock STATE L Every cyclic path contains at least one flip-flop LOK NEXT STATE 16 / 1
ool Sequential ircuits: Shift egisters A 0 1 2 3 A 0 1 2 3 0 X X X X 1 0 X X X 1 1 0 X X 0 1 1 0 X 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 17 / 1
Universal Shift egister L 3 2 0 0 1 0 3 2 1 1 1 0 3 2 2 2 1 0 3 2 3 3 1 0 S 1 S0 S 1 S 0 3 2 1 0 0 0 3 2 1 0 1 3 2 1 0 1 0 3 2 1 0 1 1 2 1 0 L S 1 S 0 Operation 0 0 Shift right 0 1 Load 1 0 Hold 1 1 Shift left 18 / 1
ool Sequential ircuits: ounters ycle through sequences of numbers, e.g., 00 01 10 11 19 / 1
Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change t su 20 / 1
Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h 20 / 1
Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h Minimum Propagation elay: Time from clock edge to when might start changing t p(min) 20 / 1
Flip-Flop Timing Setup Time: Time before the clock edge after which the data may not change Hold Time: Time after the clock edge after which the data may change t su t h Minimum Propagation elay: Time from clock edge to when might start changing t p(min) t p(max) Maximum Propagation elay: Time from clock edge to when guaranteed stable 20 / 1
Timing in Synchronous ircuits L t c t c : lock period. E.g., 10 ns for a 100 MHz clock 21 / 1
Timing in Synchronous ircuits L Sufficient Hold Time? t p(min,ff) t p(min,l) Hold time constraint: how soon after the clock edge is liable to start changing? Min. FF delay + min. logic delay 21 / 1
Timing in Synchronous ircuits L t p(max,ff) Sufficient Setup Time? t p(max,l) Setup time constraint: when before the clock edge is guaranteed to have stabilized? Max. FF delay + max. logic delay 21 / 1
lock Skew: What eally Happens L 1 2 Sufficient Hold Time? 1 2 t skew t p(min,ff) t p(min,l) 2 arrives late, creating potential hold time violation 22 / 1
lock Skew: What eally Happens L 1 2 Sufficient Setup Time? 1 2 t skew t p(max,ff) t p(max,l) 2 arrives early, creating potential setup time violation 22 / 1