Registers and Counters ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/
Registers Shift Registers Ripple Counters Synchronous Counters Other Counter HDL Description Outlines DCD-06-2
Registers Clocked sequential circuits a group of flip-flops and combinational gates connected to form a feedback path Flip-flops + Combinational gates (essential) (optional) Register: a group of flip-flops gates that determine how the information is transferred into the register Counter: a register that goes through a predetermined sequence of states DCD-06-3
Four-Bit Register An n-bit register n flip-flops capable of storing n bits of binary information 4-bit register DCD-06-4
Four-bit Register with Parallel Load and No Change DCD-06-5
Shift Registers Shift register a register capable of shifting its binary information in one or both directions Simplest shift register 1 1 0 1 1 0 1 1 0 1 Four-bit shift register DCD-06-6
Transfer Serial transfer vs. Parallel transfer Serial transfer Information is transferred one bit at a time shift the bit out of the source register into the destination register Parallel transfer: All the bits of the register are transferred at the same time DCD-06-7
Serial Transfer from Reg A to Reg B 1 0 1 1 0 0 1 0 DCD-06-8
Serial Transfer from Reg A to Reg B DCD-06-9
Serial Adder Using D Flip-Flops 4-Bit SR 4-Bit SR DCD-06-10
Serial Adder Using D Flip-Flops Clk SC SI_B SO_B 1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 SO_A 1 0 1 0 S 1 0 1 0 0 0 0 1 C 1 1 1 0 0101+0011=1000 DCD-06-11
Serial Adder Using JK Flip-Flops Digital Circuit Design J Q = x y K Q = x y = (x + y) S = x y Q DCD-06-12
Serial Adder Using JK Flip-Flops Digital Circuit Design Ci Second form of serial adder DCD-06-13
Universal Shift Register Shift Register Unidirectional shift register Bidirectional shift register Universal shift register: has both direction shifts & parallel load/out capabilities Capability of a universal shift register: 1. A clear control to clear the register to 0. 2. A clock input to synchronize the operations. 3. A shift-right control to enable the shift right operation and the serial input and output lines associated with the shift right. 4. A shift-left control to enable the shift left operation and the serial input and output lines associated with the shift left. 5. A parallel-load control to enable a parallel transfer and the n parallel input lines associated with the parallel transfer. 6. n parallel output lines. 7. A control state that leaves the information in the register unchanged in response to the clock. DCD-06-14
Four-Bit Universal Shift Register Clear s1 s0 A3+ A2+ A1+ A0+ (operation) 0 0 0 0 0 Clear 1 0 0 A3 A2 A1 A0 No change 1 0 1 sri A3 A2 A1 Shift right 1 1 0 A2 A1 A0 sli Shift left 1 1 1 I3 I2 I1 I0 Parallel load DCD-06-15
Four-Bit Universal Shift Register A 0 DCD-06-16
Ripple Counters Counter: a register that goes through a prescribed sequence of states upon the application of input pulses Input pulses: may be clock pulses or originate from some external source The sequence of states: may follow the binary number sequence ( Binary counter) or any other sequence of states Categories of counters Ripple counters: The flip-flop output transition serves as a source for triggering other flip-flops. no common clock pulse (not synchronous) Synchronous counters: The CLK inputs of all flip-flops receive a common clock. DCD-06-17
Four-Bit Binary Ripple Counter A simple complement flip-flop can be obtained: from a JK flip-flop with the J and K inputs tied together from T flip-flop use a D flip-flop with the complement output connected to the D input. Example: 0011=>0100 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 DCD-06-18
Four-Bit Binary Ripple Counter DCD-06-19
Timing Analysis of Binary Ripple Counter Digital Circuit Design Count A 0 0 1 0 1 0 1 0 1 0 1 0 1 A 1 0 0 1 1 0 0 1 1 0 0 1 1 A 2 0 0 0 0 1 1 1 1 0 0 0 0 A 3 0 0 0 0 0 0 0 0 1 1 1 1 DCD-06-20
BCD Ripple Counter Hint1: Q 1 changes state after each clock pulse. Hint 2: Q 2 complements every time Q 1 goes from 1 to 0 as long as Q 8 =0. When Q 8 becomes 1, Q 2 remains at 0. Hint 3: Q 4 complements every time Q 2 goes from 1 to 0. Hint 4: Q 8 remains at 0 as long as Q 2 or Q 4 is 0. When both Q 2 and Q 4 become 1, Q 8 complements when Q 1 goes from 1 to 0. Q 8 is cleared on the next transition of Q 1. DCD-06-21
Three-Decade BCD Ripple Counter Digital Circuit Design DCD-06-22
Synchronous Counters Synchronous counter A common clock triggers all flip-flops simultaneously. Design procedure apply the same procedure of sync seq ckts Sync counter is simpler than general sync seq ckts DCD-06-23
Four-Bit Sync. Binary Counter up down down A' 0 up A 0 down A' 0 A' 1 up A 0 A 1 down A' 0 A' 1 A' 2 Four-bit synchronous binary counter Four-bit up-down binary counter DCD-06-24
Timing Analysis of Sync. Binary Counter Digital Circuit Design Clk CE A 0 0 1 0 1 0 1 0 1 0 1 0 1 A 1 0 0 1 1 0 0 1 1 0 0 1 1 A 2 0 0 0 0 1 1 1 1 0 0 0 0 A 3 0 0 0 0 0 0 0 0 1 1 1 1 DCD-06-25
Sync. BCD Counters 1 0 1 0 X X X X X X X X X 1 0 1 1 X X X X X X X X X 1 1 0 0 X X X X X X X X X 1 1 0 1 X X X X X X X X X 1 1 1 0 X X X X X X X X X 1 1 1 1 X X X X X X X X X DCD-06-26
Sync. BCD Counters 1 T Q 1 T Q 2 T Q 4 T Q 8 C C C C y CLK Simplified functions: Need to consider other unused 6 cases DCD-06-27
Four-Bit Sync. Binary Counter with Parallel Load DCD-06-28
Four-Bit Sync. Binary Counter with Parallel Load DCD-06-29
Sync. BCD Counter with Parallel Load Generate any count sequence: E.g.: BCD counter Counter with parallel load Digital Circuit Design DCD-06-30
Other Counters Counters: can be designed to generate any desired sequence of states Divide-by-N counter (modulo-n counter) a counter that goes through a repeated sequence of N states The sequence may follow the binary count or may be any other arbitrary sequence n flip-flops 2 n binary states Unused states states that are not used in specifying the FSM may be treated as don t-care conditions or may be assigned specific next states Self-correcting counter Ensure that when a ckt enters one of its unused states, it eventually goes into one of the valid states after one or more clock pulses so it can resume normal operation. Analyze the ckt to determine the next state from an unused state after it is designed DCD-06-31
Counters with Unused States An example 0 1 1 1 0 0 1 X X 1 X 1 1 1 1 0 0 0 X 1 X 1 X 1 Two unused states: 011 & 111 The simplified flip-flop input eqs: J A = B, K A = B, J B = C, K B = 1, J C = B, K C = 1 DCD-06-32
Counter with Unsigned States DCD-06-33
Ring Counter Ring counter: a circular shift register with only one flip-flop being set at any particular time, all others are cleared (initial value = 1 0 0 0 ) The single bit is shifted from one flip-flop to the next to produce the sequence of timing signals. T 0 T 1 T 2 T 3 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 DCD-06-34
Ring Counter Application of counters Counters may be used to generate timing signals to control the sequence of operations in a digital system. Approaches for generation of 2 n timing signals Method 1: a shift register with 2 n flip-flops Method 2: an n-bit binary counter together w/ an n-to-2 n -line decoder DCD-06-35
Johnson Counter Ring counter vs. Switch-tail ring counter Ring counter a k-bit ring counter circulates a single bit among the flip-flops to provide k distinguishable states. Switch-tail ring counter is a circular shift register w/ the complement output of the last flip-flop connected to the input of the first flip-flop a k-bit switch-tail ring counter will go through a sequence of 2k distinguishable states. (initial value = 0 0 0) Disadv. of the switch-tail ring counter if it finds itself in an unused state, it will persist to circulate in the invalid states and never find its way to a valid state. Johnson counter a k-bit switch-tail ring counter + 2k decoding gates provide outputs for 2k timing signals DCD-06-36
Johnson Counter DCD-06-37
HDL for Registers and Counters Shift Register Statement: A_par <= {MSB_in, A_par [3: 1]} specifies a concatenation of serial data input for a right shift operation (MSB_in) with bits A_par[3 : 1] of the output data bus. 38
HDL Example 6.1 (Universal Shift Register Behavioral Model) 39
Variables of type reg retain their value until they are assigned a new value by an assignment statement. Consider the following alternative case statement for the shift register model: 40
HDL Example 6.2 (Universal Shift Register Structural Model) 41
HDL Example 6.2 (2/3) Digital Circuit Design 42
HDL Example 6.2 (3/3) Digital Circuit Design 43
HDL Example 6.3 (Synchronous Counter) 44
HDL Example 6.4 (Ripple Counter) Digital Circuit Design 45
HDL Example 6.4 46
Simulation Output of HDL Example 6.4 47
Simulation Output of HDL Example 6.4 48
Conclusion From this lecture, you have learned the follows: Registers Shift Registers Ripple Counters Synchronous Counters Other Counter Verilog Design DCD-06-49