DESIGN O'F A HIGH SPEED DDA

DESIGN O'F A HIGH SPEED DDA Mark W. Goldman Gidance and Control Department Martin Company Baltimore, Maryland INTRODUCTION The objective of the company-fnded task which spported this work was to develop techniqes for high-speed soltions to differential eqations, particlarly those which are common in aerospace problems. For example, the soltion reqirements for reentry gidance are very time-limit~d and mst be processed at the highest priority level. To solve this type of problem, depending on the accracy reqired, the nmber of iterations can get nreasonably large and reqire an inordinate amont of compter "power." Therefore, the soltion time reqirements led s to investigate means other than the general prpose compter to solve these timecritical differential eqations. The natre of the problem and the aerospace reqirements of long term drift stability and accracy led s to choose the digital differential analyzer (DDA) as one of the candidates for investigation. This paper, then, is concerned with the new techniqes in DDA design which were developed in order to meet the soltion time objectives. Or work on DDA's centered abot the Chapman predictive reentry gidance eqation. This eqation was chosen as a vehicle for stdy, first, becase it is representative of a class of aerospace second order nonlinear differential eqations and secondly, becase the soltion time of predictive reentry eqations, particlarly near impact, are very critical. One of or earlier DDA designs reqired approximately 200 seconds to solve the entire Chapman eqation from entry to terminal; the new design can solve the same problem in 0.56 seconds-sing less hardware and at the same accracy. These new techniqes are: 1. Shared integrators. A method of combining several ( 5 in one case) integrators which contain the same variable, and sharing the Y register and adder network with a mltiple bank of R registers. 2. Atomatic rescaling. Instead of scaling the DDA to handle the worst case range of variables, it is scaled to handle a nominal range. When a variable exceeds the range, certain critical integrators are rescaled to modify the increment size of the variable. Since the iteration time of a DDA is dependent on the variable size, this techniqe also allows the DDA to rn at the optimm speed at each region of its soltion. 3. Asynchronos timing. No fixed clock is sed in the design; rather, as each iteration is completed the next one is started. For 929

930 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 example in the Chapman design, the longest critical string of integrators is nine, bt on the average only for will overflow in anyone iteration cycle. In the asynchronos mode the next iteration cycle is started when the longest critical path has been completed. In addition, advanced logic techniqes are sed throghot. For example, carry look-ahead adders -each iteration cycle time is dependent on how many integrators overflow, which in trn is dependent on the time that it takes the integrator adder to detect this overflow and complete the addition. The carry look -ahead adder can add two operands in as little as five gate delays and is completely independent of carry. The gate delays for the microelectronics we are sing reslt in an add time of 50 to 90 nsec. In order to demonstrate the feasibility of the new featres it was not necessary to bild the complete DDA to solve the Chapman eqation. To do so wold have risked hiding the principles of the new featres in the complexity of the Chapman eqation. Instead, each of the new featres is amply demonstrated in a DDA designed to solve the simples eqation, xy" + ~y' + Y = O. This simpler eqation also has the advantage of having a closed form soltion for ease of demonstration. This compter is capable of approximately two million iterations per second. Therefore, the design goal of the project was to stdy the systems and logical organization of DDA's and to develop a machine with a significant speed increase over contemporary designs. Since speed was the target, economics of the design was deemphasized. That is, where cost and speed were in conflict, the faster bt costlier techniqe won. In some cases, the speed retrn may not have been worth the added cost, bt ntil a specific application is to be designed, no yardstick is available to measre the economic worth of one design against another. When weight and size become important, as they often do in aerospace eqipment, then the yardstick is available to tailor down the design to meet the constraints. are an extension to the theory, while the third, asynchronos timing, is an improvement in the constrction. Shared Integrators When two or more integrators store the same variable, they can be combined into one integrator with a corresponding saving in hardware. An example of the shared techniqe is shown in the following sketches. Sketch (a) shows the conventional DDA 1 hookp to obtain reciprocals, in this case - Both integrators store the variable _1_ (in the Y register). Combining the two integrators, sketch (b) provides the shared integrator which also yields 1. The eqivalents between sketches (a) and (b) are illstrated by the flow of plses throgh each figre. A d plse travels along path A. The d plse generates a~ otpt plse which travels along path B. In trn,. the ~ plse generates a d ( + ) plse which travels along path C. d A d c (a otpt NEW TECHNIQUES Dring the system's stdy, several improvements were made over contemporary DDA's. Two of these, shared integrators and atomatic rescaling, (b)

DESIGN OF A HIGH SPEED DDA 931 A more detailed comparison is illstrated below by a block diagram of each integrator. The Y registers in Integrators 1 and 2 contain the same nmbers, bt not the R registers. Therefore, the shared integrator in sketch (b) has two R registers. Register Rl is identical with the R register in Integrator 1 and R2 identical with the R register in Integrator 2. d Integrator 1 d.!!!! fixed point arithmetic, we have developed several techniqes. The first techniqe, referred to as mltiple scales, is a compromise between fixed point and floating point arithmetic. The procedre is to divide the complete range of the variables and scale each sbdivision separately. The individal scales are combined into one compter. The DDA comptes with the scale corresponding to the sbdivision which the variable size happens to be in at the moment. When the variable size changes to a different sbdivision, the DDA atomatically switches to the corresponding scale. Each scale ses fixed point arithmetic, bt the switching from scale to scale as the variable size changes simlates a floating point method. The following is a decimal example demonstrating how the DDA switches from one scale to another. The problem is to compte the reciprocal of where the desired range of is 0.02 ~ ~. 1.000. Therefore, the complete range of _1_ is 0.001 < _1_ ~ 50. - The shared integrator above reqires 1 adder, 1 Y register and 2 R registers where the conventional DDA hookp reqires 2 adders, 2 Y registers and 2 R registers. Atomatic Rescaling A major disadvantage of a conventional DDA is that it ses fixed point arithmetic. This is exemplified by the fact that the scaling is based pon the maximm vale that each variable can assme. If some of the variables very over a large range, then an extremely small independent increment may be necessary to maintain accracy. As the size of the independent increment decreases, the nmber of iterations increases. A GP compter cold solve the same problem with the same accracy sing a larger independent increment if it employs floating point arithmetic. If the GP compter were restricted to fixed point arithmetic, then it wold have fndamentally the same scaling problems encontered by the DDA. To overcome the scaling problems of Consider dividing the range of _1_ into two parts: When 1 0.001 ~ 1 1 < _1_ < 50. - - < 1 is in the range from 0.001 to 1 we se Scale A. When _1_ is in the range from 1 to 50 we se Scale B. Sppose we decide that we want to carry 5 decimal places, then from DDA scaling theory, in Scale A each d, ~ and d ( + ) eqals 10-5 as shown below. d plse

932 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 Then from the normal DDA scaling techniqes 3 both Y registers are 5 digits and 10 0 inside each triangle means the decimal points are at the extreme left as shown below. 10 0 10-1 10-2 10-3 10-4 10-5 [~~~l I I y: register For Scale B, since we wish to maintain the same nmber of decimal places as before, each d plse d 1 mst eqal 10-7, - becomes 10-5, and d- becomes 10-3 as shown below. As the comptation proceeds the nmber in the Y registers decreases. The nmber will eventally reach the vale o 9 9 At this point I. ~ I < 1 and hence in Scale A. The change to Scale A is sensed by detecting the zeros in the two leftmost positions. The scale switching is accomplished by shifting the nmber two places to the left (and the imaginary decimal point also) so it reads As in scale A both Y registers are 5 digits long. The 10 2 inside each triangle means the decimal points are two digits to the right as shown below. 10 1 10 10-1 10-2 10-3 I I I,Y Register Incidentally, the vales of the scaling constants of Scale B are those that wold be sed for the complete range in a convential DDA. An example will show how the DDA atomatically switches from one sale to the other. If _1_= 50 at the start of the comptation, then Scale B is sed and the Y register reads and the R register is reset at 0.5 (its median vale) and the DDA is started again. If the compter happens to be in Scale A and the nmber in the Y register is increasing, then the Y register will eventally read 9 9 9 The next increase (by 1 x 10-5 ) will case the Y register to overflow. The new vale of Y wold be 1 which is in Scale B. The overflow triggers the scale switch from A to B which sets Y register at 10/11.0100 10 1 10 0 10-1 10-2 10-3 5 0 1 0 I 0 I 0 I and resets the R register at 0.5. The nmber of iterations reqired to compte the. reciprocal of from = 0.02 to = 1000 sing Scale A for the complete range is 10 7 (1000-0.02)::::::::: 1.0 x 10 10

DESIGN OF A HIGH SPEED DDA 933 Using mltiple Scales A and B, the same accracy is obtained and the nmber of iterations is 10 7 (1-0.02) + 10 5 (1000-1) ~ 1.1 x 10 8 Another techniqe being considered is to actally se floating point arithmetic. We are presently exploring several methods for mechanizing a DDA to operate with floating point nmbers. Some of the ideas are as follows. The decimal (or binary) point of the Y register is no longer predetermined, and special registers are needed to specify the position of the decimal point. Special control logic will solve the scaling eqations for each iteration and perform the scaling as the DDA is compting. This techniqe shows a great amont of promise. Asynchronos Timing Asynchronos timing is a method of decreasing the iteration time. In conventional DDA's the iteration time is constant becase a fixed clock is sed (synchronos timing). In contrast, asynchronos timing means the next iteration is started as soon as the last one is finished. The DDA hookp for obtaining the reciprocal of will again be sed to explain the principle. Sppose the time reqired to process any inpt plse is T. At the start of each iteration a d plse triggers Integrator 1 (see following sketch). If the R register does not overflow, then no otpt plse occrs and the iteration is finished in time T. If an otpt plse does happen to occr then Integrator 2 is triggered. If the R register of Integrator 2 does not overflow, then no otpt plse from it occrs and the iteration is finished in 2T. If an otpt plse from Integrator 2 does occr, then the lower inpts to both integrators are triggered, and the iteration reqires 3 T. d d Integrator 2 Integrator 1 A smmary of the three possibilities and the time necessary to perform the calclations in each case is tablated here. Integrator I Integrator 2 Occrrence of an Occrrence of an Otpt Plse Otpt Plse No No Yes No Yes Yes Iteration Time Reqired IT 2T 3T For a fixed clock system the iteration time is set for the longest plse path which in this case is 3T. With the asynchronos timing techniqe each integrator has a control section which indicates whether the integrator is calclating. The master control examines each integrator, and it will generate the next d plse each time both integrators become inactive. In this way the iteration time will be 1, 2 or 3T depending on whether none, one, or both R registers overflowed. A good estimate as to the probability a particlar R register will overflow is V:2. Based on this estimate, the probability of no overflows is V:2, of one overflow is 14, and of two overflows is 14. Therefore the average iteration time sing asynchronos timing wold be Ih x IT + 14 x 2T + 14 x 3T = (1 %) T which is an improvement over the 3T reqired for synchronos timing. DDA DESIGN FOR CHAPMAN'S EQUATION In the Introdction we stated or objective was to design a DDA as part of a gidance compter for a lifting re-entry vehicle. This work was based on references 1, 2 and a Martin report, "An Atomatic Predictive Gidance Method for Unmanned Lifting Vehicles Re-entering with Circlar Velocity" by V. Blaes. The report discsses the eqations to be solved by the gidance compter. The comptations divide into two parts: sbrotine FUTURE and sbrotine PREDICT. Figre 1 shows the entire control system which incldes a block diagram of both sbrotines and their interconnection with the vehicle dynamics. The advantages were in favor of a GP (General Prpose) compter to solve sbrotine FUTURE and a DDA to solve sbrotine PREDICT. Sbrotine PREDICT reqires an accrate, high speed soltion of a differential eqation which is best sited for a DDA. The prpose of sbrotine PREDICT is to calclate the footprint size based on the spacecraft position. By varying the lift-drag ratio LID and bank

934 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 angle cp of the spacecraft, the landing spot can be controlled. The footprint specifies the region of the earth where the spacecraft cold possibly land. The idea is to control the spacecraft so the target is in the middle of the footprint. The footprint size is defined by three ranges: (Rx)max, (Rx) min, and (Ry)max which are calclated from Eqs. (1-4). Eqation (1) is Chapman's eqation - a second order, nonlinear differential eqation. Ui r (sin 'I' R y = 30 ) -Z-d, ft Uf Ui r (cozs'l' d Rx = 30 ) Uf (2) (3) Z " Z' Z 1-2 "' / R U = ---+----vtjr--cos~ L ~ U Z D (1) Eqations (2), (3), and (4) are sed to calclate the X and Y components of the range d 'I' = 1_(~) sin cp d D (4) While the spacecraft is entering the atmosphere, sbrotine FUTURE calclates the inpt conditions Zi, Z'i, Ui from the vehicle dynamics. It shold be r------------, L.1 : Initial O'c, <PC I I I Vehicle dynamics Compte vehicle trajectory 3-D, point-mass simlation.-----1 Forth order Rnge-Ktta integration method 2-sec fixed interval integration r--------- --------, Vehicl~ lat, long. I L- V,V, ~.Y ~ I L r-------- --------, I I ~ Inpt! O'C' <PC I Sbrotine ~----..,.----'" FUTURE Z. > 0.002 ~--- Zi<0.002 1 -,.-----------j...------...!vehicle L lat, long.,..11----.. Compte: RX,R tarl Y targ r-----------., I Target lat, long....---i" X, Y, x/ivi ~-----------~ ~! ~------~-------... ~ r-------- -------, I, I I Z., Z.. pnpt I 1 1, 1 I L -"'.---------- ---------, I Footprint size: I Otpt: RX ' R.' Ry I I L ~ max y min max.1 I Sbrotine PREDICT Integrate Chapman's eqation 3 times (1) With (L/D)max' <I> = 0 (2) With (L/D)min' <P = 0 (3) With (L/D)max' <I> = 45 Figre 1. Digital compter simlation - atomatic predictor gidance method.

DESIGN OF A HIGH SPEED DDA 935 emphasized that ZiJ Z'iJ Ui are the vales of ZJ Z'J U corresponding to the spacecraft's position dring the prediction. Sppose the spacecraft's L/ D and cp are known for the entire reentry. If LID and cp are sbstitted into Chapman's eqation and ZiJ Z'iJ Ui are the initial conditions, then the soltion of the range eqations, together with Chapman's eqation, predicts where the spacecraft shold land.. The miximm downrange (Rx)max is the vale of Rx that wold be achieved if the spacecraft wold maintain LID = (LID)max and cp = 0 dring reentry. Similarly, the minimm downrange (Rx)min is the vale of Rx for LID = (LID)min and cp = o. The maximm crossrange (Ry) max is the vale of R y for LID = (LID)max and cp = 45. As often as possible dring the reentry a new prediction is made of the footprint size. Each prediction reqires that Chapman's eqation and range eqations be solved three times in order to obtain (Rx) max, (Rx) min, and (Ry)max. The DDA design sed to solve Chapman's eqation and the range eqations (sbrotine PRE DICT) is given in Fig. 2. The sqare boxes with d inside represent the independent variable increment which starts each iteration cycle. The triangles represent the integrators where the inpts, otpts, and the variables stored in the Y registers are labeled. The arrows indicate the flow of plses. The pentagons and divided circles are sed to represent mltiplexed inpts to the shared integrators. Triangles 1, 6, 9 and 10 are shared integrators. The fnction performed by shared Integrator 1 wold normally reqire for integrators-one for each pentagon. Similarly, shared, Integrator 6 is eqivalent to for integrators, and Integrators 9 and 10 are eqivalent to two integrators each. Conseqently, by sing shar~d integrators we have redced the total nmber of integrators from 20 to 12. Integrators 1 throgh 6 are sed to solve Chapman's eqation. The otpts from Integrators 2, 3, 4, and 6 are smmed together; the reslting sm is Factoring ot d reslts in the right side of Chapman's eqation, Eq. (1). Therefore, the sm of the. Ry.:S~ d U f Figre 2. DDA for Chapman eqation.

936 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 otpts composing inpt 3 of Integrator 1 is eqal to Z" d: Z"d ( z' Z 1-2 L ) = - -+---- yf3r-cos cp d Z D. The change in the heading angle d'l! is derived by Integrators 3, 1, and 8 in that order according to Eq. (4). The y component of the range is obtained by Integrators 6, 7, 9, and 11 where the soltion R y is in Integrator 11. The x component of the range is obtained by Integrators 6, 7, 10, and 12 where the soltion Rx is in Integrator 12. The DDA for solving Chapman's eqation cold not be scaled to achieve the accracy and soltion time reqirements withot introdcing the techniqe of atomatic rescaling. For a skipping trajectory the vale of Z may vary from 0.0001 to 10. In trn, the vale of liz in Integrator 6 will vary from 0.1 to 10,000. Becase the DDA ses fixed point arithmetic, the large range of 1Z reqires an extremely small independent increment ~. To obtain an accracy of three decimal places, an_ increment size of 10-8 was necessary. Since varies from 0 to 1, ~ = 10-8 is eqivalent to 10 8 iterations. The nmber of iterations is directly proportional to the soltion time. The desired accracy and soltion time were ob.;. tained by applying the techniqe of atomatic rescaling. Instead of sing one scale for the complete range of liz, we divided it into for scales: A, B, C, and D. The table below shows the range of liz, vale of ~, and nmber of iterations for each scale. The accracy for each scale is approximately the same. The following sketch shows a typical plot of Z verss for a skipping trajectory. From the sketch, Scales A and B are sed dring most of the integration, and Scales C and D are sed less than 10 percent of the time. Therefore, the average ~ is abot 10-6 The se of mltiple scales has redced the nmber of iterations, and conseqently the soltion time, by a factor of 100. Scale Range of 1 I Z A 0.1 ~ liz < 10 B 10 ~ liz < 100 C 100 ~ liz < 1000 D 1000 ~ liz < 10,000 ~ 10-5 10-6 10-7 10-8 Nmber of Iterations 1 z : ---- A test of the accracy for different ~ sizes was made sing a simlation program. Figre 3 shows the reslts of solving Chapman's eqation with the same initial conditions bt with different sizes of ~. The three solid crves are the soltions for ~ = 10-4, ~ = 10-5, and ~ = 10-6 A compter program at the Martin Company, for solving differential eqations, entitled Unitrac was sed to compte an accrate soltion represented by the dotted crve for means of comparison. The crve for ~ = 10-6 more closely follows the dotted crve than the crve for ~ = 10-5, demonstrating that an increase in accracy reslts as the independent increment size decreases. DDA DESIGN FOR DEMONSTRATION PROBLEM, xy" + 2..-y' + Y = 0 2 To demonstrate the principles of the new techniqes we have designed and bilt a special prpose d 2 y 1 dy DDA to solve x dx 2 + 2 dx + Y = O. ConseqentlY' we did the detailed logic design needed to incorporate atomatic rescaling, asynchronos timing and shared integrators into a DDA. d 2 1 d 2 dx The general soltion to x d ~ + -~ + Y = 0 is y = A cos (2yx) + B sin (2yx) where A and B are arbitrary constants. If the initial conditions are y = 100 and ~~ x = a at x = a

DESIGN OF A HIGH SPEED DDA 937 then the particlar soltion is y = 100 cos (2yx) for which a graph is shown in Fig. 4. We confined or interest to compting the soltion y = 100 cos 91T (2yx) from x = 0 to x = 4,althogh other soltions cold be compted by changing the initial conditions. d 2 y 1 dy The DDA hookp sed to solve x dx2 + 2 dx + Y = 0 is shown in Fig. 5. The box with dx inside generates the independent increment which starts each iteration. The figres labeled IT, 2T, and 3T are conters for the prpose of scaling and will be explained later. The triangles labeled 11, 21, and 31 are the integrators storing _1_, dd y and y, respecx x tively. The lower inpt is the differential of the variable being stored. The otpt is the prodct of the pper inpt and the variable being stored. Integrator 11 is a shared integrator having one Y register and three R registers labeled R 1, R2, and Ra. Inpt 1 to Integrator 11, dx, cases Y to be accmlated in register R 1. The overflow from Rl, dx,becomes inpt 2. Inpt 2 cases Y to be accx mlated in Register R2. The sign of the overflow from R2 is switched; the reslt - d! is eqal to x 1 d and hence becomes the lower inpt to 11. x Inpt 3 which comes from Conter 2T is eqal to 1_ dy dx and inpt 4 which comes from 2 dx ' Integrator 31 is eqal to - y dx. Both inpts 3 and 4 reslt in Y being accmlated in Register Ra. So it is possible for Y to be added to Ra twice in the same iteration if both 31 and 2T overflow. Mltiplying the eqation x ~~ + ; ~~ + Y = 0 by dx, it is clear that the sm of inpts 3 and 4 is eqal to d 2 y X dx 2 dx. Therefore the overflow from Ra is 1;; dx which eqals d (7x) by identity. The next phase is the scaling which determines the increment size corresponding to each inpt and otpt plse and the nmber of bits in each register. To demonstrate the techniqe of atomatic rescaling, we sed two scales. Scale A is for the range from x = 0 to x = 16, and scale B is for the remaining Chapman's eqation 1 ---Exact soltion -DDAsoltion ~L.l--------~--------~-------'~-- U_ Fig. 3. Increase in Accra.ey as the Size of the Independent Variable Increment 1s Decreased (or as the Nmber of Iterations 1s Increased) for a DDA Solving Chnpnan's Eqation Figre 3. Increase in accracy as the size of the independent variable increment is decreased (or as the nmber of iterations is increased) for a DDA solving chapman) eqation. Figre 4. Soltion of XY" + -} y' + y = 0

938 PROCEEDINGS -FALL JOINT COMPUTER CONFERENCE, 1965 Scale B A dx Scale B A dx dx dx dx 2 0 IT o 1 3T Scale B A 1 "2 dy dy = (~) dx 3 1 2T -y dx range from x = 16 to x = ( 9 4 11" ) 2. d 2 y 1 dy FIgre 5. DDA to solve x dx2 + 2 dx + y = 0 The absolte maximms of ~, :: ' and y pls the scaling +.. coefficients for scale A and scale B are given in Fig. 6. For example, a 5 on a line wold indicate that the weight of the variable increment at that point eqals is or it takes 2s plses to eqal one nit of the variable. The position of the binary point in any register can be determined by the nmber inside the triangle. The following sketch shows the sign convention. The scaling coefficients were prposely chosen so that th length of each register was 7 bits for Scale A and Scale B. The conters, IT, 2T, and 3 T, in Scales A and B are sed to decrease the scaling coefficients so that they satisfy the scaling eqations. We also employed asynchronos timing in the compter. No frther explanation of asynchronos timing is needed here. Another problem not mentioned so far is seqencing, which is related to the timing. While Integrator 1 I is processing inpt 2, it is possible for inpts 3 ~ and 4 to arrive. The integrator mst process each inpt one at a time in series. To solve this problem, the integrator has been designed to store any inpt plse which arrives while the integrator is integrat-

DESIGN OF A HIGH SPEED DDA 939 2 ( JL) < x < 24 4 - - dx 3T Scale A 2T 2 24 < x «91T) - - 4 IT dx Scale B 3 5 5 5 2T o -2 I ~I = 1-100 /x sin (2{X) I < 2 5 Figre 6. Scale A and B for demonstration DDA.

940 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 ing. When the integrator is finished, it will act pon the stored inpt plse. The seqencing problem is best illstrated by examining the plse paths. Referring to the Seqencing Chart (Fig. 7) there are three basic time zones after a AX generator starts the iteration cycle. In zone A, Integrators 11, 21 and 31 do a AX cycle (triangles labeled 1, 4 and 8) and there is no possibility of an integrator time conflict. In zone B, however, there are three plse paths where Integrator 11 can be actated in a AX cycle; they are plse path 1 (triangle 2), plse path 2 (triangle 5) and plse path 4 (triangle 9). In the worst case, if all integrators in time zone A overflow, then all three reqests for 11 in time zone B mst be honored. This is done by seqencing the 1 I AX reqests on a first come, first served basis. There is also a time conflict in time zone C with Integrator 21, plse path 2 (tri- Plse path 1 Plse path 2 Plse path 3 Plse path 4 i I : I 1!---Time zone_--l-_time zone_~_time zone---j : ABC : 1 Start of iteration cycle I Figre 7. AX generator seqencing chart. angle 6) and plse path 4 (triangle 10). The worst possible series path of integrators is.9---. shown below: 1 3 4.6.10 8 The worst path is for AX cycles and one A Y cycle. They are Integrators 1, 2, 5, 9 and 3. The other integrators, Nos. 4, 7, 6, 10 and 8, are processed in parallel and take no added time. For example, while Integrator 1 is processing, Integrators 4 and 8 are also processing. In this description of the plse paths and parallel processing we have ignored the

DESIGN OF A HIGH SPEED DDA 941 inflence of the IT, 2T and 3T conters. The most they can do, however, is decrease the occrrence of the worst case series path. At the completion of all the plse paths, the ~X generator starts the next cycle. Since the longest path is five integrators (which occrs infreqently) and the shortest is one (which occrs freqently), this techniqe of asynchronos timing reslts on the average in a great time saving. Test data obtained from the demonstration compter indicates the nmber of iterations per second to be in excess of 2 million. LOGIC DETAILS OF DEMONSTRATION DDA The logic of the demonstration DDA to solve 1 xy" + - 2 + Y = 0 can be divided into three sec- tions: Integrators, Conters and Master Timing Control. Integrators There are two types of integrators, shared (11) and normal (21 and 31) both of which se the normal rectanglar integrator techniqe. To ease the description, we will describe the less complicated normal integrator and note the differences of the shared integrator where appropriate. The integrators are divided into two sections: (a) Register and Adder, and (b) Timing and Control. Carry I I Q Adder y R Figre 8. Registers and adder interconnection.

942 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 Registers and adder. The fnctions of the Y and R registers are as normally sed in a DDA (see reference 7 for fll description of DDA integrators). There is also a 0 register which is sed as a temporary storage from the adder. The block diagram of the registers and adder is shown in Fig. 8. The possible register-to-adder transfers are (In the case of a shared integrator, 0 transfers to R 1, R2, or Rs depending on which AX is in operation. ) Both the Rand 0 are 7 bit nsigned registers and the Y register is 7 bits pls sign. Sbtraction is performed by a modified 1 's complement addition pls some sign control and zero detection. The Y and Q registers can transfer ot their tre vale (Y T or OT) or their 1 'scomplement vale (Y c or Oc). The total algorithm for they, Rand 0 registers to the adder is given in Table 1. The symbols sed in the table are: Y M == Y register magnitde Y s == Y register sign Y T == Y register tre vale y c == Y register 1 's complement vale C == overflow carry-ot of adder C == no overflow carry-ot of adder ~ == transfers to DN == do nothing == yields Let's look at an example (line 4): Sppose the integrator is in the condition Y M =I=- 0 (the contents of Y register are not eqal to zero), Y M =I=- MAX (the contents of Y register are not eqal to all ones or the maximm vale) and Y s = - (the sign of Y register is negative). If the inpt to the integrator is a AX + cycle (colmn 1), then from the table it can be seen that: the 1's complement vale of Y is added to the vale of R and the reslt stored in 0 (Y c + R ~ 0). Then the tre vale of 0 is transferred back to R (QT ~ R). If an overflow carry from adder position 7 did not exist, then the integrator signals a mins (~X -) otpt (C -OUT PUT) to the next integrator. In addition to the normal fnctions of the registers and adder, they are also sed to accomplish the rescale fnction. The rescale is really only a shift left of the contents of the Y register. Rather than pt in the shift hardware and set p a special timing seqence it was fond to be cheaper and faster to se the adder. This is done by adding a 0 to the contents of Y (which is only a trick to get the otpt of the adder to contain Y) and transferring the adder otpt to the shifted rather than the normal position of Q. For example, in Integrator 21, the otpt of So (the zero stage of the adder) is sent to 04, Sl to 05 and S2 to 06. All lower stages of Q, that is 00, 01, 02 and Os are filled with O's. This reslts in a shift left 4 of the Y register. The adder network is a flly parallel 6 delay carry look-ahead adder. (For more details on adders, see references 4, 5 and 6.) In brief this adder is made ripple free becase each stage "looks ahead" to the inpt of all previos stages to determine whether a carry-in will exist. This techniqe, althogh extravagant in hardware, is the fastest method for binary addition. In passing, it shold be noted that this adder cold have been made 1 delay faster (from 6 delays maximm to 5 delays maximm), bt the amont of hardware wold have been approximately dobled. The gate delays in the microelectronics we are sing reslt in an add time of 50 to 90 nanoseconds. Timing and Control Each integrator is reqired to perform two types of operations: a ~X cycle, where Y is accmlated to R and a A Y cycle, where Y is incremented or decremented by 1. Control flip-flops in each integrator store the present stats of the integrator as well as the inpt commands (AX or AY). Another series of control flip-flops store the action to be taken by the integrator, based on the decoding of the inpt comm~nds and the present stats. See Table 1 for the combinations of inpt commands, present condition of integrator and decoded commands. The inpt commands are also sed to initiate the timing chain. No clocks exist in the timing chain, or anywhere in the machine. Rather, the timing and control is designed so that each integrator only operates on command and will process commands according to a priority seqence as shown in the following tablation.

DESIGN OF A mgh SPEED DDA 943 TABLE 1 Algorithm for Registers and Adder Condition of Integrator ax + YM = 0; Ys = + DN DN Inpt to Integrator ax ay ay + YM = 0; Ys =- DN DN Y M =F,O; Y s = + YM=FMAX YM=FO;Y S = YM=FMAX Y s = + YM = MAX Y s = Y M = MAX YT + R~Q Yc + R~Q Y c + 1 ~ Q QT~R QT~R C + OUTPUT C -OUTPUT Yc + R~Q YT + R~Q Y c + 1 ~ Q QT~R QT~R C -OUTPUT C + OUTPUT Qc~Y Qc~Y YT + R~Q Yc + R~Q 1 OVERFLOW Yc + 1 ~ Q QT~R QT~R C + OUTPUT C -OUTPUT Yc + R~Q YT + R~Q Y c + 1 ~ Q QT~ R QT~R C -OUTPUT C + OUTPUT Qc~Y Qc~Y OVERFLOW 1. If a IJ.X command occrs, and a Y is not active, process ax. 2. If a IJ.X command occrs and IJ. Y is active, then store ax command. 3. If a IJ.X command is in storage and A Y goes inactive, then process AX and reset IJ.X storage. 4. If a ax and A Y command occr at the same time, process AX and store A Y. 5. If a A Y command is in storage and ax goes inactive, then process A Y and reset A Y storage. Notice that in line 4, preference is given to AX commands since only they can case an otpt from the integrator. In this way, if there is to be an otpt, the next integrator is started processing sooner than if the A Y (which never has an otpt) were processed first. Each of the ax and A Y command and storage flip-flops from each integrator is also decoded in the Master Timing and Control Section. When all flip-flops are zero, which indicates that no integrator is processing or has anything to be processed, the next AX generator or next iteration cycle is started - which is asynchronos timing. Conters The DDA contains three conters, IT, 2T and 3T. Conters IT and 3T are simple decoding conters of 2 bits and 1 bit, respectively, and 2T is a 4- bit doble-rank forward and reverse shift conter. In e~ch of the conters, since we cannot afford to wait for ripple time, a simple expediency is sed. When a conter is one cont below its otpt vale the next cont command will trigger the otpt even thogh the conter never really increments (or decrements). For example, sppose the conter was designed to overflow or otpt at a vale of 16, when it reaches 15 the next cont command triggers the otpt and resets the conter. In this way, the compter does not have to wait for the conter to increment bt only for the time it takes the simple conter control to trigger. It might appear that, since the conter ripple time has been bypassed as a problem, we cold have sed the simplest ripple conter, bt this does

944 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 not work ot. It is tre that. the conter time is important only in as mch as it finishes its conting before the next cont command is received. Under certain conditions in the DDA, the cont commands cold be very close together so the faster shift conter was reqired. In order to avoid the annoying typical conter problems of two types of zero (pls and mins) and sign control, a simple expediency was sed of making the conter one stage too big and resetting to the middle vale. For example, if we want to cont from 0 to + 7 and 0 to - 7, we make the conter 4 bits (instead of 3) and cont from 8 p to 15 and 8 down to 1. The hardware difference between the two techniqes is so small as to be nimportant. Master Timing and Control (MT&C) The Master Timing and Control is made p of a series of hosekeeping and control fnctions which belong to the whole DDA rather than anyone integrator. They are: (1) AX Generator, (2) Falt detection, (3) Rescale, and (4) Psh btton starter. ~ Generator (~ Gen). This flip-flop receives the otpt and stats of all integrators to sense when they have completed their last operation and are waiting for another cycle. When this "nothing else to do" condition exists, the AX Generator initiates the start of the next iteration cycle. This scheme takes the place of a clock which wold rn the DDA at fixed clock periods and wold have to be timed for the worst case plse path or slowest possible cycle. By the very natre of a DDA not every iteration cycle will, and in fact many will not, have overflows from some integrators. Falt detection. Certain conditions of the Y decode logic of each integrator are considered as a falt. These conditions, when they occr, are stored in flip-flops in the MT&C and the machine will stop or ignore these falts depending on a switch setting on the operator's console. The falt conditions are: 11 Y register = o. 21 Y register> 27-1 = overflow. 3 I Y register > 2 7-1 = overflow. Rescale. Two flip-flops are sed to store the rescale conditions of 11 and 2I. When both conditions occr, the next AX Generator cycle is replaced by a rescale cycle which resets the initial conditions into the integrators and conters, and at the same time shifts left or right the contents of Y register in 11 and 2I. This shifting is done by sing the adder network. At the completion of the rescale cycle, the next AX Generator cycle is initiated and the DDA starts its normal operation. Psh btton starter. This is simply a means of filtering ot the "Single-Cycle" psh btton noise when the DDA is operated in the "Step" mode. In the "Step" mode, the psh btton intiates the AX Gen cycles so that the machine iterates on command. HARDWARE DESCRIPTION OF DEMONSTRATION DDA In the development phase of the DOA program it was nnecessary, and in fact brdensome, to package the compter for an aerospace environment. On the other hand, a "breadboard" package often trns ot to mean "slapped together." Neither of these extremes was desirable and the reslt of this program is what we call a laboratory model. For the logic hardware, it was advantageos to se aerospace approved circits. In this way, the laboratry model wold have speed and noise characteristics approximating those of a final packaged version. The logic chosen was the Fairchild commercial integrated circits. The front and back views of the resltant laboratory model are shown in Figs. 9 and 10. The chassis measres 23" X 20" X 5" (exclsive of the operator's console) and can accommodate 100 logic cards of the type shown in Fig. 11. The connectors are 86 pin AMP tab-wired and reqire no soldering. Tbe recessed tabs preclde wire shorting and also allow easy removal. Connector power (+ 4 v and gron~) is tapped-off the bs bar with all gronds isolated from the chassis and broght back to a central point. The logic cards measre 41;2" X 2" and each contains twelve 8-pin, TO-5 header microelectronic logic elements. The only interconnections made on the printed circit cards are the power bssing. The remaining logic interconnections ~re made on the wiring backpan (this is often referred to as "backpan logic"). This techniqe allows greater flexibility and ease of modification, and the logic partitioning is mch easier since it can be done at a mch later date in the design. There is also a significant cost saving in only reqiring one printed circit design. The photographs in Figs. 9 and 10 were taken

DESIGN OF A HIGH SPEED DDA Figre 9. Front view of DDA. Figre 10. Back view of DDA.

946 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 Figre 11 dring the compter checkot which acconts for aerospace applications over the pre general prthe chassis sitting vertically with the operator's con- pose (GP) approach. In brief, two very attractive sole temporarily monted on top.. applications for the high speed DDA are evident, In Fig. 11, the lower card is a normal 12-element (a) as part of a GP-DDA hybrid which wold allogic card. The pper card is also a logic card bt leviate the loading of the GP compter for aerowith the addition of capacitors and trimpots for space applications and ( b ) as the real time comsingle shots. The middle card shows the reverse side pter for a strap down inertial gidance system. A of all cards. frther detailed comparisn is necessary to jstify the merits and economics of this approach, bt we The demonstration DDA to solve xy" + {- y' do feel that the vastly disproportionate design time + Y = 0, contains 94 cards, each with 12 elements, for a total of 1200 TO-5 cans (approximately attempt at eqal design time for the DDA before given to the GP machines reqires at least some 1900 logic elements). Redesigned for aerospace, and the final comparison can be made. Potentially, the sing the conservative estimate of 17,000 flat-packs DDA can iterate a differential eqation faster since per cbic foot, the machine cold be packaged in a the GP wastes some time doing hosekeeping and volme of 0.07 ft3 and weigh approximately 3.6 memory transfer instrctions, e.g., transfers to and ponds. from memory, and indexing. In contemporary DDA's this potential has generally not been realized CONCLUDING REMARKS for two reasons; ( a ) most of the DDA's bilt have been serial machines, and ( b ) the DDA ses a The se of digital differential analyzers (DDA), fixed independent variable increment while most of becase of their great speed in solving differential the more sophisticated GP programs for solving differential eqations se a variable eqations, appears to offer a promising ftre in increment.

DESIGN OF A HIGH SPEED DDA 947 ACKNOWLEDGMENT The athor wishes to express his apprieciation to Mr. M. F. Htton of the Martin Company who contribted significantly to the details of this program. REFERENCES 1. D. R. Chapman, "An Approximate Analytical Method for Stdying Entry Into Planetary Atmospheres," NACA TN 4276, 1958. 2. R. C. Wingrove and R. E. Coate, "Piloted Simlator Tests of a Gidance System Which Can Continosly Predict Landing Point of a Low LID Vehicle Dring Atmosphere Re-entry," NASA TN D-787. 3. A. Gill, "Systematic Scaling for Digital Differential Analyzers," IRE PGEC, pp. 486-489, (Dec. 1959). 4. I. Flores, The Logic of Compter Arithmetic, Prentice-Hall, Inc., 1963. 5. R. S. Ledley, Digital Compter and Control Engineering, McGraw-Hill Book Co., p. 257. 6. R. K. Richards, Arithmetic Operations in Digital Compters, D. Van Nostrand Co., p. 303. 7. Hskey and Korn, Compter Handbook, Sect. 19 on DDA's, Mc-Graw-Hill Book Co. (1962). BIBLIOGRAPHY 1. "An Air-To-Srface Missile Gidance High Speed Digital Differential Analyzer," Final Report Contract No. AF33(600)-31315, WADC TR-59-651, IBM Fed. Sys. Division (Jan. 1960). 2. C. G. Blanyer and H. Mori, "Analog Digital and Combined Analog-Digital Compters for Real Time Simlation," Proc. Eastern Joint Compo Conf., Washington, D. C., Dec. 9 to 13, 1957, pp. 104-110. I 3. R. E. Bradley and J. F. Genna, "Design of a One-Megacycle Iteration Rate DDA," Prog. SJCC AFIPS, 1962. 4. E. L. Bran, "Brief Introdction to the DDA Compter," Compters in Control, AlEE Control Compo Session, 1960 to 1961, pp. 80 to 86. 5. E. L. Bran, "A Comparison of Integral and Incremental Digital Compters for Process Control Applications," Control Engineering, pp. 113-118 (Jan. 1960). 6. E. L. Bran, "Design Featres of Crrent DDA's," IRE Convention Record, Part 4, N. Y., pp. 87-97, 1954. 7. E. L. Bran and G. Post, "Systems Considerations for Compters in Process Control," IRE National Conv. Record, Part 4, pp. 168 to 181, 1958. 8. V. Bsh, "The Differential Analyzer," Jornalof Franklin Institte, Vol. 212 (1931). 9. "Compters in Control," AlEE Pb. S-132 (Sept. 1961). 10. J. M. Crank, The Differential Analyzer, Green and Company, Ltd., London, 1947. 11. F. G. Crl, "A Comparison of Compters," Compters in Control, 1960 to 1961, AlEE Control Compter Sessions, pp 87-96. 12. "DDA," pblished by G. Forbes. 13. M. M. Dickinson, "A Comparison of DDA & GP Eqipment in Gidance Systems," Compters in Control, 1960 to 1961, AlEE Control Compter Sessions, pp. 208-210. 14. "The Digitac Airborne Control System Trends in Compters: Atomatic Control and Data Processing S-59," Proceeding Western Joint Compo Conf., Los Angeles, Feb. 11 and 12, 1954, pp. 38-44. 15. J. F. Donan, "The Serial Memory DDA," Math. Tables and Other Aids to Comp., Vol. 6, No. 38, April 1952, pp. 102-112. 16. C. F. Edge, _ "Digital Differential Analyzers Verss General Prpose Digital Compters for Schler-Tned Inertial Navigation Systems," IEEE Trans. on Military Elec., Vol. MIL-7, pp. 23-29, Jan. 1963. 17. E. E. Grabbe, Handbook of Atomation, Comptation and Control, Vol. 2, Compters and Data Processing, Wiley, 1959. 18. D. R. Hartree, Calclating Instrments and Machines, University of Illinois Press, Urbana, Ill., 1949 19. F. B. Hills, "A Stdy of Incremental Comptation By Difference Eqations," MIT Servomech -anisms Lab., Rept. No. 7849-R-1 (May 1958). 20. E. G. Homer and W. Palmer, "Comparison of Comptational Speeds of Digital Differential Analyzers and General Prpose Compters," lee PGEC, Jne 1964, p. 307 (correspondence). 21. H. K. Kndsen, "The Scaling of Digital Differential Analyzers," IEEE Trans. on Electronic Compters, Vol. EC-14, pp. 583-589, Ag. 1965. 22. R. D. Lamson, "A Division Algorithm for a

948 PROCEEDINGS - FALL JOINT COMPUTER CONFERENCE, 1965 Digital Differential Analyzer," IEEE PGEC, Feb. 1964, pp. 54-55. 23. F. Lesh, "Methods of Simlating a Differential Analyzer on a Digital Compter," J. Assoc. of Compo Machinery, Vol. 5, Jly 1958, pp. 281-288. 24. "Maddida-DDA," Brochre No. 38, Northrop Aircraft, Inc. (Dec. 1950). 25~ H. E. Marer, "An Approximate Analysis of Error Propagation in a DDA," MIT Inst. Lab., Martin Company, MR-6140-A44 (March 1958). 26. H. E. Marer, "Error Analysis of a DDA," MIT Inst. Lab., Martin Company, MR-6140-A-17 (May 1957). 27. M. J. Mendelson, "The Decimal Digital Differential Analyzer," Aeronatical Engineering Review, Vol. 13, pp. 42-54, (Feb. 1954). 28. K. Millington, "An Experimental Incremental Compter," J. Brit. IRE, Vol. 25, pp. 461-473 (May 1963). 29. L. M. Milne-Thompson, Calcls of Finite Differences, Oxford Press. 30. L. P. Mssner, "Real-Time DDA (DART) Trends in Compters: Atomatic Control and Data Processing S-59," Proc. Western Joint Compo Conf., Los Angeles, Feb. 11 and 12, 1954, pp. 134-139. 31. D. J. Nelson, "DDA Error Analysis Using Sampled Data Techniqes," AFIPS SJCC, 1962, pp. 365-376. 32. P. L. Owen, M. F. Partridge and T. R. H. Sizer, "Cosair, A Ditital Differential Analyzer," Royal Aircraft Establishment, England, TN lap 1123; "The Use of Direct Copled Logic in the Design of an Arithmetic Unit (for a DDA)," Electronic Engrg., Vol. 34, pp. 540-545, Ag.; pp. 619-623, Sept. 1962; "A Transistor Digital Differential Analyzer," J. Brit. IRE, Vol. 22, pp. 83-96. (Ag. 1961). 33. M. Palensky, "The Design of the Bendix DDA," Proc. IRE 41, Oct. 1953, pp. 1352-1356. 34. M. Pavevsky and J. V. Howell, "Digital Differential Eqation Solver," Instr. and Control Sys., Vo. 36, pp. 118-121 (April 1963 ). 35. Z. Pawlak, "The Application of a Negative Base Nmber System to a Digital Differential Analyzer," Bll. L'Acad. Polonaise Sci., Ser. Sci. Tech., Vol. 8, pp. 149-150, (Feb. 1960). 36. R. Rtishaser, "Litton-20 DDA," Litton Indstries, 1955. 37. M. I. Schneider, "Logical Design of Integrators for Digital Differential Analyzers," MIT Instrmentation Lab., Rept. No. T-154 (May 1958). 38. R. G. Selfridge, "Coding a GP Digital Compter to Operate As a Differential Analyzer," Proc. Western Joint Compo Conf., Los Angeles, March 1 to 3, 1955, pp. 82-84. 39. G. T. Sendzk, "Reslts of Simlation Comparison of Control Compters," Compters in Control, AlEE Control Compter Sessions, 1960 to 1961, pp. 97-103. 40. G. T. Sendzk, "A Variable Increment Compter," Compters in Control, AlEE Control Compter Sessions, 1960 to 1961, pp. 112-120. 41. M. F. Sentovich, "Mechanization of SST Inertial Navigation Comptations in All-DDA Compter," 20th Annal National Meeting, Navigation, Atmn 1964, Vol. II, NVM 3, pp. 284-298. 42. S. M. Shackell and J. G. Tryon, "The Relative Merits of Incremental and Conventional Digital Compters in Air-Borne Real-Time Control," Compters in Control, AlEE Control Compter Sessions, 1960 to 1961, pp. 200-207. 43. C. E. Shannon, "Mathematical Theory of Differential Aalyzers," J. of Mathematical Physics, Vol. 4 (Dec. 1941). 44. D. E. Skabelnd, "The Nmerical Process of a Binary Differential Analyzer," University of Utah Report (Ag. 1953). 45. R. E. Sprage, "Fndamental Concepts of the DDA Method of Comptation," Math Tables and Other Aids to Compo (6), Jan. 1952, pp. 41-49. 49. 46. R. E. Sprage, "CRC-105 Compter," Aero Digest (67) pp. 48-55, (Ag. 1953). 47. R. H. Stotz, "Specialized Compter Eqipment for Generation and Display of Three Dimensional Crvilinear Figres," Contract AD33 (600)42859, Prof. DSR 8753, 154 pp., March 1963; U. S. Gov. Res. Rept., Vol. 38, p. 6 (A), September 20, 1963. AD 406 608 (OTS $12.00). 48. J. To, "Digital and Sampled-Data Control Systems," McGraw-Hill Book Co., 1959. 49. "The Trice-A High Speed Incremental Compter," IRE Nat. Conv. Record, 1958, Part 4. 50. O. C. Trtle, "Incremental Compter Error Analysis," IEEE Trans. on Commnication and Electronics," Vol. 82, pp. 492-495, Sept. 1963. 51. R. W. Waller and F. E. Brinckehoff, "A Comparison of Whole Vale and Incremental Digital Techniqes by the Use of Patch Panel Logic,"

DESIGN OF A HIGH SPEED DDA 949 Compters in Control, AlEE Control Compter Sessions, 1960 to 161, pp. 104-111. 52. C. J. Wayman, "The Airborne Digital Compter 'Dexan'," Interavaia, Vol. 16. pp. 1705-1706, (Dec. 1961). 54. E. Weiss, "Applications of CRC-105 Decimal DDA," IRE PGEC EC-1, Dec. 1952, pp. 19-24. 55. H. A. Whitted, "A High-Speed Rate Mltiplier for Data Display Systems, Navy Electronics Laboratory, Report 1174, p. 70 (Jly 1963). 56. D. J. Winslow, "Incremental Compters in Simlation," Meeting of Sotheast Simlation Concil, Hntsville, Ala., Oct. 1958.