CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits o The outputs depend on the current and past input values (i.e. present state). o It uses logic gates and storage elements. o Thus has a memory (usually called the state) stores intermediate and final data/results. o They are synchronized by a periodic clock signal. o Latches, flip-flops, state machines, counters, shift registers. o They are referred as finite state machines since they have a finite number of states. Example: Vending machine. Definition Circuits whose outputs depend not only on the present input value but also the past input value are known as sequential logic circuits. A general block diagram of a sequential circuit is shown below: The diagram consists of combinational circuit to which memory elements are connected to form a feedback path. The memory elements are devices capable of storing binary information within them. The combinational part of the circuit receives two sets of input signals: one is primary coming from the circuit environment and secondary coming from memory elements. The particular combination of secondary input variables at a given time is called the present state of the circuit. The secondary input variables are also known as the state variables. The block diagram shows that the external outputs in a sequential circuit are a function not only of external inputs but also of the present state of the memory elements. The next state of the memory elements is also a function of external inputs and the present state. Thus a sequential circuit is specified by a time sequence of inputs, outputs, and internal states. 1 P a g e

Block diagram Memory elements can store binary information. This information at any given time determines the state of the circuit at that time. The sequential circuit receives binary information from external inputs. These inputs, together with the present state of the storage elements, determine the binary value of the outputs. They also determine the condition for changing the state in the storage elements. A sequential circuit is specified by a time sequence of inputs, output, and internal states. Example1: Using a combinational circuit, we can add two numbers. But, there is no way of adding two numbers, then adding a third (a sequential operation); there is no way of remembering or storing information after inputs have been removed. To handle this, we need sequential logic capable of storing intermediate (and final) results. Example2: Consider the following circuit. Give its output when these pairs of inputs combinations are applied first C1 = (01, 00), then C2 = (11, 00). E1 E2 Internal variable Y Output = f(input, current state) S E1 E2 S 0 0 S 0 1 0 1 0 S 1 1 1 E1 E2 0 1 0 0 E1 E2 1 1 0 0 => S = 0 => S = 1 Different output, even that the input is 00 S(t+1) = f(e(t), Q(t)) Next state = g(input, current state) Q(t+1) = g(e(t), Q(t)) 2 P a g e

II. 1 Sequential Circuit Types There are two main types of sequential circuits: synchronous and asynchronous. Their classification depends on the timing of their signals. 1. Asynchronous sequential circuit The circuit behavior depends upon the input signals at any instant of time and the order in which the inputs change. In gate-type asynchronous systems, the storage elements consist of logic gates whose propagation delay provides the required storage. Thus, an asynchronous sequential circuit may be regarded as a combinational circuit with feedback. Because of the feedback among logic gates, an asynchronous sequential circuit may become unstable at times. 2. Synchronous sequential circuit The circuit behavior can be determined from the knowledge of its signals at discrete instants of time. It employs signals that affect the storage elements only at discrete instants of time. Synchronization is achieved by a timing device called a clock generator that provides a periodic train of clock pulses. Clock pulses are distributed throughout the system in such a way that storage elements only with the arrival of each pulse. In practice, the clock pulses are applied with other signals that specify the required change in the storage elements. Circuits that use clock pulses in the inputs of storage elements are called clocked sequential circuits. The storage elements used in these circuits are called flipflops. A flip-flop is a binary storage device capable of storing one bit of information. The clock emits a series of pulses with a precise pulse width and precise interval between consecutive pulses. Timing interval between the corresponding edges of two consecutive pulses is known as the clock cycle time, or period. Definition: Synchronous sequential circuits change their states and output values at discrete instants of time, which are specified by the rising and falling edge of a free-running clock signal. The clock signal is generally some form of square wave as shown in the figure below. 3 P a g e

From the diagram you can see that the clock period is the time between successive transitions in the same direction, that is, between two rising or two falling edges. State transitions in synchronous sequential circuits are made to take place at times when the clock is making a transition from 0 to 1 (rising edge) or from 1 to 0 (falling edge). Between successive clock pulses there is no change in the information stored in memory. The clock width is defined as the time during which the value of the clock signal is equal to 1. A clock signal is said to be active high if the state changes occur at the clock s rising edge or during the clock width. Otherwise, the clock is said to be active low. Synchronous sequential circuits are also known as clocked sequential circuits. II.2 Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. Latch Single-bit storage (memory) When it is enabled, its content changes immediately when its inputs change. Changes state at any time due to input change. Latches are based on combinational gates (e.g. NAND, NOR) Latches store data even after data input has been removed. The most basic circuit from which all the flip-flops are constructed. Although latches are useful for storing binary information and for the design of asynchronous sequential circuits. They are not practical for use in synchronous sequential circuits. Flip-flop Also single-bit storage (memory). Its content changes only either at the rising or falling edge of the enable signal which is usually the controlling clock signal. The flip-flop content remains constant even if the input changes, after the rising or falling edge of the clock. 4 P a g e

There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major differences in these flip-flop types are the number of inputs they have and how they change state. For each type, there are also different variations that enhance their operations. II.3 Types of latches and flip-flops Latches o SR Latch / RS Latch o SRC Latch / SR Latch with Enable / SR Latch with control input o D Latch Flip-flops o D Flip-flop / Edge-Triggered D Flip-flop o D Flip-flop with Enable o SR Flip-flop / Edge-Triggered SR Flip-flop o JK Flip-flop / Edge-Triggered JK Flip-flop o T Flip-flop Bitstable Element The simplest sequential circuit or storage element or one bit memory is called a bitstable i.e. it has 2 internal states. Latches and flip-flops are particular implementations of bitsables. The bitstable is constructed with two inverters connected sequentially in a loop as show in the figure below. It has no inputs and two outputs labeled Q and Q. Since the circuit has no inputs, we cannot change the values of Q and Q. However, Q will take on whatever value it happens to be when the circuit is first powered. Assume that Q = 0 when we switch on the power => Q = 1. 1 0 0 1 0 1 SR Latch S for Set and R for Reset. The SR latch adds two inputs to the bitstable and replaces the two inverters with two NAND gates (see figure a below). The RS latch replaces the two inverters with two NOR gates (see figure b below). The SR latch made of cross-coupled NANDs sometimes called S R latch can be in one of two states: 5 P a g e 1 0

a set state when Q = 1 or a reset state when Q = 0 SR latch using NAND gates CIRCUIT USING NAND GATES CIRCUIT USING NAND GATES S R S R Q Qnext Qnext 0 0 1 1 Previous state No change (last state) 0 1 1 0 x 0 1 RESET 1 0 0 1 x 1 0 SET 1 1 0 0 x Illegal INVALID TRUTH TABLE LOGICAL SYMBOL LOGICAL SYMBOL TIMING DIAGRAM SR latch using NOR gates S R Q Qnext Qnext 0 0 Previous state No change 0 1 x 0 1 RESET 1 0 x 1 0 SET 1 1 x Forbidden? LOGICAL SYMBOL CIRCUIT USING NOR GATES 6 P a g e

SR Latch with control input / Enable input Occasionally, it is desirable to avoid latch changes. C=0 disables all latch changes. The control signal enables data changes when C = 1. Right side of circuit is same as ordinary SR latch. SR latch with Control Input with NOR gates D Latch (D = Data) One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. D latch has two inputs: D ( Data): directly goes to the S input and its complement is applied to the R input C (Control) input D latch is a Data latch. It is a copy latch, the output copies the Input D. If E = 0 then Q(t+1) = Q(t) If E = 1 then Q(t+1) = D(t) LOGICAL SYMBOL 7 P a g e

The D latch has an ability to hold data in its internal storage. It is suited for use as a temporary storage for binary information. This circuit is often called transparent latch: the output follows changes in the data input as long as the control input is enabled. Input value D is passed to the output Q when C is high. Input value D is ignored when C is low. The D latch stores data indefinitely, regardless of input D values, if C = 0. It forms basic storage element in computers. 8 P a g e

Symbols for latches SR latch is based on NOR gates, S R is based on NAND gates, and D latch be based on either. Note: The control input changes the state of a latch or a flip-flop. The momentary change is called a trigger. Example: D latch is triggered every time the pulse goes to the logic level 1. As long as the pulse remains at the logic level 1, the change in the data (D) directly affects the outputs. THIS MAY BE A BIG PROBLEM since the state of a latch may keep changing depending on the input (may be coming from a combinational network). To solve this problem, use a flip-flop, trigger the flip-flop only during a control signal transition. FLIP-FLOPS Flip-flops are constructed in such a way to make D latches operate properly when they are part of a sequential circuit that employs a common clock. The problem with the latch is that is responds to a change in the level of a clock pulse. Positive level response in the control input allows changes in the output when the D input changes while the control pulse stays at logic 1. The key to the proper operation of a flip-flop is to trigger it only during a signal transition. 9 P a g e

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Reset latch Output latch Set latch 11 P a g e

In case of a positive-edge-triggered D flip-flop or a negative-edge-triggered D flip-flop: Q(t+1) = D(t) The D flip-flop plays a role of delaying the value of the input D. The most economical and efficient flip-flop constructed is the edge-triggered D flip-flop since it requires smallest number of gates. Other types of flip-flops can be constructed by using the D flip-flop and external logic gates which are JK flip-flops and T flipflops. There are three operations that can be performed with a flip-flop: set it to 1, Reset it to 0, and complements its output (0-> or 1->0). JK Flip-flop (J = S and K = R) D = J.Q + K.Q No change No change 12 P a g e

From the circuit shown in the figure above: Operation1: When J = 1 and K = 0, D = 1.Q + 1.Q = 1 => next clock edge sets the output to one. Operation2: When J = 0 and K = 1, D = 0.Q + 0.Q = 0 => next clock edge sets the output to zero. Operation3: When J = 1 and K = 1, D = 1.Q + 0.Q = Q => next clock edge complements the output. When J = 0 and K = 0, D = 0 => next clock edge the output is unchanged. D(t) = J.Q + K.Q Q(t+1) = D(t) = J.Q + K.Q T (toggle) Flip-flop This is a complementing flip-flop. A T flip-flop changes states on every clock tick. It can obtained either from a JK or a D flip-flop and a XOR gate. To build it from a JK flip-flop, we tie the inputs J and K together to the input T. It is useful for designing binary counters. No change Complement No change No change 13 P a g e

FIG1: T FLIP FLOP BUILT FROM JK FIG2: T FLIP FLOP BUILT FROM D In FIG1: when T = 0 then J = K = 0 => A clock edge does not affect the output. When T = 1 then J = K = 1 => A clock edge complements the output. In FIG2: When T = 0 then D = Q => No change in the input. When T = 1 then D = Q => output complements. 14 P a g e

Flip-flops with asynchronous inputs Some flip-flop have asynchronous inputs that are used to force the flip-flop to a particular state independent of clock. These are referred to as asynchronous sequential circuits. Asynchronous inputs are usually available for both latches and flip-flops, and they are used to either set or clear the storage element s content independent of the clock. The input that sets the flip-flop to 1 is called preset. The input that clears the flip-flop to 0 is called clear or direct reset. When power is on in a digital system, the state of the flip-flop is unknown. The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation. 15 P a g e

When Preset = 0 => Preset = 1 => the content of the storage elements is set to 1 immediately, and when Clear = 0 => Clear = 1 => the content of the storage element is set to 0 immediately. When Preset = 0 and Clear = 0 (i.e. Preset = 1 and Clear = 1) then the flip-flop changes its state based on the clock edge triggering (positive or negative). Pr Cl Q Q 0 0 INVALID 1 0 1 0 0 1 0 1 1 1 Flip-flop Flip-flop types There are basically four main types of flip-flops: SR, D, JK, and T. The major differences in these flip-flop types are in the number of the inputs they have and how they change state. Each type can have different variations such as active high or low inputs, whether they change state at the rising or falling edge of the clock signal, and whether they have asynchronous inputs or not. The flip-flops can be described fully and uniquely by its logic symbol, characteristic table, characteristic equation, state diagram, or excitation table, and are summarized in the figure below. 16 P a g e

The characteristic table: is just the truth table but usually written in short format. It answers the question of what is the next state given the inputs and the current state, and is used in the analysis of sequential circuits. The characteristic equation: is the functional Boolean function that is derived from the characteristic table. It formally describes the functional behavior of the flip-flop. Like the characteristic table, it specifies the flip-flop s next state as a function of its current state and inputs. This equation can be obtained from the truth table using the K-map. 17 P a g e

The state diagram is a graph that shows the flip-flop operations in terms of how it transitions from one state to another. The nodes are labeled with the states and the directed arcs are labeled with the input signals that cause the transition to go from one state to next. The excitation table gives the value of the flip-flop s inputs that are necessary to change the flip-flop s current state to the desired next state at the next active edge of the clock signal. It answers the question of what should the inputs be when given the current state that flip-flop is in and the next state that we want the flip-flop to go to. This table is used in the synthesis of sequential circuits. 18 P a g e

SR Flip-Flop We can replace the D latches in the D flip-flop with SR latches to get a master-slave SR flip-flop. Like SR latches, SR flip-flops are useful in control applications where we want to be able to set or reset the data bit. However, unlike SR latches, SR flip-flops change their content only at the active edge of the clock signal. Similar to SR latches, SR flip-flops can enter an undefined state when both inputs are 1 simultaneously. Logic symbols for flip-flops The logic or graphic symbol describes the flip-flop s inputs and outputs, the names given to these signals and whether they are active high or low. All the flip-flops have Q and Q as their outputs. All of them also have a clk input. The small triangle at the clock input indicates that the circuit is a flip-flop and so triggered by the edge of the clock signal; if there is a circle in front, then it is the falling edge, otherwise it is the rising of the clock signal. Without the small triangle, the circuit is a latch. In addition, the flip-flops have one or two more inputs that characterize the flip-flop and give it its name. 19 P a g e

Analysis of clocked sequential circuits The behavior of a clocked sequential circuits is determined from the inputs, the outputs, and the state of its flip-flops. The outputs and the next state are both a function of the inputs and the present state. The analysis of sequential circuits consists of obtaining a table or a diagram for the time sequence of inputs, outputs, internal states. It is also possible to write Boolean expression that describes the behavior of the sequential circuit. The behavior of a clocked sequential circuit can be described algebraically by means of state equations (transition equations). A state equation specifies the next state as a function of the present state and inputs. Example: 20 P a g e

State table The time sequence of inputs, outputs, and flip-flop can be enumerated in state table (transition table). In general, a sequential circuit with m flip-flops and n inputs needs 2 m+n rows in the state table. 21 P a g e

State diagram The information available in a state table can be represented graphically in the form of a state diagram. State is represented by a circle. Transition between states are indicated by directed lines connecting the circles. Design procedure The design of a clocked sequential circuits starts from a set of specifications and culminates in a logic diagram or a list of Boolean functions from which the logic diagram can be obtained. The design procedure consists of the following steps: 1. Derive a state diagram for the circuit from the word description 2. Reduce the number of states if necessary. 3. Assign binary values to the states. 4. Obtain the binary-coded state table. 5. Choose the type of flip-flops. 6. Derive the simplified flip-flop input equations and output equations. 7. Draw the logic diagram. 22 P a g e

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COUNTERS Counters are important components in computers: the increment or decrement by one in response to input. There are two main types of counters: 1. Asynchronous (ripple) counters 2. Synchronous counters In the ripple counters, flip-flop output serves as a source for triggering other flip-flops. Ripple counters triggered by initial Count Signal. In the synchronous counters, all flip-flops are triggered by a clock signal. Synchronous counters are more widely used in industry. Counter: a register that goes through a prescribed series of states. Binary counter: counter that follows a binary sequence. N bit binary counter counts in binary from 0 to 2 N-1. It requires N flip-flops. Applications: counters are used in watches, clocks, alarms, Web browser refresh. Asynchronous counter The simplest counter is the binary counter modulo 2. 24 P a g e

Asynchronous binary UP counter modulo 8 = 2 3 In general, for an asynchronous binary UP counter modulo N = 2 n, we connect n flip-flops. It is also called ripple counter since the carry ripples down the chain. If the counter is made of D flip-flops. The D input of every flip-flop takes the value of Q as input. The lower flip-flop is synchronized with the clock signal while the output of Q synchronizes the second flip-flop, the Q of the second synchronizes the third, and so on. If the counter is made of JK flip-flops. The J and K of every flip-flops take 1 as an input (i.e. J = K = 1). The lower flip-flop is synchronized with the clock signal while the output Q of a flip-synchronizes the next flip-flop as previously. If the counter is made of T flip-flops. The input of every T flip-flop takes 1 (i.e. T = 1) and the connection among the flip-flops is the same as previously. In case of a down counters, the inputs of the flip-flops remain the same, however we connect the output Q to synchronize the other flip-flops as shown below. 25 P a g e Asynchronous binary down counter modulo 8

There are three types of asynchronous counters: 1. Complete counter N = 2 n 2. Incomplete counter N 2 n, example: N = 10 3. Irregular counter, example: 0, 3, 4, 7, 0 In case of incomplete counter, we use the preset and clear inputs for every flip-flop. These will change the state when necessary. 2. Example about incomplete counter: Asynchronous incomplete UP counter modulo 6. The number of flip-flops required for this counter is 3. The transition state diagram (or simply state diagram) is as follows: 5 0 4 1 3 2 The transition state table is as follows: Q2 Q1 Q0 Q2 + Q1 + Q0 + Pri Cli 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 0 1 X X X X X X Cli = 1, Pri = (Q2 Q1 Q0 ) => Pri = (Q2 Q1 Q0 ). 26 P a g e

3. Example about Irregular asynchronous UP counter 0, 2, 3, 6, 0, 2, 3, 6, 0, Detect 7 & force to 0 7 0 Detect 1 & force to 2 1 6 Detect 4 & force to 6 4 3 2 Note: to force the counter to change its state to another specified state, we use its asynchronous inputs. The transition state table is as follows: Q2 Q1 Q0 Q2 + Q1 + Q0 + Pr2 Cl2 Pr1 Cl1 Pr0 Cl0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 0 1 Cl2 = 1, Pr2 = Q2Q1Q0 => Pr2 = (Q2Q1Q0) Pr1 =Pr2 = (Q2Q1Q0), Cl1 = Q2 Q1 Q0 + Q2Q1 Q0 => Cl1 = (Q2 Q1 Q0 + Q2Q1 Q0 ) Cl0 = 1, Pr0 = Q2 Q1 Q0 + Q2Q1Q0 => Pr0 = (Q2 Q1 Q0 + Q2Q1Q0) Synchronous counters: In these counters, all the flip-flops are synchronized with the clock signal at the same time i.e. they change their state together. To design these counters, we try to find the value of their inputs. To solve this problem, we use the excitation tables learned earlier. Input 0? Input 1? Input n-1? Input n? Flip-flop 0 Flip-flop 1 Flip-flop n-1 Flip-flop n CLK Q0 Q1 Qn-1 Qn 27 P a g e

To design a synchronous counter, we follow the next steps: 1. Determine the necessary number of flip-flops. 2. Establish the transition state table of the counter [Next State (Qi+) in function of present state (Qi)]. 3. Determine the expression of the inputs of the flip-flops in function of the present state Qi. 4. We draw the logic diagram for the counter. Example: Build a complete synchronous counter modulo 8 = 2 3 using D flip-flops 1. We need 3 D flip-flops 2. Use the excitation table to compute the transition table: Q2 Q1 Q0 Q2 + Q1 + Q0 + D2 D1 D0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 3. We use the K-maps to compute the expressions of D2, D1, and D0. D0 = Q0 Q2\Q1Q0 00 01 11 10 0 1 0 0 1 1 1 0 0 1 D1 = Q1 Q0 + Q1Q0 = Q0 (+) Q1 Q2\Q1Q0 00 01 11 10 0 0 1 0 1 1 0 1 0 1 D2 = Q2 Q1Q0 + Q2Q1 + Q0 Q2 = Q2 (Q1Q0) + Q2(Q1 + Q0 ) = Q2 (Q1Q0) + Q2(Q1Q0) = Q2 (+) Q1Q0 Q2\Q1Q0 00 01 11 10 0 0 0 1 0 1 1 1 0 1 28 P a g e

D0 D1 D2 CLK Q0 Q0 Q1 Q1 Q2 Q2 Example: Build an incomplete synchronous counter modulo 6 using JK flip-flops 1. We need 3 JK flip-flops 2. Use the excitation table to compute the transition table: Q2 Q1 Q0 Q2 + Q1 + Q0 + J2 K2 J1 K1 J0 K0 0 0 0 0 0 1 0 X 0 X 1 X 0 0 1 0 1 0 0 X 1 X X 1 0 1 0 0 1 1 0 X X 0 1 X 0 1 1 1 0 0 1 X X 1 X 1 1 0 0 1 0 1 X 0 0 X 1 X 1 0 1 0 0 0 X 1 0 X X 1 1 1 0 X X X 1 1 1 X X X 3. We use the K-maps to compute the expressions of J2, K2, J1, K1, J0, and K0. J2 = K2 = Q2 Q1Q0 + Q2Q1 Q0 = Q0 (Q1 (+) Q2) J1 = K1 = Q2 Q0 J0 = K0 = 1 Note: To design a down counter, we start from the last state and move toward the first state. Example: down counter modulo 6 => 5 - > 4 -> 3 - > 2 -> 1 -> 0 -> 5. For a complete down counter, the initial state of every flip is 1. 29 P a g e

Registers Multiple flip-flops can be combined to form a data register. A register can store information as binary words coded on n bits (called data store/ buffer register) or to perform storing and shifting on these words (called shift register). Shift registers allow data to be transported one bit at a time. Registers also allow for parallel transfer, many bits transferred at the same time. Shift registers can be used with adders to build arithmetic units. Remember that most digital hardware can be built from combination logic (and, or, invert) and flip-flops which are the basic components of most computers. Buffer register with parallel load The register is a group of flip-flops. Example, to build the buffer register i.e. used as a memory to store data, we can use D latches or flip-flops. The register will hold a word (nibble) of data. Loads occurs in parallel on clock transition. The Word (E1E2 En) is the word that we want to store in the flip-flops on the next clock positive edge triggering. We simply, connect the Ei to the input of the flip-flop Di. REGISTER WITH LOAD CONTROL 30 P a g e

Example: if we want to store 1011 in a buffer register, we use 4 D flip-flops and the input of each one of them is 1, 0, 1, and 1 consecutively since Q(t+1) = D(t). On positive edge triggering of the clock signal H, the state of the register will be (Q1Q2Q3Q4) =(1011). Shift register The flip-flops are connected, there is a cascade chain of flip-flops. Exclusively the flipflops can be used to build shift registers. Bits travel on clock edges. The function of this register is shifting to the right. Serial Input Serial Output Di = Qi-1 => E arrives at Qn after n positive edge triggerings of the clock signal H. Example of a register with parallel loading LOAD = 1, (EP1, EP2,, EPn) is loaded in the register. LOAD = 0, the register is in shifting mode. 31 P a g e

Main Memory (Register File Implementation) Example: Use 256 16-bit registers, multiplexer and decoder which are combinational circuits. 32 P a g e

EXERCISES Exercise1 Consider the following circuit made of D, T, and JK flip-flops: Give the timing diagram for Q0, T, Q1, J, K, and F signals assuming that the flip-flops and are initially 0. The CLK and X signals are given below: Exercise2 Consider the following sequential circuit: 2.1) Analyze the schema to find the logic equations for Q1 +, Q0 +, and F. 2.2) Give the state transition table with inputs Q1, Q0, and X, and three outputs Q1 +, Q0 +, and F. 33 P a g e

Exercise3 (asynchronous up counter) Design an asynchronous up counter using JK flip-flops (modulo 4) that generates the sequence in decimal 0, 1, 2, 3, 0 by answering the following questions: 3.1) How many JK flip-flops are required? 3.2) Draw the state transition diagram and the counter logic circuit. 3.3) Draw the timing diagram for this counter. Exercise4 (synchronous irregular up counter) Design an irregular synchronous up counter using JK flip-flops that generates the following sequence: 0 2 4 6 1 3 5 7 0 2 4 4.1) How many JK flip-flops are required? Draw the state transition diagram 4.3) Give the transition table (Present state, Next state, Inputs of flip-flops) 4.4) Simplify the input equations using K-maps and draw the counter logic circuit. Exercise5: Design a synchronous up counter modulo 8 using D flip-flops. Exercise6 (Asynchronous down counter) 6.1) Design an asynchronous count down counter modulo 4 using D flip-flops that are triggered on positive edge of the clock. 6.2) Answer the previous question using D flip-flops synchronized with clock triggered on negative edge. Exercise7 (Incomplete count down counter) 7.1) Design an asynchronous count down counter that counts from 6 to 2 using D flipflops. 7.2) Answer the previous question using synchronous counter. Exercise8 (Register) Design a shift right register to write serially the data 1001 in it, how many clock triggering is required. Same question but this time using parallel access. 34 P a g e

Exercise9 For a given S and R inputs to SR flip-flop, sketch the output signal Q. Exercise10 The input D to a positive-edge triggered flip-flop is shown. Find the output signal Q. Exercise 11 a) Derive the Boolean expressions for the inputs D0 and D1 of each flip-flop in the schematic in terms of external input Cnt and the flip-flop outputs Q1 and Q0. 35 P a g e

b) Derive the next-state equations by converting the previous equations into flip-flop characteristic equations. Then convert these equations into tabular form called the nextstate table. c) Derive the state diagram for the sequential circuit shown in the figure below. Exercise12 We wish to design a synchronous sequential circuit whose state diagram shown below. The type of flip-flop to be used is JK. a) From the state diagram, generate the state table. Present State Q0Q1 Next State x = 0 x = 1 b) Derive the excitation table of the circuit. Present State Q0Q1 Next State Q0Q1 Input x Flip-flop Inputs J0K0 J1K1 c) Derive the simplified flip-flop input functions using Karnaugh maps. Draw the logic diagram of the circuit. 36 P a g e