German Jordanian University. Department of Communication Engineering. Digital Communication Systems Lab. CME 313-Lab. Experiment 3.

Similar documents
Department of Communication Engineering Digital Communication Systems Lab CME 313-Lab

CPE 400L Computer Communication Laboratory. Laboratory Exercise #9 Baseband Digital Communication

PCM ENCODING PREPARATION... 2 PCM the PCM ENCODER module... 4

ECE 5765 Modern Communication Fall 2005, UMD Experiment 10: PRBS Messages, Eye Patterns & Noise Simulation using PRBS

BASE-LINE WANDER & LINE CODING

CONVOLUTIONAL CODING

Communication Lab. Assignment On. Bi-Phase Code and Integrate-and-Dump (DC 7) MSc Telecommunications and Computer Networks Engineering

BLOCK CODING & DECODING

BER MEASUREMENT IN THE NOISY CHANNEL

Experiment 7: Bit Error Rate (BER) Measurement in the Noisy Channel

H-Ternary Line Decoder for Digital Data Transmission: Circuit Design and Modelling

EC 6501 DIGITAL COMMUNICATION

Exercise 1-2. Digital Trunk Interface EXERCISE OBJECTIVE

Experiment 4: Eye Patterns

AC103/AT103 ANALOG & DIGITAL ELECTRONICS JUN 2015

CS311: Data Communication. Transmission of Digital Signal - I

DIGITAL COMMUNICATION

CAP240 First semester 1430/1431. Sheet 4

Experiment 13 Sampling and reconstruction

AIM: To study and verify the truth table of logic gates

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

Name: Date: Suggested Reading Chapter 7, Digital Systems, Principals and Applications; Tocci

BUSES IN COMPUTER ARCHITECTURE

COSC3213W04 Exercise Set 2 - Solutions

MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM

Chapter 9 MSI Logic Circuits

SingMai Electronics SM06. Advanced Composite Video Interface: HD-SDI to acvi converter module. User Manual. Revision 0.

LATCHES & FLIP-FLOP. Chapter 7

Synchronization Issues During Encoder / Decoder Tests

SingMai Electronics SM06. Advanced Composite Video Interface: DVI/HD-SDI to acvi converter module. User Manual. Revision th December 2016

A New Hardware Implementation of Manchester Line Decoder

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

Workshop 4 (A): Telemetry and Data Acquisition

Physics 217A LAB 4 Spring 2016 Shift Registers Tri-State Bus. Part I

Oscilloscopes, logic analyzers ScopeLogicDAQ

Asynchronous (Ripple) Counters

S op o e p C on o t n rol o s L arni n n i g n g O bj b e j ctiv i e v s

Generation of Novel Waveforms Using PSPL Pulse Generators

Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533

Application Note. Serial Line Coding Converters AN-CM-264

Assignment 2 Line Coding Lab

Lab #10 Hexadecimal-to-Seven-Segment Decoder, 4-bit Adder-Subtractor and Shift Register. Fall 2017

EMS DATA ACQUISITION AND MANAGEMENT (LVDAM-EMS) MODEL 9062-C

ASYNCHRONOUS COUNTER CIRCUITS

MODULE 3. Combinational & Sequential logic

Experiment # 4 Counters and Logic Analyzer

Digital Fundamentals: A Systems Approach

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS

4 MHz Lock-In Amplifier

2 MHz Lock-In Amplifier

Analyzing 8b/10b Encoded Signals with a Real-time Oscilloscope Real-time triggering up to 6.25 Gb/s on 8b/10b encoded data streams

3rd Slide Set Computer Networks

8. Stratix GX Built-In Self Test (BIST)

ASNT_PRBS20B_1 18Gbps PRBS7/15 Generator Featuring Jitter Insertion, Selectable Sync, and Output Amplitude Control

Laboratory 8. Digital Circuits - Counter and LED Display

Notes on Digital Circuits

UNIVERSITY OF BAHRAIN COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

Generation and Measurement of Burst Digital Audio Signals with Audio Analyzer UPD

MULTIDYNE INNOVATIONS IN TELEVISION TESTING & DISTRIBUTION DIGITAL VIDEO, AUDIO & DATA FIBER OPTIC MULTIPLEXER TRANSPORT SYSTEM

NAPIER. University School of Engineering. Advanced Communication Systems Module: SE Television Broadcast Signal.

Engineering College. Electrical Engineering Department. Digital Electronics Lab

Exercise 2: D-Type Flip-Flop

R.G.O. 32 BIT CAMAC COUNTER MODULE USER MANUAL

Flip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari

NAND/NOR Implementation of Logic Functions

MICROLINK 304x A-D Converter User Manual

013-RD

DIGITAL ELECTRONICS: LOGIC AND CLOCKS

Memory-Depth Requirements for Serial Data Analysis in a Real-Time Oscilloscope

Experiment 9 Analog/Digital Conversion

Bell. Program of Study. Accelerated Digital Electronics. Dave Bell TJHSST

RS flip-flop using NOR gate

6.111 Project Proposal IMPLEMENTATION. Lyne Petse Szu-Po Wang Wenting Zheng

Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:

Logic Gates, Timers, Flip-Flops & Counters. Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur

PHYS 3322 Modern Laboratory Methods I Digital Devices

Chapter 2. Digital Circuits

OFC & VLSI SIMULATION LAB MANUAL

Digital Circuits I and II Nov. 17, 1999

R3B Si TRACKER CABLE TEST REPORT

Notes on Digital Circuits

Solutions to Embedded System Design Challenges Part II

Transmission System for ISDB-S

Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours

What is sync? Why is sync important? How can sync signals be compromised within an A/V system?... 3

Exercise 2-1. External Call Answering and Termination EXERCISE OBJECTIVE

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

The Discussion of this exercise covers the following points:

Synthesis Technology E102 Quad Temporal Shifter User Guide Version 1.0. Dec

Chapter 11 State Machine Design

ELECTRICAL ENGINEERING DEPARTMENT California Polytechnic State University

Rec. ITU-R BT RECOMMENDATION ITU-R BT * WIDE-SCREEN SIGNALLING FOR BROADCASTING

Implementing a Rudimentary Oscilloscope

16 Stage Bi-Directional LED Sequencer

Lab #6: Combinational Circuits Design

INC 253 Digital and electronics laboratory I

Digital Systems Laboratory 3 Counters & Registers Time 4 hours

Graduate Institute of Electronics Engineering, NTU Digital Video Recorder

PicoScope 6407 Digitizer

EET 1131 Lab #12 - Page 1 Revised 8/10/2018

Transcription:

German Jordanian University Department of Communication Engineering Digital Communication Systems Lab CME 313-Lab Experiment 3 Line Coding Eng. Anas Alashqar Dr. Ala' Khalifeh 1

Experiment3Experiment Line Coding Objectives: The objectives of this experiment are to: Get familiar with definitions and properties of commonly used line codes. Measure the delay associated with practical digital systems. Introduction Digital data can be transmitted by various Line codes. Line codes are waveform patterns of voltage or current used to represent the 1s and 0s. Each line code has its advantages and disadvantages. Among other desirable properties, a line code is preferred to have the following: Bandwidth efficiency; the possibility of transmitting at a higher rate than other schemes over the same bandwidth. Power efficiency: For a given bandwidth and quality, the transmitted power should be as small as possible. No DC component; this allows AC coupling (capacitor or transformer) between stages (as in telephone lines). Spectrum shaping; this is important in telephone line applications, for example, where the transfer characteristic has heavy attenuation below 300 Hz. Synchronization; where bit clock recovery can be simplified. Error detection capabilities; It should be possible to detect some patterns of errors. Using a common external clock signal, the SEQUENCE GENERATOR produces twoindependent pseudorandom sequences X and Y. In this experiment we need only one output. The SEQUENCE GENERATOR will be clocked by B.CLK from the LINER ENCODER module. A SYNC output is provided which is coincident with the start of the sequences. The synch out from the SEQUENCE GENERATOR can be used to trigger the oscilloscope. The sequences may be stopped and restarted at any time via front panel controls. Sequences X and Y are available as either standard TTL or analog level output. The SEQUENCE GENERATOR is a basic module and you can read more about it in TIMS 301 User Manual. The module and its block diagram are shown in the figure below. 2

LINE ENCODER and LINE DEODER Modules In a digital transmission system line encoding is the final digital processing performed on the signal before it is connected to the analog channel, although there may be simultaneous bandlimiting and wave shaping. Thus in TIMS the LINE-CODE ENCODER accepts a TTL input, and produce an output that is suitable for transmission via an analog channel. The TIMS LINE-CODE DECODER decodes it back to the binary TTL format. The LINE-CODE ENCODER serves as a source of the system bit clock. It is driven by a master clock (M.CLK) at 8.3 khz (from the TIMS MASTER SIGNALS module). The LINE-CODEENCODER module divides M.CLK by a factor of four, in order to derive some necessary internal timing signals at a rate of 2.083 khz (B.CLK). The latter becomes a convenient for use as the system bit clock. The reason we are using a slower clock (clock/4) is that the encoder requires some cycles to provide the proper output and hence the data should arriveat a slower rate. Because the LINE-CODE DECODER has some processing to do, it introduces a time delay. To allow for this, it provides a re-timed clock (STROBE) if required by any further digitalprocessing circuits (eg, for decoding, or error counting modules). For a TTL input signal the following output formats are available from the LINE- CODEENCODER: NRZ-L, NRZ-M, UNI-RZ, BIP-RZ, RZ-AMI, BiØ-L (Manchester), DICODE-NRZ. Rather than defining each of the previous codes, you will find what they mean experimentally. 3

Lab Work Modules: To complete the experiment the following modules are needed: SEQUENCE GENERATOR,LINE-CODE ENCODER, and LINE-CODE DECODER. SEQUENCE GENERATOR 1. Construct Construct the TIMS model of line coding system as shown in below Figure Figure.1`Line Coding TIMS Model 2. Before plugging the SEQUENCE GENERATOR module in locate the on-board switch SW2 and set both toggles UP. 3. Adjust the gain of the BUFFER AMPLIFIERS to 1. Try all the coding schemes and prepare a chart as in Figure 2. Without using any textbook, try to determine the law of transformation for each coding scheme. 4

Figure.2 Line Codes 4. Using the PICO SCOPEmonitor the signals at the input of the LINE-CODE ENCODER and at the output of the LINE-CODE ENCODER for the NRZ-L code. Save the obtained signal in step 4 in your lab sheets. Compare between the original message signal and recovered signal, if there any difference explain the reasons in you lab sheet. 5