Digital Circuits Part 1 Logic Gates

Similar documents
Topics. Microelectronics Revolution. Digital Circuits Part 1 Logic Gates. Introductory Medical Device Prototyping

Digital Circuits. Innovation Fellows Program

Computer Systems Architecture

EXPERIMENT #6 DIGITAL BASICS

Digital Integrated Circuits EECS 312

Digital Integrated Circuits EECS 312. Review. Remember the ENIAC? IC ENIAC. Trend for one company. First microprocessor

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM

Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)

Physics 323. Experiment # 10 - Digital Circuits

Explosive growth over years - now dominates applications, still growing

EECS150 - Digital Design Lecture 2 - CMOS

Logic. Andrew Mark Allen March 4, 2012

[2 credit course- 3 hours per week]

DIGITAL CIRCUIT COMBINATORIAL LOGIC

Laboratory 7. Lab 7. Digital Circuits - Logic and Latching

Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements

CCE RR REVISED & UN-REVISED KARNATAKA SECONDARY EDUCATION EXAMINATION BOARD, MALLESWARAM, BANGALORE G È.G È.G È..

B. Sc. III Semester (Electronics) - ( ) Digital Electronics-II) BE-301 MODEL ANSWER (AS-2791)

Microprocessor Design

Laboratory 10. Required Components: Objectives. Introduction. Digital Circuits - Logic and Latching (modified from lab text by Alciatore)

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

DepartmentofElectronicEngineering NEDUniversity ofengineering &Technology LABORATORY WORKBOOK DIGITAL LOGIC DESIGN (TC-201)

MSCI 222C Fall 2018 Introduction to Electronics

Introduction to Microprocessor & Digital Logic

EE292: Fundamentals of ECE

Chapter 5 Flip-Flops and Related Devices

Digital Electronic Circuits and Systems

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters

WINTER 15 EXAMINATION Model Answer

Logic Circuits. A gate is a circuit element that operates on a binary signal.

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science

Helping Material of CS302

Experimental Study to Show the Effect of Bouncing On Digital Systems

Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:

G. D. Bishop, Electronics II. G. D. Bishop, Electronics III. John G. Ellis, and Norman J. Riches, Safety and Laboratory Practice

Laboratory 9 Digital Circuits: Flip Flops, One-Shot, Shift Register, Ripple Counter

Flip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001

LAB #4 SEQUENTIAL LOGIC CIRCUIT

CPS311 Lecture: Sequential Circuits

PHY 351/651 LABORATORY 9 Digital Electronics The Basics

ME 515 Mechatronics. Introduction to Digital Electronics

Digital Principles and Design

Sequential Logic Basics

Light Emitting Diodes and Digital Circuits I

The University of Texas at Dallas Department of Computer Science CS 4141: Digital Systems Lab

University of Victoria. Department of Electrical and Computer Engineering. CENG 290 Digital Design I Lab Manual

Saturated Non Saturated PMOS NMOS CMOS RTL Schottky TTL ECL DTL I I L TTL

IC TECHNOLOGY Lecture 2.

TYPICAL QUESTIONS & ANSWERS

Lecture 1: Circuits & Layout

Chapter 2. Digital Circuits

CS302 Glossary. address : The location of a given storage cell or group of cells in a memory; a unique memory location containing one byte.

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology

ELEN Electronique numérique

Sequential Logic. References:

Assignment 2b. ASSIGNMENT 2b. due at the start of class, Wednesday Sept 25.

Integrated Circuit Design ELCT 701 (Winter 2017) Lecture 1: Introduction

An Introduction to Digital Logic

Asynchronous (Ripple) Counters

MSCI 222C Class Readings Schedule. MSCI 222C - Electronics 11/27/18. Copyright 2018 C.P.Rubenstein Class Seating Chart Mondays

Lecture 1: Intro to CMOS Circuits

MSCI 222C Fall 2018 Introduction to Electronics

EE 367 Lab Part 1: Sequential Logic

ELECTRICAL ENGINEERING DEPARTMENT California Polytechnic State University

COMP2611: Computer Organization. Introduction to Digital Logic

16 Stage Bi-Directional LED Sequencer

COE328 Course Outline. Fall 2007

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL

Digital Circuits I and II Nov. 17, 1999

Physics 120 Lab 10 (2018): Flip-flops and Registers

Texas Instruments TNETE2201 Ethernet Transceiver Circuit Analysis

TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC)

Light Emitting Diodes and Digital Circuits I

The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of

Music Electronics Finally DeMorgan's Theorem establishes two very important simplifications 3 : Multiplexers

Introduction to Digital Electronics

'if it was so, it might be; and if it were so, it would be: but as it isn't, it ain't. That's logic'

Chapter 7 Counters and Registers

EET 1131 Lab #10 Latches and Flip-Flops

Topics of Discussion

Light Emitting Diodes and Digital Circuits I

Review : 2 Release Date : 2019 Last Amendment : 2013 Course Code : SKEE 2742 Procedure Number : PK-UTM-FKE-(0)-10

Basics Of Digital Logic And Data Representation

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

Rensselaer Polytechnic Institute Computer Hardware Design ECSE Report. Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

Part IA Computer Science Tripos. Hardware Practical Classes

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY

Laboratory 8. Digital Circuits - Counter and LED Display

WINTER 14 EXAMINATION

Part IA Computer Science Tripos. Hardware Practical Classes

1967 FIRST PRODUCTION MOS CHIPS 1969 LSI ( TRANSISTORS) PMOS, NMOS, CMOS 1969 E-BEAM PRODUCTION, DIGITAL WATCHES, CALCULATORS 1970 CCD

Notes on Digital Circuits

EE Chip list. Page 1

PLTW Engineering Digital Electronics Course Outline

Digital Circuits 4: Sequential Circuits

MSCI 222C Class Readings Schedule. MSCI 222C - Electronics 11/20/ Class Seating Chart Mondays Class Seating Chart Tuesdays

CPE 200L LABORATORY 3: SEQUENTIAL LOGIC CIRCUITS UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: SR FLIP-FLOP/LATCH

Laboratory 11. Required Components: Objectives. Introduction. Digital Displays and Logic (modified from lab text by Alciatore)

Transcription:

Introductory Medical Device Prototyping Digital Circuits Part 1 Logic Gates, http://saliterman.umn.edu/ Department of Biomedical Engineering, University of Minnesota

Topics Digital Electronics CMOS Logic National Instrument s Multisim (SPICE) and Ultiboard Software Prototyping with Breadboards Boolean Logic CMOS and TTL IC Packaging and Pinouts Various Devices and Circuits Schmitt triggers Contact debouncing Simulation and elimination of noise; voltage summing Leading edge detection Counters and 7-segment display Drivers for LEDs, lamps and relays Field Programmable Gate Arrays (FPGA)

Microelectronics Revolution Triode tube 1915 (Langmuir) Point-contact transistor 1947, Bell Labs (Brattain and Bardeen). Junction transistor 1948 (Shockley), IC 1958 (Kibly and Noyce), & Intel Pentium Microprocessor 10 8 Transistors!

From Molten Silicon to IC Chips Molten silicon - Czochralski puller technique Silicon wafer diced into integrated circuits (DIP and SMD). Single crystal silicon boule

CMOS Logic Complementary Metal Oxide Semiconductor Logic (4000B and 74HC00 series) Wide range of power supply voltages, from 3 to 15 Vdc Logic changes half-way up the power supply voltage, giving good noise immunity. Almost no power supply current needed except during input logic changes. Inputs are open circuits and easy to drive. The unloaded output logic swings the full range of the power supply. CMOS circuits create little noise of their own. CMOS circuits pass along less noise. Low cost.

Design with NI Multisim

CMOS Packages & Pins Lancaster, D. and Berlin, H.M. CMOS Cookbook. H.W. Sams, Indianapolis, IN (1988)

Inverter 74HC04 Notice the output is inverse to the input. Input High Low Output Low High

Available Logic Gates in the 74HC04 Lancaster, D. and Berlin, H.M. CMOS Cookbook. H.W. Sams, Indianapolis, IN (1988)

NAND 74HC00 Input 1 Input 2 Output 0 0 1 1 0 1 0 1 1 1 1 0 If either or both inputs are low the output will be high.

Available Logic Gates in the 74HC00 In addition to this NAND gate, there are many different types and combinations of Boolean logic gates to select from. These include AND, OR, NOR, Exclusive OR & NOR and others. Lancaster, D. and Berlin, H.M. CMOS Cookbook. H.W. Sams, Indianapolis, IN (1988)

Flip-Flop 74HC74 QQ QQ Notice the divide by 2 of frequency. The information presented to the D input goes on to the QQ output whenever the clock input changes from a low to a high level. If D is high, on clocking, QQ goes high and QQ goes low. If D is low, on clocking, QQ goes low and QQ goes high.

4 Bit Binary Counter with Buffer Drivers Place 2 3 =8 2 2 =4 2 1 =2 2 0 =1

Available Logic Gates in the 74HC74 In addition to this D-Flip-Flop, there are also JK Flip-Flops Lancaster, D. and Berlin, H.M. CMOS Cookbook. H.W. Sams, Indianapolis, IN (1988)

Counter on Breadboard

Tri-State Logic 74HC126

Available Logic Gates in the 74HC126 Lancaster, D. and Berlin, H.M. CMOS Cookbook. H.W. Sams, Indianapolis, IN (1988)

Schmitt Trigger 74C14

Switch Contact Noise Thresholds are ~ 1.35 V for Low and 3.15 V for High Mechanical contact noise can cause multiple pulses to occur the first 100 µs or so. In this example, three pulses would be generated.

Contact Debouncer Schmitt Trigger Output Input Switch Off & On

Creating Noise with Voltage Summing Voltage Summing Voltage Inverter

Noise Eliminator Schmitt Trigger 4093B Summer Input Output Voltage Follower

Leading Edge Detector Schmitt Trigger Debounced button pushes Single pulse with each positive edge

Available Logic Gates in the 74HC14 & 4093B Lancaster, D. and Berlin, H.M. CMOS Cookbook. H.W. Sams, Indianapolis, IN (1988)

One-and-only One Synchronized Pulse Clock Button Output is a synchronized pulse with the clock, while the button push is not.

Driving LEDs 4049B Current sourcing. Current sinking. RR 1 oooo 2 = VV FF II FF The 4049 Inverter- Buffer can source or sink sufficient current to light the LED directly. For other CMOS logic you need to have a transistor. Push Button Debounce Certain devices, like counters, may have built in LED drivers.

Available Logic Gates in the 4049B Lancaster, D. and Berlin, H.M. CMOS Cookbook. H.W. Sams, Indianapolis, IN (1988)

Lamp Driver with Transistor Lamp is rated 5 V and power of 200 mw. Required current: PPPPPPPPPP WW = II 2 RR = VVVV II = PPPPPPPPPP WW 200 mmmm = = 40 mmmm VV The 2N2222 is a general purpose medium power amplifier and switch, for I C of up to 500 ma (max. 1 A). 5

MOSFET Relay Driver with Transient Suppression MOSFET is a transconductance device (base current is negligible, base voltage controls collector current). The MOSFET allows for higher collector current than the BJT.

Field Programmable Gate Arrays (FPGA) These are ICs that can be programmed in the field with Hardware Descriptive Language (HDL). They contain an array of programmable logic blocks that can be wired together with software. Images from Wikipedia, used under Creative Commons

Summary CMOS Logic Designing with NI Multisim (SPICE) and Ultiboard Software Prototyping with Breadboards Boolean Logic CMOS Packaging and Pinouts Various Devices and Circuits Schmitt triggers Contact debouncing Simulation and elimination of noise; voltage summing Leading edge detection Counters and 7-segment display Drivers for LEDs, lamps and relays Field Programmable Gate Arrays