NATIONAL RADIO ASTRONOMY OBSERVATORY

NATIONAL RADIO ASTRONOMY OBSERVATORY GREEN BANK ) WEST VIRGINIA ELECTRONICS DIVISION INTERNAL REPORT No. 17 DDP-116/MODCOMP DATA LINK AT THE -FT TELESCOPE GEORGE H. PATTON APRIL 17 NUMBER OF COPIES:

DDP-116/MODCOMP DATA LINK AT THE -FT TELESCOPE George H. Patton TABLE OF CONTENTS Page I. Introduction. OOOOOOO OOOOO 1 II. Description... OOOOOOOOOOO OOOOOOOOOOO OOOOOOOOOOOO 1 A. Modcomp Computer and Peripheral Equipment.. 1 B. Data Link.... 1 III. Programming OOOOO.0 0 0 0 OOOOO OOOOOOOOOOOOOOOO 2 A. Link Address. o O. OOOOOOO 2 B. Link Status. o OOOOO 2 C. Link Commands.. OOOOO 3 D. Interrupts.. OOOOO. OOOOO 7 IV. Circuit Description... OOOOO O. OOOOO 00 OOOOO 000000 OOOOO 0000 OOOOO 0 8 V. Acknowledgements.... OOOOO OOOOOOOOO 0 0 VI. Mnemonic List.. OOOOOOOOOOOOO 00.0... 000 0 0 0 00 OOOOOOO 0 OOOOO 0000. LIST OF FIGURES No. 1 Modcomp-116 Link - Sheet 1 of 3 O 1 2 Modcomp-116 Link - Sheet 2 of 3 OO O OO 1 3 Modcomp-116 Link - Sheet 3 of 3 O OO OOO OO OO O OO 16 116-Modcomp Link Buffer - Card 1 0.000.01.00 17 116 Modcomp Link Buffer - Card 2. 0.000000.00000000. 18

DDP-116/MODCOMP DATA LINK AT THE -FT TELESCOPE George H. Patton I. Introduction A Modcomp 11/2 digital computer has been installed in the -ft telescope to permit the observer to perform some real time data reduction. The data, collected by the DDP-116 computer, can be transferred via a data link to the Modcomp and stored for processing by the observer. This report gives a description of the data link between the two computers. II. Description A. Modcomp Computer and Peripheral Equipment. The Modcomp 11/2 purchased for the -ft telescope is a general purpose 16-bit computer with 32 K words of core memory. Two general purpose controller modules were also purchased to facilitate interfacing the Modcomp computer to special NRAO devices. One of these controllers is used in the data link. The peripheral equipment consists of a punched card reader (Documation M200), a moving head disc with 2,8,00 words of storage (Diablo), a computer display terminal (Tektronix 0), and a hard copy unit (Tektronix 6). This equipment is located adjacent to the CPU unit in the control room. B. Data Link The data link is designed to transfer data between the two computers in block form (DMC mode for the DDP - 116 and DMP mode for the Modcomp) and can operate in either direction. At the present time, the link is active only in the direction for data transfer from the DDP-116 to the Modcomp, but can be activated in the other direction when required and the software becomes available. Once initialized, the transfer occurs at a rate of approximately one word every 7 psec times the number of words being transferred.

2 III. Programming A. Link Address The link address is different for the DDP-116 and the Modcomp since it was chosen not to coincide with any planned additions to either computer. The link address and associated information for each computer is as follows: commands: B. Link Status DDP-116 Link Arrangements: Link Address: 0 DMC Channel: 0* PIL Line: 1 * The start and stop addresses for DMC channel 0 are 20 and 21 respectively. Modcomp Link Arrangements: Link Address: 1C DMP Channel: 0* * The TA (transfer address) and TC (transfer count) locations are 7 and 6 respectively. The link status may be checked by the DDP-116 with the following SKS 20: The DRL (device ready line) will be low if the DDP-116 has reached an end of range. SKS 30: The DRL will be low if the Modcomp is ready to receiver or transmit data. SKS 0: The DRL will be low if the link is set to transfer data from the Modcomp to the DDP-116. The computers need not be ready to transfer data as this SKS just indicates the present condition of the direction flip-flop.

3 The Modcomp can check the link status by performing an input status command for device 1C. The status word has the following configuration: Bit 0 1 = Link controller power on. Bit 1 0 Bit 2 0 Bit 3 0 Bit 1 = Memory Parity Error. Bit 0 Bit 6 0!iI_Z Lf_nSL21 1 2_1 _11_11P.P.sfer Data. Bit 8 0 Bit 0 Bit A 0 Bit B 0 Bit C 1 = DDP-116 Ready to Transfer Data. Bit D 1 = EOBLK (End of Block) Flip Flop Set. Bit E 1 = ERL (End of Range) Flip Flop Set. Bit F 1 = Direction Flip Flop Set for Transfer from Modcomp. C. Link Commands The link commands for the DDP-116 are listed below: OCP 00: This command is used by the DDP-116 to initiate data transfer from it to the Modcomp. When the command is issued, the following flip-flops are set: 1. 116 Ready. 2. Direction (indicates transfer from Modcomp). 3. DIL Providing DMC channel 0 has previously been set up in the DDP-116, this command will load the first word to be transferred into the link buffer register and wait for the Modcomp to acknowledge the transfer request. The Modcomp would recognize the transfer request by monitoring the link status word bits C (DDP-116 Ready) and F (Direction).

OCP : This command is used by the DDP-116 to acknowledge a data transfer request initiated by the Modcomp for transfer from the Modcomp. This request would be via an interrupt on PIL 1 in the DDP-116. When interrupted, the DDP-116 needs to perform a series of SKS's to determine the reason for the interrupt. When this command is executed, the following flipflops are set: 1. 116 Ready. 2. DMP Request. When the Modcomp receives the DMP request, it will load the first word to be transferred into the link register and generate a PIL to the DDP-116. If DMC channel 0 has been set up, the transfer will take place. OCP 20: This command is used by the DDP-116 to initiate data transfer from the Modcomp to it. When the command is executed, the following flip-flops are set: 1. 116 Ready. 2. DMP Request. Also, the Direction flip-flop is reset so as to indicate a data transfer from the Modcomp. With the DMP Request flip-flop set, the link waits for the Modcomp to acknowledge the request which it detects by monitoring the link status and observing the DDP- 116 going ready. When the Modcomp acknowledges the

OCP 20 continued): request, and the Mod Ready flip-flop is set, the DMP Request will be sent on to the CPU and the first word will be loaded into the link register. The transfer will then occur providing DMC channel 0 is set up in the DDP-116. OCP 30: This command is used by the DDP-116 to acknowledge a data transfer request initiated by the Modcomp for transfer to the Modcomp. The transfer request would be via an interrupt on PIL 1 and the DDP-116 would need to perform the necessary SKS's to detect the reason for the interrupt. This command sets the following flip-flops: 1. 116 Ready. 2. DIL. Setting the DIL flip-flop will cause the DDP-116 to load the first data word to be transferred into the link register, thus starting the block transfer. Any of the OCP's listed above will also reset the ERL (End of Range) and EOBLK (End of Block) flip-flops. The Modcomp controls the link via the command OCB to device 1C. This instruction outputs a command word which permits control of the link by changing the word's bit pattern. The configuration of the command word is as follows:

Bit 0 1 = Transfer Initiate (0 = Control) Bit 1 1 Bit 2 1 = Data Interrupt Connect Bit 3 1 = Service Interru t Connect Bit 1 = End of Block Bit 1 = Terminate Bit 6 1 = Direction into Modcomp Bit 7 1 = DDP-116 Interru t Bit 8 1 = Modcomp Ready Bit 0 Bit A 0 Bit B 0 Bit C 0 Bit D 0 Bit E 0 Bit F 0 The following gives a brief explanation of the bits in the control word. BIT 2 and BIT 3: These two bits connect (or enable) the data and service interrupts respectively in the general purpose control of the Modcomp. BIT : This bit can be used to signify an end of block of data. It is not needed for the link as an end of block is already generated in the DM F mode. BIT : This bit can be used to terminate a transfer any time. A terminate command will also cause a Service Interrupt if this interrupt is enabled. BIT 6: This bit controls the direction flip-flop in the link along with commands from the DDP-116. BIT 7: This bit when set will interrupt the DDP-116 on PIL 1 (normally used when the Modcomp wants to initiate a transfer). BIT 8: This bit controls the Modcomp Ready flip-flop and is used to enable the link on the Modcomp end. The appropriate selection of bits can then handle all combinations of transfer requests either when the Modcomp initiates the request or acknowledges one from the DDP-11.6.

7 D. Interrupts The DDP-116 can be interrupted on PIL 1 by two methods (PIL 1 entrance location = 6 ): 8 1. An interrupt will be generated on PIL 1 when an end of range (ERL) is generated by the DDP-116 along with an input or output data command (INDCM or OUDCM) from the Modcomp, depending on the direction of transfer. 2. An interrupt can also be generated on PIL 1 by the Modcomp when it does an OCB to the link with bit 7 set. The Modcomp has two interrupts connected to the link. These are the data interrupt (DI) and the service interrupt OW for device address 1C (DI entrance location = C 16' SI entrance location = DC ). If these interrupts 16 are enabled, the following will generate an interrupt to the Modcomp. DATA INTERRUPT: A DI will be generated when the Modcomp reaches an end of block (EOBLK) in a DMP transfer. SERVICE INTERRUPT: A SI will be generated when one of three conditions are met. 1. When a terminate command is executed by the Modcomp. 2. When the Modcomp either reaches an end of block or outputs an end of block command. 3. When a complete (CMPT) is generated in the link. This is generated when either computer has transferred its entire block of data. Additional information on the programming for the computers can be found in their respective Programmers' Reference Manuals.

IV. Circuit Description The electronics for the link is located in two locations, with the main portion located with the General Purpose Controller in the Modcomp. The remainder, which consists of two buffer cards, is located in the expansion rack in the DDP-116. Figures 1, 2 and 3 show the circuit built on the board with the General Purpose Controller. This controller is designed with room for customer additions to interface with special systems. The circuits shown are just the addition to the controller. Along with the customer interface, there were four wiring connections to be completed in the controller. They were as follows: 1. Link address 1C. 2. Interrupt priority code. 3. Source ID for interrupt.. DMP channel address. The location for these connections and diagrams for the General Purpose Controller can be found in the Technical Manual, Peripheral Controllers, Volume II for the Modcomp computer. Figure 1 shows the logic for decoding commands from the DDP-l16, logic for SKS instructions, logic for generating CLEAR signals, and inverters for the bits from the output bus in the DDP-116. Output commands 00,, 20, 360, and 0 are decoded and gated with the OCP pulse. OCP 0 is not used at the present time but is available for future expansion. An output command pulse OCP 0 is also generated anytime an OCP is executed in the link. This pulse is used to reset the ERL and EOBLK flip-flops. The pulse OCP 0A is OCP 0 delayed by a few psec and is used to set the 116 READY flip-flop.

Three types of clear signals are generated: CLEAR A, CLEAR B, and CLEAR. CLEAR A is generated from MSTCL (Master Clear from the DDP-116) or ICBFB (Master Clear from the Modcomp), CLEAR B is generated from a CLEAR A signal or a TERM (Terminate) from the Modcomp, and CLEAR is generated from a CLEAR B signal or a HALT from the link. The three clear signals reset flip-flops as follows: CLEAR A: Resets - SI REQUEST F/F CLEAR B: Resets - PIL F/F 116 READY F/F DIL F/F ERL F/F EOBLK FiF OUT/IN F/F DMP REQUEST F/F Also clears - BUFFER 1 BUFFER 2 CLEAR: Resets - MOD READY F/F Figure 2 shows the buffer register in the link used in data transfer between the two computers. BUFFER 1 is used in transfer from the DDP-116 to the Modcomp. The output word from the DDP-116 is latched into this buffer by an OTP pulse gated with a DAL pulse. These two pulses gated together also generate a DATA READY pulse which sets the DMP REQUEST flip-flop notifying the Modcomp that a word is in the buffer. BUFFER 2 is used for transfer in the other direction ( q odcomp to DDP-116). The output word from the Modcomp is latched into the register by an OUDCM pulse which also sets the DIL flip-flop notifying the DDP-116 that the buffer contains data. The data contained in BUFFER 2 is then gated on to the DDP-116 input bus by a DAL pulse for transfer in this direction.

-- Figure 3 contains the remaining of the custom logic for the link which is located with the General Purpose Controller. This figure contains most of the receivers for command pulses from the DDP-116 along with the link control logic. The flip-flops used for control are explained in the following: MOD READY F/F: This flip-flop is set when the Modcomp performs an OCB with bit 8 set. It signifies that the Modcomp is ready to transfer data. It also gates the output of the DMP REQUEST F/F to the Modcomp and gates the RRL signal to the input of the DMP REQUEST F/F. SI REQUEST F/F: This flip-flop, when set, generates a service interrupt to the Modcomp. It can be set by an end block (EOBLK) or terminate command from the Modcomp, and by a complete of transfer (CMPT) from the link. It is reset by reset service interrupt (SIRSTN), CLEAR A, or load command register (UDGMR) pulse. DMP REQUEST F/F: This flip-flop is set when the link wants to transfer a word either to or from the Modcomp via a DMP channel. It can be set by an RRL pulse gated with the MOD READY signal, DATA READY signal, OCP 20, or OCP, depending on direction of transfer and whether initiating transfer or transfer in progress. The flip-flop is reset by a data command (DCM), end of block (EOBLK), data command delayed (DMCA) gated with end of range (ERLA) or CLEAR B. The DCM signal resets the flip-flop after every word transfer, while the rest of the reset signals are either associated with an end of block of data, a terminate command, of a master clear from either computer. PIL F/F: This flip-flop, when set, will interrupt the DDP-116 on priority interrupt line 1. It can be set by an OCB from the Modcomp with bit 7 = 1 or with a CMPT B. (CMPT B is an end of

PIL F/F (continued): range gated with data command pulse from the Modcomp.) It is reset by an acknowledge (ACK) signal from the DDP-116 or a CLEAR B signal. 116 READY F/F: This flip-flop, when set, signifies that the DDP-116 is ready to transfer data. It is set by an OCP 0. (0CP 0 is generated anytime the DDP-116 executes an OCP on the link.) It is used to gate signals to the DIL FiF for data transfers. They are (1) an end of range (ERL) from the DDP-116, (2) an end of block (EOBLK) from the Modcomp gated with the OUT/IN direction signal, (3) an end of block gated with a DAL, and () a CLEAR B. The second and third methods of reseting the flip-flop deal with an end of block from the Modcomp and are gated with the appropriate signal to make sure the last word to or from the Modcomp is removed from the link's buffer register before the flip-flop is reset. DIL F/F: The DIL flip-flop is set every time the link wants to transfer a word in or out of the DDP-116 via DMC channel 0. This is done by an OCP 0, output data command gated with the OUT/IN FF for transfer from the Modcomp, or input data command gated with the OUT/IN FiF for transfer in the other direction. There is a delay of approximately 7 psec in the clock pulse to the DIL F/F to slow down the rate of transfer in order to avoid any conflict with the DDP-116's normal functions. The DIL flip-flop is reset by all the signals which reset the 116 READY F/F plus it is reset by a DAL pulse each time a word is transferred in or out of the DDP-116.

- - ERL F/F: This flip flop is set when the DDP-116 reaches an end of range in a DMC data transfer. It is reset by a load command register (LDCMR) pulse from the Modcomp, by an OCP 0 from the DDP-116, or by a CLEAR B. EOBLK F/F: This flip-flop is set when the Modcomp reaches an end of block in a DMP data transfer. It is reset by the same signals as the ERL F/F. A one shot multivibrator, location U11, is used to generate a delayed data command pulse from the Modcomp. This delayed pulse, gated with end of range (ERL) from the DDP-116 generates a pulse called complete B (GMPT B). CMPT B indicates that an end of range has been reached and the last word removed from the link buffer for data transfer to the Modcomp. Likewise, an end of block from the Modcomp (EMILK) gated with a DAL from the DDP signifies that the entire data block has been transferred from the Modcomp and the DDP-116 has removed the last word from the link buffer register. The rest of Figure 3 contains gating for the various control signals. Figures and are the buffer cards for the DDP-116. These cards contain the necessary line drives and gates to drive the 60 feet of cable between the DDP-116 and the Modcomp and are located in the DDP-116 expansion rack. V. Acknowledgements Credit should be given to R. Weimer, D. Schiebel and W. Vrable for their help in the design and construction of the data link.

-- VI: Mnemonic List Mnemonic Description ACK Acknowledge signal from DDP-116 used to reset PIL F/F. ADBxx Address bits from DDP-116. CLEAR Generated by Master Clear, ICBFB, TERM, or HALT. CLEAR A Generated b Master Clear, or ICBFB. CLEAR B Generated by Master Clear, ICBFB, or TERM. CMPT Generated by CMPT A or CMPT B. CMPT A Complete A, generated by EOBLKA gated with DAL. CMPT B Complete B, ;:,enerated by ERLA sated with DCMA. DAL Signal from DDP-116 when a DMC work transfer occurs. DATA READY Signal which signifies data is in the link buffer for the Modcomp. DATARS Signal used for DMP word transfer request in Modcomp. DCMA Pulse to gate data to 'orfrom the Modcomp. DFB Output data from buffer - Modcomp. DIL Request for data transfer in DMC DDP-116. DTLM Input data to computer - Modcomp. EOBLK...Signal enerated at end of DMP block transfer - Modcomp. EOBLKA ERL ERLA HALT ICBFB Signal from F/F in link set by EOBLK. Signal generated at end of DMC block transfer Signal from F/F in link set by ERL. Sipal generated by EOBLKA or ERLA. DDP-116. INB INDCM ISLM xx LDCMR LDCMRA LDCMRB MOD READY OCP OCP xxx OCP 0 OCP 0A OTB xx OTB A xx OTP OUDCM OUT/IN PIL 1 RRL SIRSTN SKS xxx STSIRQ TERM Master clear - Modcomp. Input bits to DDP-116. Input data command - Modcomp. In ut status bit - Modcom Load command register pulse - Modcamp. DFB06 gated with LDCMR. DFB06 gated with LDCMR. Signal which signifies the Modcomp is ready to transfer data. Output control pulse from DDP-116. Output command gated with OCP. Pulse generated any time an OCP to the link is executed. Dela y ed OCP 0. Output bit from DDP-116. Inverted OTB xx. Output pulse for gating output bits from DDP-116. Output data command - Modcomp. Signal from F/F in link which determines direction of transfer. Priority interrupt line 1 - DDP-116. Pulse used to reset ready condition in the link. Signal to reset Service Interrupt F/F Modcomp. Sensing commands from DDP-116. Set Service Interrupt request to Modcomp. Terminate command from Modcomp.

C1-2._3 MSTCL >""- CI-26 "I"D 0 70. 8820 6 U2J ICBFB > HALT > V2BO2 CLEAR A CLEAR B 70 70 3 737 CLEAR B 732,11 11 732 732 CLEAR CLEAR ERLA 20 OUT/IN 0 SKS 20 ( LOW FOR ERL ) S KS 0 ( LOW FOR OUT OF MODCOMP ) CI-01-02 - 03 OTB C3 - ADB 16 C3-8 ADB1 > 30 SKS 30 ( LOW FOR MOD READY) MOD READY DRL+ " I - 0-0 - 06 C3-7 ADB 1 > OCP 0-07 6 C3- ADB C3-6 ADB C3- ADB II > II UJ 02 UJ06 2 UJI3 J1 _11 UJ0 Vc c 1 1111111 Wv-- II C3-3 ADB I 0 OCP 30 UJ K pf C 3-2 ADB 0 C3-1 ADB 08 >1" j" 1 3 70 IK LOW FOR POWER ON 2 p 702 OCP 00 OCP OCP 20 OCP 0 UIP 2r - 31116 71 vcc"rb "I"E "1"Fill"G 1 II 8 "En 1 2 3 6 7 "I"A "I"B "I"C - 0 8 0CPIDA IK UM 70 C 2-23 MODCOMP 116 LINK Sheet I of 3 00 pf - 0 - - 1 3-1 - 1-16 U L 70 FIG. I OTBA 0 0 06 07 08 0 11-1 2 1 3 1 1 1 6

BUFFER 1 BUFFER 2 OTBA 1 0 1 > 0 2 > 0 11 3 >--- 6 0 > >--- 3 0 6 > 1 0 7 >--- 0 8 I I 0 > 6 1 0 I I 3 1 2 >-- 7 I 7 B VIP 717 VIN A C 717 B VIM A 1 DTLM > 00 > 01 1 0 --> 0 2 7 > 0 3 0 2 > 0 INB C2 01 I < 02 6 2 < qvj 3 < 03 0 if < c(tj 703 OPEN COLLECTOR DFB 1 1 3 V J 2 8 VJ 0 3 <. V J 2 0 6 6< 60( V J 07 7< V J 0 8 II 8 < V J 0 3 < </ 3J I 6 1 0 < V 3 J 1 1 1 I < 8.0E/3J 11 < V3 J < 1 6 1< V 2J 30E2J 2 1 8 1 < 0( i2j111l. 7 1 717 V IL A IT- 7 17 c V IK B II 1 ---> 1 --> 1 7 2 1 < 16 16 V 2J 1 7 7 17 VIJ A 2 A 0 I I I < 0 2 6 < 0 3 < 0 3 0 1 < 1 2 I I 6, 3 1 V 3M 0 UDCM CLEAR B 8 CLEAR B 70 V 2P 708 708 OTP 2 V 2P DATA OUT/IN READY V2P DAL DAL MODCOMP 116 LINK Sheet 2of 3 FIG. 2 1 1

708 LDCMR 8 DFB07> V3 ;) (V308) CMPT B 2 732 "I"A OUT/1N "I" C 1 MOD READY ISLM07 (V30) PIL F/F 77 C VK 0 MOD READY _ F/F U2N C _r V3M 6 PILlS 70 3 LDCMR 6 OUDCM INDCM 70 ACK _FL CLEAR "I"A 2 702 < SIRSTN -u- 1 V3M V3N V3K 708 "I C (UI F08) C3-2 ACK 3 0>-- 3 8820 6 II II uc A CLEAR B 732 C3-21 > V2M II EOBLK ISLMI2 STS I R0_ 0 (UIE01) I " C SI REQ CMPT ACK 1 1 (V2002) CMPT A U3N F/F OCP0A > 1.:1:1 708 2 70 - UN 2 UIJ02 -- 2 UIJ06 - C3-18 C3-I C2-2 C2-26 31 1 6 I UIJI3 11 UIJ0 77 116 READY F/F 732 DAL V3N EOBLKA 602 V K 2 1 0 UIH OCP 00 LDCMR 732 CLEAR A 702 CLEAR B I II 732 "I" C 8 732 1 C 702 DFB08 (V3B) TERM (U3L 0) V3N 732 732 8 708 708 8 708 MOD 708 OUT/IN DATARS 2 6 " 1 "C UIL V3N (11 L (UC 03) UIL OUDCM EOBLKA DMP REQ MOD F/F "I A READY -L A 732 6 77 3 DCM 6 Q U2M C UIM 732 2 702 PIL 1 EOBLK 702 DIL F/F 708 PIL 1 77 _ DCMA 6 70 UIL 8 "l Ao 2 ERLA 732 "I c 732 CMPT B 6 ERL 1 CLEAR B 732 "I"C 732 DAL OUT/ IN F/F D READY RRL OCP II 20 DATA READY OCP "I"E 0 C P OUT/IN < Vcc _ 77 OCP00 3 0 C P DC-1 (V2 D) ISLMI < U2M C3-1> 1 111111 8 + 8820 U1J LDC MR B (UB0) DRID01 732 300pF C3-1> V2L V L OTP 7K CM PT A.01 pf CLEAR B CMPT 0 732 CMPTB 2 31116 71 OCP 20 LDCMRA 70 708 II II ERL Vcc C3-16 > + 8820 J1_ 1 1,111 11 81 C3-17> - V2 L V 2 V31) 3 > - ERL LDCMR< 70 -If DC-2 rit-1,3 2 U J LDCMRN U3N U3N "I" E 7K UJ02 11 III 1 --LIL0 270 pf U J 06 602 _FL 1 C3-22 < 8830 2 16 7 I U H 6 3K DCMA II C3-23 < V2 N II i ll 1.1 0.1.1. LDCMRA < 2 708 LDCMRB < 6 (M OIL 0 (V2DI0 ) ISLMI 77 ERL -o "I" B o TERM U,1 70 - DAL 0 70 F/F (V6 B)> UJ0 C3-2> 732 6 732 U2L c 6 3 ERL OUDCM 732 U3N + 8820 V2K V3L V3L > DAL HALT C3-2> 11,111, DCM L DA L0 ISLMI3 (V200)< _11_ EOBLKA < Q77 D "I" B "I"B > DAL OCP0 EOBLK 70 >1 8820 C 2-21 + C2-22> V2K - -1_11R.L 70 V3L 708 V2P) j1; RRLLDCMR B 732 8 I : CLEAR 702 _ F/F "1- U2L FIG. 3 MODCOMP 116 LINK Sheet 3 of 3 1 EOBLK U3N -< EOBLKN (V6 D 08) IN DCM < --t_r 3 -< LDCMRN (U2DII) <DFB06 (V3806) OUDCMN ( V6E06) U3N -< INDCMN 70 (V6 F06) 1

- 17 - ADB 7 II > 6> RI RI 7 > R2 8 1 0 R2 -- R3 1 2 737 2 737 11 ADB+ 3 7 > 0 1 >2 3 11 ADB 1 1 16 737 > R I 11 > 11 R 1 3 > 2 R > R 737 70)3 ADB+ > 6 1 > 7 1 >8 16 OTB+ 737 OTB- OTB+ 1 17 > > 2 I R6 18 > )3 2 R6 3 1 > 8 R7 io -2-0-)o > 3 II 1 3 20> 11 R7 > 21> >6 R8 6 22> 1 )06 1 >7 6 R8 7 8 23> >8 7 1 0 R -"" 2> 11 1 > 8 R 1 737 OTB 2 > 2 T IT Y > 60 RIO 26> RIO 27> R11 28> R11 (2 27> R 30> R 31> RI3 II 16 32> RI3-7> 737 737 11 61 > 62 II >63 >6 >6 1 >66 1 >67 16 FRONT OF BOARD PIN I - RI 08 + R2 RI3 R3 RI2 R 21 Rh R RIO 16 1 II R6 6 R R7 7 R 8820 708 DCC 2 737 737 737 R88-1-1K 737 737 737 17 737 36 BACK 70 FRONT 3 DECOUPLE CHIPS 17,18,1,20,22,23,2 WITH. 2 2/, F 8820 1> H + DIL0 i3 1 16, RI 737 DIL 0+ 2 )0 3 >33 116 - MODCOMP LINK BUFFER CARD I FIG.

18 - INB-A INB- R 17 1 60> RIO >18 2 61)1 RI NB- 1 2 R2 2 3>-i 707 707 707 707 II DRLI- 0 1 DRL- MSTCL- 6 RI7 8830 DRL2-1 RRL- 6> PIN I 0 8 R23 R3 3 >1 R >1 R 6>1 R6 6 7> R7 7 8> R8 8 ) 1 707 8830 1 0 11 1 2 R2 1 3 RhI >1 3 II 62> 1 RI2 >20 63> 1 RI3 >21 6>1 RI >22 6 1 6) 1 RI >23 7 1 66> 1 >2 8 16 67 > 1 RRL A >8 RRL-A >1 RRL B > RRL+ B OCP 1> RIB 8830 R20 OTP- 0> RI 8830 R2I R16 R22 8830 707 INB-A II I 0 >2 II 1 2 8830 >26 >27 II >28 >2 >30 1 >31 1 >32 16 >6 MSTCL+A )11 MSTCL-A 7 MSTCL+B MSTCL-B > OCP+A > OCP-A > OCP+B > OCP-8 >2 OTP +A > OTP -A >3 OTP+B >8 OTP-B 16 R8 -I-1K 2 8830 8830 8830 8830 R8 _ 1 1 K 707 707 17 707 RI R2 R3 R R R6- R7 R8- -(K 20 1 + R RI2 _ RI I RIO R R RI RI RI6 RI7 R18 RI R20 7 R8- (-(K 11 1 1.11.1 + R2 R23 R22 8 R 21 36 BACK 70 FRONT 3 DECOUPLE CHIPS 17,18,1,21, 22,23,2 116 MODCOMP LINK BUFFER CARD 2 FIG.