بسام عب د الكريم جاد هللا النبريص Bass am Ak J Alnabr iss Islamic University of Gaza Faculty of Engineering Computer Engineering Dept. Digital Design Lab : ECOM 2112 Fall 2016 Eng. Bassam Nabriss LAB 7 Latches & Flip Flops 11/11/2016
Objectives Become familiar with flip-flops. Implement and observe the operation of different flip-flops Theory Sequential Circuits Digital electronics is classified into combinational logic and sequential logic. Combinational logic output depends on the inputs levels, whereas sequential logic output depends on stored levels and also the input levels. The memory elements are devices capable of storing binary info. The binary info stored in the memory elements at any given time defines the state of the sequential circuit. The input and the present state of the memory element determine the output. Examples on sequential circuits are Flip-Flops, latches, counters, registers, and time state generators. There are two types of sequential circuits. Their classification depends on the timing of their signals: Synchronous sequential circuits: is achieved by a timing device called a clock pulse generator. Clock pulses are distributed throughout the system in such a way that the flipflops are affected only with the arrival of the synchronization pulse. Synchronous sequential circuits that use clock pulses in the inputs are called clocked-sequential circuits They are stable and their timing can easily be broken down into independent discrete steps, each of which is considered separately Asynchronous sequential circuits: The behavior of an asynchronous circuit depends on the order in which the inputs change. Sometimes, there is an input labeled clock, that provides some level of synchronization, but it is normally only applied to one flip-flop. In addition to this style of asynchronous circuit, you also get gate-level asynchronous circuits, which are combinatorial circuits with feedback Where the tringle in the block means input for clocks and work on rising edge, and if it was followed by circle it means that the clock works on falling edge. 1
Flip-Flops and Latches Rising Edge Falling Edge Active high Active low Flip-Flop Flip-Flop Latch Latch There are several types of flip-flops and they are S-R, J-K, D and T flip-flops, but the two most important kinds are the D and J-K flip-flops. The difference between latches and flip-flops is that the latches output essentially responds immediately to changes on the input lines where the flip-flop output is designed to change at the edge of a controlling clock signal (rising or falling). S-R latch is the first type of latches, you can implement it using NAND, or using NOR gates. Use the KL 33002 and implement the following figure, and put the following sequence for the inputs S-R, (0,0) (0,1) (1,1) (1,0) (1,1) and each case read the output Q and Q`, What you note? Types of flip flops Symbol SR JK D T Characteristic table S R Q t 0 0 Q t-1 0 1 0 1 1 X J K Q t 0 0 Q t-1 0 1 0 1 1 Q t-1` Equation Q t = S + R`Q t-1 Q t = JQ t-1` + K`Q t-1 D Q t 0 0 1 1 Q t = D T Q t 0 Q t-1 1 Q t-1` Q t = TQ t-1` + T`Q t-1 Excitation table Q t Q t-1 S R 0 0 0 x 0 0 1 1 x 0 Q t Q t-1 J K 0 0 0 x 0 1 x 1 x 1 1 x 0 Q t Q t-1 D 0 0 0 0 1 0 1 1 1 Q t Q t-1 T 0 0 0 0 1 1 1 1 0 2
Example 1, Timing diagram for the positive edge triggered D flip-flop: Timing diagram for the D latch The timing diagram for the negative and postive triggered JK flip-flop The timing diagram for the positive triggered T flip-flop 3
Example 2, 1) Convert a D-FF to a T-FF: Method A: by thinking, we want to find inverse if input is 1, and work as buffer if the input is 0, you get it? The XOR gate? the second Method is from excitation table, the system has T and Q t-1 as inputs, and has the output the D, the excitation table will be Q t Q t-1 T D 0 0 0 0 0 1 1 0 1 1 Now you should deal with D as output and Q t-1 with T as inputs, so D = Q t-1 T 2) Convert a D-FF to a JK-FF the system has J, K and Q t-1 as inputs and D as output Q t Q t-1 J K D 0 0 0 x 0 0 1 x 1 0 x 1 1 1 x 0 1 Using K-map, you will get that D = JQ t-1 ` + K`Q t-1 LAB work Construct A JK flip-flop Think, how you will construct a T flip-flop and D flip-flop 4
Exercises 1- Convert a RS-FF to a JK-FF. 2- Convert a RS-FF to a D-FF. 5