Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By 1 Chapter 8 Sequential Circuits 1
Classification of Combinational Logic 3 Sequential circuits Sequential circuits use current input variables and previous input variables by storing the information and putting back into the circuit on the next clock (activation) cycle. (Sequential circuit = Combinational logic + Memory Elements) 4 2
Memory Element A Memory Element: logic device that can store a binary information, this binary information defines the state of the circuit. Can remember value indefinitely, or change its value on command from its inputs. Current State of a sequential Circuit: Value stored in memory elements (value of state variables). State transition: A change in the stored values in memory elements thus changing the sequential circuit from one state to another state. Types of sequential circuits depending on the timing of their signals: Synchronous Asynchronous EECC341 - Shaaban 5 Memory Element states The output Q of the memory element represents the value stored in the memory element. This is also called the state variable of the memory elements. A memory element can be in one of two possible states: Q = 0 (the memory element has 0 stored), also said be in state 0. Q =1 (the memory element has 1 stored), also said to be in state 1. A sequential circuit that contains n memory elements could be in one of a maximum of 2 n states at any given time depending on the stored values in the memory elements. EECC341 - Shaaban 6 3
Memory Element commands The commands to the memory element formed by its input(s) may include: Set: Store 1 (Q=1) in the memory element. Reset: Store 0 (Q=0) in the memory element. Flip: Change stored value from 0 to 1 or from 1 to 0. Hold value: Memory value does not change. Memory Element state transition: A change in the stored value from 0 to 1, or from 1 to 0 such as that caused by a flip command. EECC341 - Shaaban 7 Synchronous Sequential circuits Synchronous Sequential circuits must employ signals that affect the memory elements only at discrete instance of time using pulses of limited duration, where one pulse represents logic 1 and another pulse represents logic 0. Synchronization is achieved by a timing device called master-clock generator. (Synchronous Sequential Circuits: Sequential circuits that have a clock signal as one of its inputs) Synchronous Sequential circuits that use clock pulses in the input of memory elements are called clocked sequential circuits. EECC341 - Shaaban 8 4
Clock Signals A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals. EECC341 - Shaaban 9 Sequential Circuit Memory Elements: (Latches, Flip-Flops) Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops. Latches: The output of a latch depends on its current inputs and on its previous inputs and its change of state can happen at any time when its inputs change. Flip-Flop: The output of a flip-flop also depends on current and previous input but the change in output (change of state or state transition) occurs at specific times determined by a clock input. EECC341 - Shaaban 10 5
Clocked sequential circuits. Memory elements used here are called flipflops. These circuits are binary cells that can store one bit of information. 11 Flip-Flops Flip-flop types: Basic flip flop circuit (latch). RS flip-flop. D flip-flop. JK flip-flop. T flip-flop. 12 6
Basic flip flop circuit (latch) 13 Basic flip flop circuit (latch) S = 1 and R = 0 Gate 1 output in complement condition: Q=1. Gate 2 in always 0 condition: Qꞌ=0. This is the Set condition. S = 0 and R = 0 Gate 1 remains in complement condition: Q=1. Gate 2 remains in always 0 condition: Qꞌ=0. This is the hold condition. S = 0 and R = 1 Gate 1 output in always 0 condition: Q=0. Gate 2 in complement condition : Qꞌ=1. This is the Reset condition. S = 0 and R = 0 Gate 1 remains in always 0 condition: Q=0. Gate 2 remains in complement condition: Qꞌ=1 This is the hold condition. S = 1 and R = 1 Gate 1 in always 0 condition: Q=0. Gate 2 in always 0 condition: Qꞌ=0. This is the illegal condition S R Q Qꞌ 1 0 1 0 0 0 1 0 (After S=1, R=0) 0 1 0 1 0 0 0 1 (After S=0, R=1) 1 1 0 0 Logic Diagram Truth Table 14 7
Basic flip flop circuit (latch) A flip-flop has two useful states, when: Q=1 and Qꞌ =0 Set state. Q=0 and Qꞌ =1 Reset state (clear). 15 Basic flip flop circuit with NAND gates Logic Diagram S R Q Qꞌ 1 0 0 1 1 1 0 1 (After S=1, R=0) 0 1 1 0 1 1 1 0 (After S=0, R=1) 0 0 1 1 Truth Table 16 8
RS flip-flop (Clocked) RS flip-flop 17 18 9
RS flip-flop (Clocked) RS flip-flop With the condition: Function Table 19 D flip-flop (gated D-latch) To eliminate the undesirable condition of the indeterminate state in the RS flip-flop. Ensures that inputs S and R are never equal to 1 at the same time. Has only two inputs: D, CP. 20 10
D flip-flop (gated D-latch) D input goes with S input, D s complement goes with R input If CP=0 gate 3 and 4 outputs =1.. And the circuit does not change state. If CP=1 if D=1 then Q=1.. (Set state). If CP=1 if D=0 then Q=0..(Clear state). (The next state = D, whether Q=1 or Q=0) 21 D flip-flop (gated D-latch) 22 11
D flip-flop D flip-flop refers to its ability to hold data into its internal storage. The CP input sometimes called G (gate) because it enables the gated latch to make possible data entry into the circuit. 23 JK Flip-Flop It is a refinement of RS flip-flop where the indeterminate state is defined here. Input J is set and K is Reset. When J=K=1 the flip-flop switches to its complement (last state is inverted): if Q=1 it switches to Q=0. if Q=0 it switches to Q=1. 24 12
JK Flip-Flop When J=K=1: then CP transmitted through one AND gate only (the one whose input is connected to flip-flop output that is presently =1): If Q=1 the upper K s AND =1 flip-flop is Cleared. If Qꞌ=1 the upper J s AND =1 flip-flop is Set. 25 JK Flip-Flop 26 13
JK Flip-Flop Problems: Because of the feedback connection in the JK flip-flop, CP will still =1 while J=K=1 will cause the output to complement again and repeat complementing until the CP=0. To avoid this, CP must have shorter time duration (pulse width) than the flip-flop delay time. This is a restrictive requirement. Solution: JK flip-flop is not constructed like this. Restriction on pulse width can be eliminated with a Master-Slave or Edge-Triggered construction. 27 T flip-flops Is a single-input version of JK flip-flop. It is obtained from JK flip-flop when both inputs are tied together. T refers to the ability of flip-flop to Toggle or complement its state. 28 14
T flip-flops When CP=1: if T=1 flip-flop complements its current state. If T=0 next state = present state (no change). ( ) 29 T flip-flops 30 15
Triggering of Flip-flops Triggering of Flip-flops Problem: The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger and the transition it causes is said to trigger the flip-flop. The feedback path between the combinational circuit and memory elements can produce instability if the outputs of the memory elements (flip-flops) are changing while the outputs of the combinational circuit that go to the flip-flop inputs are being sampled by the clock pulse. Two types of flip-flops that synchronizes the state changes during a clock pulse transition : Master-Slave Flip-Flop Edge Triggered Flip-Flop 32 16
Triggering of Flip-flops Solution: To solve the feedback timing problem is to make the flip-flop sensitive to the pulse transition rather than the pulse duration. 33 Triggering of Flip-flops Example: The D flip-flop if level sensitive (triggered on pulse duration) 34 17
Edge Triggered Flip-Flop When the clock pulse input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not affected by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs. Some edge-triggered flip-flops cause a transition on the: Positive edge of the clock pulse (positive-edgetriggered) or (Rising-edge-triggered). Negative edge of the pulse (negative-edge-triggered) or (Falling-edge-triggered). 35 The D flip-flop: Positive-edge-triggered D flip-flop Graphic Symbol 36 18
Positive-edge-triggered D flip-flop Example: Positive-edge-triggered D flip-flop. 37 comparison 38 19
Positive-edge-triggered D flip-flop 39 Positive-edge-triggered D flip-flop Cp=0 S=R=1 (steady state) 40 20
Positive-edge-triggered D flip-flop S=0 & R=1 Q=1..(set) S=1 & R=0 Q=0..(Clear) 41 Positive-edge-triggered Negative-edge-triggered D flip-flop Graphic Symbol 42 21
Master-Slave Flip-flops Master-Slave Flip-flops It is constructed from 2 flip-flops: one serves as master and the other as slave. The following is RS master-slave flip-flop: 44 22
RS master-slave flip-flop It consists of: master flip-flop, slave flip-flop and an inverter. When CP=0: Slave is Enabled Q = Y & Qꞌ = Yꞌ. Master is Disabled. When CP=1: R & S inputs transmitted to Master. Slave Disabled. 45 RS master-slave flip-flop 46 23
RS master-slave flip-flop Timing Relationship: Assume the flip-flop Is in clear state, so Q=Y=0 When CP=0 : - No change. When CP changes from 0 to 1: Master Set & Y=1. 47 J-K Master-Slave Flip-Flop Solves the problem in the problem when both S=R=1 - When J=K=1 the last state is inverted. 48 24
J-K Master-Slave Flip-Flop 49 Analysis of Clocked Sequential Circuits 25
Analysis of Clocked Sequential Circuits Behavior of sequential circuit is determined by: Inputs. Outputs. Flip-flop state. (Outputs & Next state ) are functions to ( inputs & present state). Analysis is to obtain: table, diagram for time sequence of (inputs, outputs, states), write Boolean expressions (to describe behavior of circuit) that include necessary time sequence. 51 Sequential circuit example The following clocked sequential circuit consists of: Two D flip-flops A and B, Input x. Output Y. 52 26
53 1- State equation Is an algebraic expression that specifies the condition for a flip-flop state transition: Left side: denotes the next state of flip-flop. Right side: Boolean expression that specifies present state & input conditions to make next state =1. Next state equations: A(t+1)= A. x + B. X B(t+1)= Aꞌ. x Present state of the output: Y= (A + B) xꞌ 54 27
2- State Table Enumerates the sequence of inputs, outputs and flip-flop states. It consists of 4 sections : Current state. Input. Next state (must satisfy the state equation). Output. First: we should list all possible combinations of current states and inputs. Second: next-state and output values are determined from state equations. Number of rows (combinations) = 2 m + n, where: m :number of flip-flops. n: number of inputs. 55 2- State Table In the example there are: Two flip-flops, so m=2. One input (x), so n=1. Then we have 2 3 combinations 56 28
2- State Table Next state equations: A(t+1)= A. x + B. X B(t+1)= Aꞌ. x Present state of the output: Y= (A + B) xꞌ 57 3- State Diagram The information in the state table can be represented graphically: State is represented be a circle. Transition between states represented by directed lines. 58 29
3- State Diagram Binary numbers inside circles identifies flipflop states. Binary numbers on lines separated by / : first number : input. Second number: output. Directed line connecting circle with itself means no change. 59 4- Input Functions The part of the circuit that generates the inputs to flip-flop are described algebraically by a set of Boolean functions. Also called input equations. We use two letters: First is the name of the input. Second is the name of the flip-flop. 60 30
4- Input Functions For the following circuit, input functions are: JA= B Cꞌ x + Bꞌ C xꞌ KA= B + y 61 Example: 4- Input Functions Write the input functions For the circuit in the following slide. 62 31
63 4- Input Functions Solution: 64 32
Example 1 65 Example 2 66 33
Example 3 Note: 67 Analysis with JK and other flip-flops 34
Analysis with JK and other flip-flops In D flip-flop we can derive the next state directly from next state equation. In other types we must return to the characteristic table: Obtain the binary values of each flip-flop input function in terms of the current state and input variables. Use the corresponding flip-flop characteristic table to determine the next state. 69 characteristic tables 70 35
characteristic tables 71 Example 72 36
1- input functions Flip-flop A: JA= B KA= B xꞌ Flip-flop B: JB= xꞌ KA= A x =(Aꞌ x + A xꞌ) 73 2- state table 74 37
3- state diagram 75 Excitation table 38
Excitation table characteristic table: Useful for analysis and for defining the operation of flip-flop. Specifies next state when inputs and current state are known. But, Some times we only know the transition from current state to next state and want to find the flip-flop input conditions that causes the required transition. So we use Excitation table. 77 Excitation table 78 39