A Simulatio Experimet o a Built-I Self Test Equipped with Pseudoradom Test Patter Geerator ad Multi-Iput Shift Register (MISR) Afaq Ahmad Departmet of Electrical ad Computer Egieerig College of Egieerig, Sulta Qaboos Uiversity P. O. Box 33, Postal Code 23; Muscat, Sultaate of Oma Telephoe: (+ 968) 244 327 Fax: (+968) 244 346 afaq@squ.edu.om ABSTRACT This paper ivestigates the impact of the chages of the characteristic polyomials ad iitial loadigs, o behaviour of aliasig errors of parallel sigature aalyzer (Multi-Iput Shift Register), used i a LFSR based digital circuit testig techique. The ivestigatio is carried-out through a extesive simulatio study of the effectiveess of the LFSR based digital circuit testig techique. The results of the study show that whe the idetical characteristic polyomials of order are used i both pseudo-radom test-patter geerator, as well as i Multi-Iput Shift Register (MISR) sigature aalyzer (parallel type) the the probability of aliasig errors remais uchaged due to the chages i the iitial loadigs of the pseudo-radom test-patter geerator. KEYWORDS LFSR, MISR, BIST, Characteristic Polyomial, Primitive.0 INTRODUCTION Reliability is oe of the mai cosideratios i ay circuit desig. It ivolves a correct ad predictable behaviour of the circuit accordig to desig specificatios over a sufficietly log period of time. To achieve this goal, the logic-circuit desig is aimed at a error-free circuit operatio. Ufortuately, i spite of all possible care beig bestowed o desig ad simulatio, hardware faults resultig from physical defects (e.g. mask defects, maufacturig process flaws) will occur i the hardware implemetatio of the logic circuit. Hece, whe a fault occurs ayway, oe must be able to detect the presece of the fault ad, if desired to pipoit its locatio. This task is accomplished by testig the circuit. System maiteace draws heavily upo the testig capability of the logic system [], [2]. Digital circuit maufacturers are well aware of the eed to icorporate testability features early i the desig stage, or otherwise they have to icur higher testig costs, subsequetly. A empirical relatioship, that have bee used for estimatig the cost of fidig a faulty chip, idicates that the cost icreases by a factor of 0, as fault fidig advaces from oe level to the ext [3] [7]. However, recet studies have show that the cost of testig ad fault fidig, at system ad field level, is higher tha this factor of 0 ad icreases expoetially [7] [9]. Thus, if a fault ca be detected at chip or board level, the sigificatly larger costs per fault ca be avoided. This is the prime reaso that attetio has ow focused o providig testability at chip, module or eve at board level.
Ay test methodology usually cosists of (i) A test strategy for geeratig the test-stimuli, (ii) A strategy for evaluatig output resposes, ad (iii) Implemetatio mechaisms to realize the appropriate strategies i test-geeratio ad respose evaluatio. Preset day philosophy to achieve ecoomical ad cost effective testig of Very Large Scale Itegratio (VLSI) compoets ad systems is to provide o-chip testig. Though these techiques ivolve additioal chip area for the added test circuitry, they have provided reasoable testability levels. I fact it has bee reported that, for about 20% additioal silico area required, more tha 98% of the chip desig ca be checked usig structured Desig For Testability (DFT) approaches [7] []. As a atural outcome of the structured desig approach for DFT, built-i testig has draw cosiderable attetio. Usually a built-i test methodology is defied as the oe that icorporates both test-patter geeratio ad respose data compressio mechaisms iterally i the chip itself. If this methodology is self-sufficiet i detectig the faults of its iteral test circuitry also, the such a methodology is referred to as Built-I Self-Test (BIST) i test literature. The mai emphasis i BIST desigs is that to provide close to oe hudred percet testig of combiatioal circuits [0], [2]. I particular, pseudo-radom test-patter geeratio followed by the compressio of respose data by sigature aalysis has become a stadard form of testig i BIST eviromet. Liear Feedback Shift Registers (LFSRs) have bee proposed as a itegral part of a sequetial logic desig, such that they ca be used to both geerate ad compact the results of a test. Udoubtedly, a LFSR based pseudo-radom test-patter geeratio is a extremely simple tool for geeratig desired sequece as well as the legth of the test-stimuli. May estimatio schemes are readily available for computig the legth of test patters where the desired sequece of the test-patters ca be obtaied by the predetermied seed of the LFSRs. Further, the effective testig of large circuits uses the cocept of pseudoexhaustive testig where the priciple of divide ad coquer is applied [3] [9]. Difficulty arises whe the resultig respose data obtaied from the Circuit Uder Test (CUT) is compressed ito small sigatures usig Sigature Aalyzer (SAZ). Although, this scheme of SAZ is easily implemeted by a LFSR either i the form of Sigle Iput Shift Register (SISR) serial SAZ or MISR- parallel SAZ. But this leads to loss of iformatio, due to the erroeous respose patters that get compressed ito the same sigature as the fault-free sigature of the CUT. Thus, some of the faults might go udetected due to this maskig pheomeo. This compressio ca further reduce the fault-coverage i the BIST scheme. This problem of error maskig is called aliasig [20] [25]. Methods to determie the extet of fault escape caused by a respose compressor are ot readily available. However, various attempts have bee made to aalyze ad improve the basic SAZ's realizatio methods [26] [33]. The ed goal of the above schemes, idividually, or with a combiatio of these, is to reduce the deceptio volume [26]. Methods that cosider both, the test patter geerator ad respose data compressor factors i totality ad simultaeously, i aalyzig the aliasig behaviour of the circuit, are ot available. There is a growig eed for such a approach, which comprehesively looks at aliasig problems with respect to both test patter geerator ad respose data compressor ad reflects the true aliasig characteristics. This is the prime ustificatio of the research work i this area. Therefore, towards this directio a research work have bee doe [34], [35]. Through these papers, differet studies were carried out to ivestigate the roles of characteristic polyomials used i Pseudo-Radom Test-Patter Geerator (PRTPG) as well as i SAZ, ad iitial loadig of PRTPG with the behaviour of aliasig errors of SAZ. The work cotaied i the papers [34], [35] used separate differet structures (iteral ad exteral exclusive-or types) of LFSRs. However, both the papers cosidered SISR type of SAZ. This paper is a extesio of the previous research where MISR type of SAZ is used. I this work exteral exclusive-or type ad iteral exclusive-or type LFSR is used i PRTPG ad MISR respectively. The results of the study show that the probability of aliasig errors remais uchaged due to the chage i the iitial loadig whe
the idetical characteristic polyomials of order are used i both PRTPG, as well as i SAZ (MISR type). 2.0 MATHEMATICAL CHARACTERIZATION OF LFSR I this sectio we cosider briefly the mathematical backgroud, defiitios ad theorems related to a LFSR. Details ca be foud i literatures [36] [39]. Basic defiitios ad theorems are give below for the sake of completeess. Let [ A] represet the state trasitio matrix of orderr, for a stage LFSR show i Figure. Assume the state at ay time t be represeted by vector [Q(t)] = [q (t),...,q (t),...,q 2 (t), q (t)] (whichh is effectively the cotets of the LFSR) where each q represets the state of the th stage of the LFSR. Further, let the LFSR feedback stages be umbered from C 0 to C, proceedig i the same directio as the shiftig occurs i.e. left to right. Let the preset state of the LFSR be represeted by [Q(t)] ad, oe clock later, the ext state by [Q(t+)]; the the relatioship betwee the two states is give by Equatio (). Figure. A -bit LFSR model ( ) 0 0 0 0 0 0 0 0 0 0 0 0 where, c = 0 or, for - ad c =, for =. (2) I Equatio (2), the values of C show the existece or absece of a feedback coectio from the th stage of the LFSR. Equatio () ca be writte as [Q(t+ +)] = [A][Q(t)] (3) If [Q] = [Q(0)] represets a particular iitial loadig of the LFSR, the the sequece of states through which the LFSR will pass durig successive times is give by [Q(t)], [A][Q(t)], [A] 2 [Q(t)], [A] 3 [Q(t)],
Let the matrix period be the smallest iteger p for which [A] p =I, where I is a idetity matrix. The [A] p [Q(t)] = [Q(t)] for ay o zero iitial vector [Q(0)], idicatig the cycle legth (or period) of the LFSR is p. Thus, o the basis of this property of periodicity of LFSR ad Equatio (3), it follows that [Q(t)] = [Q(t+p)] = [A] p [Q(t)] (4) Defiitio : The cycle legth p, for vector [Q(0)] = 0 is always, which is idepedet of matrix [A]. Defiitio 2: The period p of a bit LFSR will oly be maximal whe p = m = 2 -. For the matrix [A] of the LFSR, the characteristic equatio is give by Determiat [A-I] = 0. Thus, C C C 2... C i C2 C F()= 0... 0 0 0 (5) M M M... M M 0 0 0 L 0 0 0 0 L0 Defiitio 3: For the matrix [A] of a LFSR, the polyomial of {determiat [A-I]}is called the characteristic polyomial F() of the LFSR ad ca be writte as F() = + C ; C =. (6) = Let, T() deote the characteristic polyomial of a stage LFSR used i PRTPG. Let, {a -, a - 2,...,a -+,a - } be the iitial state of the shift register. The sequece of umbers a 0, a, a 2,... a q... ca be associated with a polyomial, called geeratig fuctio M(), by the rule M() = a 0 + a +... + a q q + Let {a q } = a 0, a, a 2,... represet the output sequece geerated by a LFSR used as PRTPG, where a i = 0 or. The this sequece ca be represeted as M q ( ) = a q (7) q= 0 From the structure of the type of the LFSR show i Figure 2, it ca be see that if the curret state of the th flip-flop is a q-, for =, 2,...,, the by the recurrece relatio a q = C = a q (8) Substitutig (8) i (7) M ( ) = q= 0 = C a q q (9)
Or, by solvig for geeratig fuctio, it ca be show that M() is give by M ( ) = = C - (a + - + a - + C = - + +... + a - - ) (0) M () = Or, = C (a - + a - + + +... + C = - a - ) () B( ) M ( ) = T ( ) (2) Thus, the PRTP (represeted by polyomial M(), geerated by the LFSR ca be obtaied through the log divisio of the fuctio B() by T( (). Therefore, it ca be implied from the Equatio () that the geerated sequece M() is fuctio of iitial loadig as well characteristic polyomial of the LFSR used i the realizatio of the PRTPG. 3.0 MULTI-INPUT SHIFT REGISTER (MISR) MODEL Figure 2 shows a typical MISR cofiguratio. This cofiguratio of MISR is based o the iteral-exor. I the figure, deotes the legth of the MISR, i.e., the umber of FFs i the register. Also, the LFSR feedback stages be umbered from C to C, are the biary coefficiets of the characteristic polyomial P (of the MISR. Figure 2. A -bit MISR model P() = + C = (3) Let f i be the cotet of the i-th FF, the the state of the MISR
(i.e., the sequece r = r + r - + + r 2 + r ) ca be represeted by the state polyomial s() = r - + r - -2 + + r 2 + r (4) Similarly, a -bit iput sequece (d = D + D - + + D 2 + D ) ca be represeted by the iput polyomial. d() = D - + D - -2 + + D 2 + D (5) The sigature obtaied by SAZ (ay SISR or MISR) is defied as the fial state of the register after the iput sequece d has bee etered ito the register. The the MISR sigature ca be give as s(x) = D(x) mod P(x) (6) Thus, the theory behid the use of the LFSR for SAZ is based o the cocept of polyomial divisio process, where the remaider left i the register after the last bit of iput data is sampled, correspods to the fial sigature. Whereas, the output sequece from the th bit of the LFSR defies the quotiet, QO of the divisio. I geeral, the shift register is iitialized by the reset or by parallel load fuctio of the register, at a time of fault-free evaluatio as well as every time whe a ew fault is iected i the CUT. Assume that the CUT is of combiatioal ature with primary iputs ad k primary outputs. If the iitial state of the LFSR is all 0 s, let the fial state of the LFSR be represeted by the polyomial s(). The it ca be show that these polyomials are related by the equatio d( ) P( ) s( ) = QO( ) + (7) P( ) where, P() is the characteristic polyomial of the LFSR structure used i MISR-SAZ. Hece a LFSR carries out polyomial divisio o the iput data stream by the characteristic polyomial, producig a output stream correspodig to the quotiet QO() ad remaider s(). 3.0 SIMULATION STUDY The testig model employed i the simulatio study for PRTPG ad MISR is as described i sectio 2 ad show i Figures ad 2. Various combiatioal circuits have bee simulated usig the maufacturer's logical diagrams with gate level descriptio. A sigle stuck-at fault model is assumed. Where, s-a-0 ad s-a- faults are postulated o each idividual, N L, braches of the each CUT. I the case of each -iput CUT, idetical all possible characteristic polyomials of order are idividually applied to PRTPG ad MISR-SAZ as well. All possible iitial loadig of PRTPG, 2 -, are exhausted to moitor the aliasig error behaviour of MISR- SAZ. These characteristic polyomials are geerated usig the algorithms developed ad reported i papers [2], [40] ad [4]. To make it more readable the simulatio procedure used to study the aliasig behaviour is described below.
Simulatio procedure Begi (For a -iput CUT) NL = total umber of braches i the CUT; NP = total umber of possible characteristic polyomial of order, over GF(2); L i = is the periodicity of i th characteristic polyomial of order ; NS = total umber of possible iitial loadig {NS = 2 -, excludig S =[000..0]}; RC = is the aliasig cout; For i = to NP, do For r = to NS, do Begi Choose i th characteristic polyomial for PRTPG as well as for SAZ {i.e. T i () ad P i ()}respectively; Choose r th iitial loadig S r ; Geerate test stimuli of legth L i ; Choose circuit respose d g {fault-free circuit respose}; Compute s g {fault-free sigature}; For t = to 2NL, do Begi Iitialize aliasig cout RC; Choose circuit respose d ft {d f has fault umber iserted, d f2 has fault umber 2 iserted, etc.}; Compute sigature s ft {sigature whe the t th fault is iserted}; Compare s ft, with s g if s ft s g the, icremet aliasig cout RC; Ed do; Write aliasig cout {oe each for s r, T i (), P i ()}; Ed do; Ed. The above procedure is used to observe the effect of the characteristic polyomials used i PRTPG as well as i MISR-SAZ alog with the iitial loadig of PRTPG o aliasig couts of MISR-SAZ. The aliasig couts for the circuits of Table were moitored for the sets of all NP ad NS of order. Table. Summary of simulated circuits Circuit Number Module of IC Number C- SN-74LS39 DUAL 2-TO-4 LINE DECODER/ DEMULTIPLEXER C-2 SN-74LS82 2-BIT BINARY FULL ADDER C-3 SN-74H87 4-BIT TRUE/ COMPLEMENT, ZEO/ ONE ELEMENT Circuit Specificatios (-iputs, k-outputs) 3-iputs; 4-outputs 9-gates 5-iputs; 3-outputs 2-gates 6-iputs; 4-outputs 4-gates Number of Faults Iected NP / NS of order 58 2 / 7 48 6 / 3 64 6 / 63
The observed results demostrates that whe the idetical characteristic polyomials are used i both the PRTPG ad MISR-SAZ, the ay chage i iitial loadig of PRTPG does ot chage the value of aliasig cout. Due the complexity of the result sets ad space oly a cadidate of result for circuits summarized i Table are show i Tables 2 to 4. I Tables 2 4 the aliasig cout is show. These values of aliasig couts remai uchaged for all the possible chages of iitial loadig of PRTPG. Table 2. Aliasig errors for all possible NS for circuit C- PRTPG T() MISR-SAZ P() ++ 4 + 3 + 4 ++ 3 9 3 + 2 + 3 3 9 Table 3. Aliasig errors for all possible NS for circuit C-2 PRTPG T() MISR-SAZ P() ++ 3 + 2 + 3 + 3 + 5 4 2 + 2 + 5 7 5 + 2 + 3 + 4 + 5 3 9 ++ 3 + 4 + 5 4 6 ++ 2 + 4 + 5 0 8 ++ 2 + 3 + 5 7
Table 4. Aliasig errors for all possible NS for circuit C-3 PRTPG T() MISR-SAZ P() ++ 4 + 3 + 4 + 5 + 6 24 9 ++ 6 6 8 + 2 + 3 + 5 + 6 7 22 ++ 4 + 5 + 6 2 6 ++ 3 + 4 + 6 23 26 ++ 2 + 5 + 6 9 28 4.0 CONCLUSIONS It has bee demostrated through this simulatio study that the chage of the iitial loadig of PRTPG does ot have ay impact o the effectiveess of a LFSR based digital circuit testig techique that uses idetical characteristic polyomials i both the PRTPG ad MISR-SAZ as well. Thus, this result restricts the outright use of the results of fidigs; that the effectiveess of LFSR based digital circuit testig techiques ca be improved by chagig the iitial loadig of PRTPG. Thus, for effective use of iitial loadig of PRTPG of LFSR based digital circuit testig techique, it is essetial to aalyze the role of characteristic polyomials used i PRTPG as well as i MISR-SAZ. Although, our ivestigatio is limited with small sizes of circuits but the tred of results suggests for further through aalytical ivestigatio. 5.0 REFERENCES [ ] Ahmad, A., Reliability Computatio of Microprocessor Based Mechatroic Systems A Highlight for Egieers, to appear i: Caledoia Joural of Egieerig (CJE) vol. 6, o. 2, pp. 7, 200. [ 2] Ahmad, A., Dawood Al-Abri, Desig of a Optimal Test Simulator for Built-I Self Test Eviromet, To appear i: The Joural of Egieerig Research, vol. 7, o. 2, pp. 69 79, 200. [ 3] Muehldrof, E.I. ad Savakar, A.D. 98. LSI Logic Testig - A Overview. IEEE Trasactios o Computers, C-30(), pp -7, 98. [ 4] Beets, R. G.982. Itroductio to Digital Board Testig. Crae Russak Ltd., New York. [ 5] Abadir, M. S., ad Reghbati, H. K., LSI Testig Techiques. IEEE Micro, 3(), pp 34-5, 983. [ 6] Williams, T. W. ad Parker, K. P., Desig for Testability - A Survey, IEEE Proceedigs, 7(), pp 98-2, 983.
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ACKNOWLEDGEMENTS The ackowledgemets are due to authorities of Sulta Qaboos Uiversity (Sultaate of Oma) for providig geerous research support grats ad eviromets for carryig out the research works. Author (Short Biography) Afaq Ahmad belogs to departmet of Electrical ad Computer Egieerig departmet at Sulta Qaboos Uiversity, Sultaate of Oma. He holds B.Sc. Eg., M.Sc. Eg., DLLR ad Ph.D. degrees. Ahmad did his PhD from IIT Roorkee, Idia i 990. Before oiig Sulta Qaboos Uiversity, Dr. Ahmad was Associate Professor at Aligarh Muslim Uiversity, Idia. Prior to startig carrier at Aligarh, he also worked as cosultat egieer with Light & Co., lecturer with REC Sriagar ad seior research fellow with CSIR, Idia. Dr. Ahmad is Fellow member of IETE (Idia), seior member of IEEE Computer Society (USA) ad life member of SSI (Idia), seior member IACSIT, member IAENG ad WSEAS; He has published over 00 techical papers. At preset he is associated as editors ad reviewers of may reputed ourals. He has delivered may keyote, ivited addresses, extesio lectures, orgaized cofereces, short courses, ad coducted tutorials at various uiversities of globally repute. He chaired may techical sessios of iteratioal cofereces, workshops, symposiums, semiars, ad short courses. He has udertake ad satisfactorily completed may highly reputed ad challegig cosultacy ad proect works. His research iterests are: fault diagosis ad digital system testig, data security, graph theoretic approach, microprocessor based systems ad computer programmig. Dr. Ahmad s field of specializatio is VLSI testig ad fault-tolerat computig.