Control Unit Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN
Large Digital Systems In both combinational and sequential circuit design: small circuits via gate-level design (truth tables, K maps, etc) large circuits via block-level design (MSI components, etc.) However, larger digital systems need more abstract and systematic design techniques. One such systematic design method has the following characteristics: top-down approach separation of controller from controlled hardware develop an overall architecture (at block levels) before proceeding into the details of hardware. 2
Top-Down Approach Top-down approach is immensely important for large complex system (whether hardware, software, or manual systems). Emphasis on macroscopic view, starting from original problem and gradually refine it towards solution. Steps for a top-down design procedure: Specify the problem clearly (at global/top level without unnecessary details). Break the problem into smaller sub-problems. Repeat the process until subproblems are small enough to be solved directly (implementable). 3
Controller & Data Processor Digital systems are typically processors of information. They store data through flip-flops, registers and memory, and process them using combinational circuits like adders, multipliers, etc. These processing may pass through complicated sequences. A digital system consists of two components A control algorithm (controller) and An architecture (data processor) Status condition External command Control unit (Controller) Commands Input data 4 Data Processor (Architecture) Output data
Controller & Data Processor Separation of the controller operations from the data processing operations Control operations give commands that direct the data processing operations to accomplish the desired tasks. Data processing operations manipulates the data according to requirements. A mechanical analogy: Automobile. Car (data processor): transports people from one location to another. Driver (controller): gives instructions to car to achieve objective. 5
Flowcharts Flowcharts: a tool for precise description of algorithms/procedures. Specify tasks to perform and their sequencing. Main symbols: Operation box: contains tasks/operations to perform. Decision box: alternative actions based on decisions to be taken. Arrows: indicate appropriate sequencing. 6
Flowcharts Flowcharts can be used to implement complex decisions. nice colour & style? no yes affordable? no reject made in Europe? no poor yes insulting yes test out fitting? acceptable BF s opinion? get BF to buy encouraging 7
ASM Charts Algorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems. Major differences from flowcharts are: uses 3 types of boxes: state box (similar to operation box), decision box and conditional box contains exact (or precise) timing information; flowcharts impose a relative timing order for the operations. From the ASM chart it is possible to obtain the control the architecture (data processor) 8
Components of ASM Charts The state box is rectangular in shape. It has at most one entry point and one exit point and is used to specify one or more operations which could be simultaneously completed in one clock cycle. state one or more operations binary code 9
Components of ASM Charts The decision box is diamond in shape. It has one entry point but multiple exit points and is used to specify a number of alternative paths that can be followed. deciding factors deciding factors
Components of ASM Charts The conditional box is represented by a rectangle with rounded corners. It always follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box. conditional operations
ASM Charts: An Example An example: A is a register; A i stands for i th bit of the A register. A = A 4 A 3 A 2 A E and F are singlebit flip-flops. T T Initial state S A F A A + A 2 E E A 3 2 T 2 F
Register Operations Registers are present in the data processor for storing and processing data. Flip-flops (-bit registers) and memories (set of registers) are also considered as registers. The register operations are specified in either the state and/or conditional boxes, and are written in the form: destination register function(other registers) where the LHS contains a destination register (or part of one) and the RHS is some function over one or more of the available registers. 3
Register Operations Examples of register operations: A B Transfer contents of register B into register A. A Clear register A. A A Decrement register A by. 4
Timing in ASM Charts Precise timing is implicitly present in ASM charts. Each state box, together with its immediately following decision and conditional boxes, occurs within one clock cycle. A group of boxes which occur within a single clock cycle is called an ASM block. 5
Timing in ASM Charts T Initial state S A F T A A + 3 ASM blocks A 2 E E A 3 6 T 2 F
Timing in ASM Charts Operations of ASM can be illustrated through a timing diagram. Two factors which must be considered are operations in an ASM block occur at the same time in one clock cycle decision boxes are dependent on the status of the previous clock cycle (that is, they do not depend on operations of current block) 7
Timing in ASM Charts clock 2 3 4 5 6 7 8 9 2 3 states T T T T T T T T T T 2 T T T input S= S= S= register values A= F= A= E= A=2 E= A=3 E= A=4 E= A=5 E= A=6 E= A=7 E= F= Operations A F A A+ E A A+ E A A+ E A A+ E A A+ E A A+ E A A+ E F A= A 4 A 3 A 2 A 8
Timing in ASM Charts clock 2 3 4 5 6 T T A= A 4 A 3 A 2 A Initial state S A F A A + A 2 E E T 2 A 3 F states T T T T T T input S= S= S= register values Operations A F A= F= A= E= A A+ E A=2 E= A A+ E A A+ Operations F E 9A A+ A A+ E E A=3 E= A A+ E A A+ E clock 7 8 9 2 3 states T T T T 2 T T T input register values A=4 E= A=5 E= A=6 E= A=7 E= F=
ASM Chart => Digital System ASM chart describes a digital system. From ASM chart, we may obtain: Controller logic (via State Table/Diagram) Architecture/Data Processor Design of controller is determined from the decision boxes and the required state transitions. Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes. 2
ASM Chart => Controller Procedure: Step : Identify all states and assign suitable codes. Step 2: Draw state diagram. Step 3: Formulate state table using State from state boxes Inputs from decision boxes Outputs from operations of state/conditional boxes. Step 4: Obtain state/output equations and draw circuit. 2
ASM Chart => Controller T T T Initial state S A F A A + A 2 E E T 2 A 3 F T T 2 22 Assign codes to states: T = T = T 2 = Present Next state inputs state + G G S A 2 A 3 G G + outputs T T T 2 X X X X X X X X X X X Inputs from conditions in decision boxes. Outputs = present state of controller.
ASM Chart => Architecture/Data Processor Architecture is more difficult to design than controller. Nevertheless, it can be deduced from the ASM chart. In particular, the operations from the ASM chart determine: What registers to use How they can be connected What operations to support How these operations are activated. Guidelines: always use high-level units simplest architecture possible. 23
ASM Chart => Architecture/Data Processor Various operations are: Counter incremented (A A + ) when state = T. Counter cleared (A ) when state = T and S =. E is set (E ) when state = T and A2 =. E is cleared (E ) when state = T and A2 =. F is set (F ) when state = T2. Deduce: One 4-bit register A (e.g.: 4-bit synchronous counter with clear/increment). Two flip-flops needed for E and F (e.g.: JK flip-flops). 24
ASM Chart => Architecture/Data Processor start S A 3 Controller Clk T T (A A + ) when state = T. (A ) when state = T and S =. (E ) when state = T and A 2 =. A 2 T 2 J Q E K J Q F A 4 A 3 A 2 4-bit syn. counter A A count CP clear 25 clock K
Implementing the Controller Once the state table is obtained, the controller can be implemented using one of these techniques.. Traditional method: With JK flip-flops. design done at gate level. suitable for small controllers. procedure: prepare state table, use K-maps to obtain nextstate/output functions. 2. Decoder + D flip-flops suitable for moderately large controllers. procedure: use decoder to obtain individual states; from the state table, obtain the next-state functions by inspection. 26
Implementing the Controller 3. Multiplexers a more structured approach to implement controller. suitable for moderately large controllers. three level structure: first level consists of multiplexers that determine the next state of the register; second level is a register that holds the present state; third level has a decoder to provide separate output for each controller state. 27
Implementing the Controller 4. One flip-flop per state also known as One-Hot Spot Method of ASM synthesis. procedure: allocate one flip-flop per state; from state table, determine the formulae to set each flip-flop; must ensure that controller is properly initialised. 5. PLA/ROM highly regular approach. ROM approach uses a very simple table lookup technique but suffers from large number of don t care states. PLA can handle don t care states well but design method is still at gate-level. 28
Implementing Controller: With JK Flip-flops State table obtained from ASM chart: Present Next state inputs state outputs G G S A 2 A 3 + G + G T T T 2 X X X X X X X X X X X Corresponding state table using JK flipflops: Present Next state inputs state G G S A 2 A 3 G + + G 29 Flip-flop inputs JG KG JG KG X X X X X X X X X X X X X X X X X X X X X X X
Implementing Controller: Decoder + D Flip-flops The flip-flop input functions can be obtained directly from the state table by inspection. This is because for the D flip-flops, the next state = flipflop D input. Decoder is then used to provide signals to represent different states.? D Q G? D Q G 2x4 decoder T T unused T 2 clock 3
Implementing Controller: Decoder + D Flip-flops Given the state table: Present Next state inputs state + G G S A 2 A 3 G G + outputs T T T 2 X X X X X X X X X X X We can directly determine the inputs of the D flipflops for G and G. DG = T.A 2.A 3 DG = T.S + T3
Implementing Controller: Decoder + D Flip-flops Flip-flop input functions: DG = T.A2.A3 DG = T.S + T Circuit: A 2 D Q G S A 3 D Q G 2x4 decoder T T 2 T unused clock 32
Implementing Controller: One Flip-flop per State Require n flip-flops for n states; each flip-flop represents one state. (Other methods: n flipflops for up to 2n states.)? D Q T? D Q T : : clock 33
Implementing Controller: One Flip-flop per State Formulae for next state can be obtained directly from state table:. If there is only one line going into the state, then formula = input condition ANDed with the previous state. 2. If there are more than one line, then formula = Ored of all the conditions found in () 34
Implementing Controller: One Flip-flop per State State table: State diagram: Present state inputs S A 2 A 3 Next state S= A 2 = S= T X X T T X X T T X X T T X T T X T 2 T 2 X X X T T T T 2 A 2 =, A 3 = A 2 =, A 3 = Flip-flop input functions: DT = T 2 + S'.T DT = S.T + A 2 '.T + A 2.A 3 '.T = S.T + (A 2.A 3 )'.T DT 2 = A 2.A 3.T 35
Implementing Controller: One Flip-flop per State Circuit diagram below. To initialized to state T, set flip-flop of T to and clear the rest to zero. preset S D Q T D Q T A 2 A 3 D Q T 2 DT = T 2 + S'.T DT = S.T + (A 2.A 3 )'.T DT 2 = A 2.A 3.T 36 clock clear
Implementing Controller: One Flip-flop per State Alternative: Use Q' output for T, and input function for T is complemented. To initialise, clear all flipflops to zero. S D Q Q' T D Q T DT = (T 2 + S'.T )' DT = S.T + (A 2.A 3 )'.T DT 2 = A 2.A 3.T A 2 A 3 37 clock clear D Q T 2
Implementing Controller: Multiplexers Purpose of multiplexer is to produce an input to its corresponding flip-flop equals to the value of the next state. The inputs of multiplexers are determined from the decision boxes and state transitions in the ASM chart. 38
Implementing Controller: Multiplexers Example : Given the state table. Reformat the state table. Present Next state inputs state + G G S A 2 A 3 G 39 G + X X X X X X X X X X X Present state Next state G G G + + G S' S A 2 ' Multiplexer Input inputs conditions MUX MUX?? A 2. A 3 '?? A 2. A 3??
Implementing Controller: Multiplexers Obtain multiplexer inputs: Present state Next state G G G + + G S' S A 2 ' Multiplexer Input inputs conditions MUX MUX S A 2. A 3 ' A 2. A 3 A 2 ' + A 2. A 3 ' + A 2. A 3 = A 2. A 3 4
Implementing Controller: Multiplexers Draw circuit: A 2 A 3 S MUX 2 3 S S 2 3 S S MUX clock D Present state Multiplexer inputs G G MUX MUX T S T A 2. A 3 T 2 Q G 2x4 decoder T T D Q T 2 G Determine next state of register Hold present 4 state
Implementing Controller: Multiplexers Example 2: T w T x T 3 T 2 y y z z Present state Next state G G + G G + Input conditions w' w x x' y' y.z' y.z y'.z y y'.z' Present state Multiplexer inputs G G MUX MUX T w T x+x'= x' T 2 y.z' + y.z = y T 3 y + y'.z' 42 = y + z' y.z y'.z + y'.z' = y'
Implementing Controller: Multiplexers Present state Multiplexer inputs G G MUX MUX T w T x' T 2 y y.z T 3 y + z' y' y z' y z y w x' y' MUX 2 3 S S 2 3 S S MUX clock D 43 Q G 2x4 decoder T T D Q T 3 G T 2
Implementing Controller: PLA/ROM Similar to the design using D flip-flops and a decoder. The only difference is PLA essentially replaces the decoder and all the gates in the inputs of the flipflops. External command PLA/ROM Commands to architecture Present state Next state Register to represent 44 states