RPI Rensselaer Polytechnic Institute Computer Hardware Design ECSE 4770 Report Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory Name: Walter Dearing Group: Brad Stephenson David Bang Sung K Park TA: Chao Ling Group: 3A Date: 11/18/03 Instructor: John F. McDonald
Table of Contents ABSTRACT... 3 PARTS LIST... 3 DESCRIPTION OF INTERNAL CONTROLLER OPERATION... 4 INTRODUCTION... 4 SWITCH DEBOUNCING AND OTHER SWITCH CONSIDERATIONS... 4 POWER-UP RESET CIRCUITRY... 6 SA PULSE... 6 OUTPUT LATCHING... 7 STOPWATCH CONTROLLER / TIMING CONSIDERATIONS... 7 CONCISE DESCRIPTION OF DEBUGGING PROCESS / NECESSARY REVISIONS... 14 RICHARDS FLOW DIAGRAM... 16 STATE DIAGRAM... 17 FULL LOGIC SCHEMATIC... 18 CONCLUSION... 19 **INCLUDED IN APPENDIX XILINX LOGIC DIAGRAMS 2
Abstract This lab focuses on a Xilinx Richards Controller, a counter-based state machine implementation. The purpose is to download the design hardwired in lab two to a FPGA. The circuit should perform the same functions as in lab 2, but should be implemented strictly in software, namely Xilinx. Major considerations during the lab are timing and input/output. Logic analysis is also stressed. Analysis and debugging is a major part of any design project, and is no exception here. Parts List In Xlinx: 1 - X74_163 13 - Inverters 2 4 input AND gates 3 2 input OR gate 2 4 input NAND gate 4 2 input NAND gate 2 X74_42 2 X74_151 6 JK flip-flops 9 D flip-flops 4 Buffers 1 Clock Buffers 8 Output Buffers 5 Input Pads 8 Output Pads 4 Input Buffers 1 2 input AND gate Parts used for hard wired circuit: 1 7420 4 input NAND gate 1 7421 4 input AND gate 1 7404 HEX inverter 2 7432 2-input OR gate 2 7400 2 input NAND gate 2 74121 - Monostable multivibrator 2 74109 Dual JK positive edge triggered flip-flop 2 74151 One-of-Eight Data Selector/Multiplexer 2 7442 BCD to decimal decoder 1 74163 Synchronous 4-bit counter 1 7414 - Hex Schmitt-trigger inverters Misc. Resistors and Capacitors *every integrated circuit has a decoupling 0.1 µf capacitor connected to it. 3
Description of internal controller operation Introduction The Richards Controller required in this design is a priority controller which evaluates primary conditions first and then considers secondary conditions. These considerations lead to either the execution of primary functions or secondary functions, respectively. The implementation of this priority controller is generally the same as the dual decision controller implemented in Richards paper. The three major designs of the lab is the stopwatch controller, the controller power-up reset circuitry and the debouncing circuitry for the START/STOP and COUNTER/SPLIT switches. Switch Debouncing and Other Switch Considerations The switch debouncing circuit had to be changed from the hardwired version, since Xilinx didn t have any Schmitt trigger parts. To debounce the SS and CS switches in Xilinx, a double buffer implementation was used. This is done by running the circuit through two D-flip flops in series. Figure 1.1: Setup used to debounce SS and CS switches. What this does is actually sample the single every time the clock goes high. If it s sample twice as much as the clock (by running it through two flip-flops) a bounce will not make it through the circuit, thereby eliminating the bounce. 4
BEFORE AFTER Figure 1.2: The top graph shows the SS and CS switches output before the debounce circuitry was implemented and the bottom graph shows the switches after the debounce circuitry is implemented Also it was important to stop the controller from passing through two states with one button push. This could happen in any instance where two states that are right next to each other need the same condition to pass through it. For example in state one, SS is needed to pass through, and in state twob, SS is needed to pass through it. So with one SS push, the controller can pass through both. To get around this the following circuit was used, Figure 1.3: Circuit used to make sure the state machine doesn t jump states. Figure 1.4: Close-up of circuit component in Figure 1.3. 5
Each JK flip flop is set to toggle on a rising clock edge. The way the circuit works is that each JK flip flops output, is fed into its corresponding condition on the 74151 mux. For example D1 is fed into condition 1 of the primary mux. The only way that a high can be outputted on the flip-flop is by giving it a low to high pulse (this is done by feeding the button push into the clk input of the flipflop). Now the only way the flip flop isn t clearing is if the controller is in the correct state needed for condition one. So this means that unless the button push happened during the correct state, the flip flop will not toggle, and the state will not accidentally pass through states it shouldn t. Even if the button is held for 30 seconds, it would traverse through states, since a rising edge is needed to output a high or a second button push. Power-up reset circuitry The power-up/reset button should be a button that turns the stopwatch on, but also, when pressed, returns the stopwatch to a known state. This is done by having the button keep a high state when normally open, and connects to ground when closed. This button will do a number of things. The time counter is cleared, enable is set low (by clearing the JK flip-flop keeping the state of enable), muxc is set high (by setting the JK flip-flop keeping the state of muxc high to display the counter display). It will also clear the state counter, so it resets the state back to state 0. vcc R1 1K vcc MuxC J Clk K POWER UP/RESET SWITCH vcc Enable J Clk K Time Counter Clear State Counter Clear Figure 2.1 : Schematic of the circuitry used to power up the circuit and reset the stopwatch. It should be noted that 2-74109 JK flip-flops are used to keep track of the current state of enable and muxc. They are set up to be toggle switches by tying the J input high and the K input low. The enable is cleared when the reset is asserted, and muxc is preset when the reset is asserted. More about this will be mentioned shortly. SA pulse The SA (store address) switch, which was used as an input to the state machine, came as a 10 ms pulse. It needed some noise filtering and was done once again by using double buffering [two D latches]. Whenever a user pressed an address switch, SA would go high for 10ms, but at the edges of the 10ms pulse, it was questionable to whether or not a valid address was available, so circuit design would be needed to allow only valid addresses to be read when a button was pushed. More about this will be mentioned shortly. 6
Output Latching Some of the signals sent into the stopwatch module needed to behave by toggling from one logic level to another, as opposed to a momentary state change. This was accomplished using generic JK flip flops. One signal that required this functionality was the counter enable signal. When the state machine enters into a state that should enable the stopwatch counter, the stopwatch should continue counting until leaving that state. To keep the stopwatch counting until further user interaction, the enable must be latched high indefinitely. The counter display (MUXC) also exhibits this same behavior. Figure 3.1 : Logic diagram of outputs and out latches. Stopwatch Controller / Timing Considerations The circuit design is basically a standard Richards Controller. A 4-bit state counter is used to keep track of the state, a primary and secondary multiplexer is used to check low and high priority inputs. In this design, no condition really has priority over the other one, and priority is given to a specified condition to simplify design. A 3 to 8 decoder is also used to perform the functions once the conditions hold true. NAND gates are used to allow two functions to set the same signal low. 7
Figure 3.2 : Logic diagram of primary and secondary decoders. Figure 3.3 : Logic diagram of muxes used to determine when conditions are met to proceed to the next state. The basic operation is as follows: the 74163 counter generates the initial state 0000 when the power on or reset switch is pressed. This state number, X, is passed to the primary multiplexer (mux) which will check the condition on the associated condition line. In this case, these conditions are simply the other three switch signals (SA, SS, CS). If the primary condition is not met, the strobe of the second mux is enabled, and the condition associated with state X is checked for its secondary condition. A successful mux compare with either the primary or secondary condition results in the enabling of the associated primary or secondary decoder. The state X is decoded by the decoder to enable (active low) the associated function. 8
Jump addresses are generated on the load inputs of the 74163 counter. These addresses are created using the function outputs of the decoders. When a function is triggered, it creates the next state address at the load address and also enables the load to take place. Figure 3.4 : Logic diagram of counter and load logic used to jump states. There is one special case of a function needing to be generated. State 3 has three conditions that it needs to check. In order to avoid the use of a third mux/decoder pair or a 16 state mux, we interpret a button push on either the secondary or tertiary condition to be a single event. This creates a decoder function that may be either the secondary or the tertiary function. In order to determine which is the correct function to generate, we simply NAND the inverted ambiguous function with the switch output (SA or SC). Since the switch is active high and the active low function is inverted, this gate produces a high output. This signal is inverted again to obtain the desired active low input at the load addresses. The operation of the stopwatch controller flow is quite simple. It can best be defined if it s explained state by state. Before any of the states are present, the controller is off. It has to be powered on by the power/reset button. Once this is pressed it goes to state zero, where it is waiting for its first condition. At this point the enable is not asserted, the mux is outputting the counter, and the read/write is set to read. It should be noted that the memory enable is tied low since it is always needed, and is pointless to turn it on and off. The condition for state zero is that SS(start/stop must be pressed). It waits until it is. Once SS is pressed, enable is asserted (set high). Now the controller is in state 1. At this point, two different things can happen. SA can be asserted, or SS can be pressed again. 9
If SA is asserted (which means an address button is pressed) it will correspondingly make addlatch go high. They are connected together, but have two D flip flops in between them. One reason why this is done is to debounce SA, if there was an noise from the signal. Figure 4.1: Schematic of the circuit used to control ADDLATCH. Another reason for using this setup is that ADDLATCH will essentially go from low to high, only two clock cycles after SA has been pushed. This is because the D latches will only latch the data on a rising clock edge. Since there are two D latches, two clock cycles are necessary to present the data from SA to ADDLATCH. This will ensure that ADDLATCH will only read data, when a valid address is available, no matter when SA is pressed during the clock cycle. This is because ADDLATCH has a low to high rising clock edge trigger. The following timing diagram establishes this fact. SA CLK MEMLATCH Figure 4.2 : Timing Diagram used to show the function of MEMLATCH. Once SA is pressed, the controller jumps to state seven. Once SA is low again, it returns to state one. Enable is counting the entire time. 10
Figure 4.3 : Timing Diagram used to show the outputs as the controller is going from state 7 to state 1 transitions. During this time memlatch is going low or writing. Also in state 1, SS can be pressed. When this happens, the enable is set low and the controller is moved to state 2. Now the counter is in state 2. Now two different things can happen. The SS button can be pressed or the CS (Counter / Split) button can be pressed. If SS is pressed, the counter is cleared and the controller jumps to state 6, where the enable toggle is set low. From state six, the counter returns to state one. Figure 4.4: Timing diagram showing the controller starting in state 0, going to state 1 by pressing SS, then moving to state 2 by pressing SS, and then taking its second priority option, jumping to state 6 and then automatically returning to state one. During this time the counter is cleared, and then enabled on the next clock cycle. Also in state 2 the CS button can be pressed. If it is, muxc is set low (using the flip-flop set-up as described previously) and the counter moves to state 3. In state 3, three different things can happen: SA can be asserted, CS can be asserted, and SS can be asserted. If CS is asserted, muxc is set high and the counter moves back to state two. 11
Figure 4.5: Timing diagram showing the controller in moving to state 3, taking one of its second priorities and moving back to state 2, while muxc is set high to display the counter output. The counter is then cleared. While still in state 3, if SS is pressed, muxc is set high, the display counter is loaded, and the counter is moved to state 6. In state 6, enable is automatically set high (with no condition needed). Now the counter is back at state 1. Figure 4.6: Timing diagram showing the controller in moving to state 3, taking one of its second priorities, and jumping to state 6 and then to state one, while loading the display with an address from memory, setting muxc high, then enabling the counter. Also in state 3, SA can be asserted. If it is, addlatch is set high in the same way it was in state 7(using the quarter clock cycle). The counter now is in state 4. Now the memory chips outputs the split time specified by the addlatch and automatically moves to state 5. In this state memlatch is set high to latch the data present at the output of the memory and automatically moves back to state 3. Figure 4.7: Timing diagram showing the controller in moving to state 3, then moving to state 4 when SA is asserted, and using the ¼ clock cycle implementation to read the address push, and then moving to state 5 and asserting memlatch and moving back to state 3. This is the entire state description of the controller. 12
The counter can be sent back to state 0, by pressing the reset switch, where it will have the same properties as it did when it first turned on. Common ground is used to ensure that the interface signals have a common reference ground. It was determined that in states 4 and states 7, it was better to wait until the end of the SA assertion to stop reading the memory address pushed. To do this, an inverted SA was tied into both. This allowed the controller not to proceed into its next state until SA went low and produced a corresponding high at the 4 and 7 input of the primary mux. 13
Concise Description of Debugging Process / Necessary Revisions There wasn t much debugging that had to be done. The debugging that did have to be done took much longer than expected though. The first problem encountered was with pin assignments and buffers. The correct way was not really known by anyone, but it was finally figured out that input and output pads had to be used, and pins could be assigned by attaching a p to the number[i.e. for pin 84, assign the pad LOC to p84]. So when the correct pin assignments were made, and everything was hooked up, it still didn t work. It was first checked to see if the wires were connected correctly. Once that was checked the real debugging began. One big problem was that the address buttons were stopping the counter from running [toggling enable]. So the oscilloscope was used to check what states that the controller was jumping to, and what enable was doing. It was determined that the controller was moving to the right states, but enable was toggling when it wasn t supposed to. After running the timing simulation again in Xilinx, it was discovered that there was a small glitch on the function 1 output, that controlled the counter enable. This glitch would happen whenever the controller went from state 7 to state 1[when an address button was pressed]. The first attempt to fix this was by putting a buffer on the output of function 1. This didn t work. It was realized that the glitch always happened on the same part of the clock cycle [the rising edge], so it was determined that if function1 was fed into a D latch that would only latch on the falling edge of a clock cycle, the glitch wouldn t matter [the glitch was very small, and was never evident on the falling edge of the clock cycle]. Figure 5.1: Circuit used to fix glitch problem. It should be noted that there was also glitches on the function 2, and the second priority function 2. These glitches were fixed in the same manor. The only other thing that was changed from the original design was the way the address buttons control ADDLATCH. Originally JK flip flops were used to cut down the clock cycle, and use the slower clock cycle to control ADDLATCH whenever an address button was pressed. In the midst 14
of debugging the problem previously discussed, it was determined that using D flips would be more useful. It would get rid of any noise the SA signal had when it when low to high, and it would control ADDLATCH in a simpler and more consistent manner. The way this circuit works has been previously discussed and evident in Figure 4.1. SA A1 d A2 d ADDLATCH clk clk CLK CLK Figure 5.2: Schematic of the circuit used to control ADDLATCH. 15
Richards Flow Diagram SS 0 0 SS 1a SA 1b 1b Reset: MuxC Set High Counter Cleared Enable Set Low Fctn 0: Enable Set High Fctn 1a: Enable Set Low Fctn 1b: Add Latch is Set High Fctn 2a: MuxC Set Low Fctn 2b: Counter Cleared Enable Set High Fctn 3a: Add Latch is Set High Fctn 3b: MuxC is Set High Fctn 3c: Load Counter MuxC Set High Fctn 5: MemLatch is Set High Fctn 6: Set Enable High Fctn 7: Read/Write set to write 1!SA 7 Notes: State can be sent back to state 0 by pressing the reset switch, which is hardwired into the ckt. CS 2 SS 2 7 Arrows exiting below denotes state condition satisfied. Arrows exiting to side denotes state condition not satisfied. 2 2b SS 3 CS 3 SA 3 3c 3b 3a TRUE 6!SA 4 5 6 TRUE 5 16
State Diagram Power / Reset is Pressed 0 0 - Enable set low SA 1a E set high 1b addlatch set high 1 b - SS 6 set enable low 6 b - SA a - SS 7 7 -Rw set to write 2 2a muxc low 2b counter cleared b - CS a - CS c - SS 3a addlatch is set high 3b - muxc is set high 3c load counter, muxc set high 3 a - SA 4 SA 5 Memlatch is set high 5 Note: Clear can be executed from any state and will send it back to state 0. When this happens, mux C is set high, counter is cleared, and enable is set low. ME is always tied low. SS Start / Stop Button is pressed CS Counter / Split Button is pressed SA Switched Activated 17
Full Logic Schematic 18
Conclusion This lab showed the functionality and abilites of a Richards Controller. Many complex functions could be executed with a relatively small amount of work. Also, the importance and significance of the debugging process was shown once again. It shows the comparison between the implementation of a design in hardware and the implementation of a design in software and how much time and energy are saved by using the software. Also debugging was considerably easier in the software. Much work was put into get it done, but the final design work, and that s all that was important. 19