COC 243 equential Logic COC 243 (Computer Architecture) Lecture 5 - equential Logic 1
Overview Last Lecture This Lecture equential logic circuits ource: Chapter 11 (10 th edition) Next Lecture Computer architecture 1 COC 243 (Computer Architecture) Lecture 5 - equential Logic 2
Introduction Combinatorial logic circuit - the same inputs always produces the same outputs (last lecture) Inputs Combinational circuit Outputs equential logic circuit - outputs depend not only on the present inputs, but also on the past history (this lecture) Inputs Combinational circuit Outputs Memory COC 243 (Computer Architecture) Lecture 5 - equential Logic 3
Introduction (cont) Types of equential Circuits ynchronous tate changes occur in synchronization to a clock signal Input changes occur between clock pulses tate changes occur at the clock pulses Asynchronous tate changes occur as changes in inputs occur Event driven We will not study these COC 243 (Computer Architecture) Lecture 5 - equential Logic 4
Memory Circuits et-reset latch D-type flip-flop T-type flip-flop JK-type flip-flop COC 243 (Computer Architecture) Lecture 5 - equential Logic 5
et-eset Latch If you tie the output of the circuit to one of its inputs then the circuit saves state. In this case output is on tart with a = = = 0 ( = 1), the latch stores a 0 NO A B 0 0 1 0 1 0 1 0 0 1 1 0 COC 243 (Computer Architecture) Lecture 5 - equential Logic 6
= 0 et () the Latch NO A B 0 0 1 0 1 0 Now toggle = 1 (set the latch) 1 0 0 1 1 0 = 1, Now toggle = 1 (set the latch) COC 243 (Computer Architecture) Lecture 5 - equential Logic 7
eset () Latch = 1 Now toggle = 1 (reset the latch) NO A B 0 0 1 0 1 0 1 0 0 1 1 0 = 0, Now toggle = 1 (reset the latch) COC 243 (Computer Architecture) Lecture 5 - equential Logic 8
et-eset Latch egardless of, By setting = 1 the latch is set ( = 1) By setting = 1 the latch is reset ( = 0) Action 0 0 None 0 1 =0 1 0 =1 1 1 Invalid (why?) From: http://en.wikipedia.org/wiki/file:-_mk2.gif COC 243 (Computer Architecture) Lecture 5 - equential Logic 9
Clocked (Enabled) Flip-Flop The latch is a nice trick If we add a control line to the circuit then we can turn the latch on and off when we want to Enable COC 243 (Computer Architecture) Lecture 5 - equential Logic 10
Clocked NAND flip-flop By inverting the signals into the latch, a flip-flop can be built using only NAND gates (De Morgan) And recall that a NAND gate can be built with 2 transistors Enable COC 243 (Computer Architecture) Lecture 5 - equential Logic 11
D-Type Flip-Flop ince =, Combine into one line: D D Enable D >C D-Type flip-flop Triangle indicates edge-triggered COC 243 (Computer Architecture) Lecture 5 - equential Logic 12
7400 uad 2-Input NAND Gate http://en.wikipedia.org/wiki/7400_series COC 243 (Computer Architecture) Lecture 5 - equential Logic 13
D-Type Flip-Flop Data flip-flop (Delay flip-flop) et or reset D Toggle the enable line (from 0 to 1) D is stored Toggle the enable line (from 1 to 0) D can vary (wobble) freely There is a 1 clock-cycle delay between D and Enable (Clock) Data Output Time t 1 t 2 t 3 t 4 t 5 COC 243 (Computer Architecture) Lecture 5 - equential Logic 14
T Flip-Flop Toggle Flip-Flop The output is inverted when Toggle is held high Enable is clocked Toggle Enable COC 243 (Computer Architecture) Lecture 5 - equential Logic 15
JK Flip-Flop One flip-flop to rule them all (the universal flip-flop) >C J K Enable J K JK flip-flop J K t+1 Meaning 0 0 t No Change 0 1 0 eset 1 0 1 et 1 1 t Toggle COC 243 (Computer Architecture) Lecture 5 - equential Logic 16
JK Flip-Flop One flip-flop to rule them all (the universal flip-flop) et J = K to get T flip-flop et J = K to get a D flip-flop >C J >C J >C J K K K JK flip-flop T flip-flop D flip-flop COC 243 (Computer Architecture) Lecture 5 - equential Logic 17
Asynchronous ipple Counter A 1-bit counter switches between 0 and 1 each cycle It s a toggle flip-flop It s also a divide by 2 Clock >C J High K Clock Data Output The output square wave is half the frequency of the input square wave Time t 1 t 2 t 3 t 4 t 5 COC 243 (Computer Architecture) Lecture 5 - equential Logic 18
Asynchronous ipple Counter A 2-bit counter The low bit toggles every full clock cycle The high bit toggles at half the clock cycle rate Tie the output of the low bit to the input of the high bit 0 Clock >C 0 >C 1 1 High J K J K COC 243 (Computer Architecture) Lecture 5 - equential Logic 19
ynchronous Counter The async counter has the problem that the propagation delay is inconsistent; a function of the number of transistors the signal passes through Ideally the flip-flops will clock at the same time This is achieved with a synchronous counter Logic is added to set the next state based on the previous state Clock >C 0 >C 1 >C 2 >C 3 High J K J K J K J K 0 1 2 3 COC 243 (Computer Architecture) Lecture 5 - equential Logic 20
equential Circuits COC 243 (Computer Architecture) Lecture 5 - equential Logic 21
nakes and Ladders From: https://wiki.sfu.ca/personal/aoberman/images/thumb/b/b5/nakesandladders.jpg/609px-nakesandladders.jpg COC 243 (Computer Architecture) Lecture 5 - equential Logic 22
Binary nakes and Ladders 6 7 8 5 4 3 0 1 2 0 = move 1 1 = move 2 In this case a 3*3 board and a binary die (0 or 1) COC 243 (Computer Architecture) Lecture 5 - equential Logic 23
nakes and Ladders 6 7 8 5 4 3 0 1 2 0 0 0 0 0 0 1 2 3 4 5 6 7 8 1 1 1 tate Transition Diagram 1 1 Board 0 = move 1 1 = move 2 COC 243 (Computer Architecture) Lecture 5 - equential Logic 24
Detect a Given Input equence Detect the input sequence 11101 ingle input x ingle output z Consider repeating sequences COC 243 (Computer Architecture) Lecture 5 - equential Logic 25
tate Transition Diagram 1 1 1 0 1 0 1 2 3 4 5 1 0 0 0 0 0 Z = 0 Z = 1 COC 243 (Computer Architecture) Lecture 5 - equential Logic 26
Detect a Given Input equence Initial state table Input Present tate Next tate Output 0 0 0 0 1 0 1 0 0 1 0 0 1 1 2 0 0 2 0 0 1 2 3 0 0 3 4 0 1 3 3 0 0 4 0 0 1 4 5 0 0 5 0 1 1 5 2 1 COC 243 (Computer Architecture) Lecture 5 - equential Logic 27
Detect a Given Input equence 6 states 3 state variables (to count to 6) A, B, C Using A, B, C (in that order), let 0 = 0 0 0 1 = 0 0 1 2 = 0 1 0 3 = 0 1 1 4 = 1 0 0 5 = 1 0 1 tore the current state in 3 flip-flops COC 243 (Computer Architecture) Lecture 5 - equential Logic 28
Detect a Given Input equence Complete state table Present tate Input Next tate Output A B C X A' B' C' Z 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 1 0 1 0 1 COC 243 (Computer Architecture) Lecture 5 - equential Logic 29
Detect a Given Input equence A = ABCX + ABCX B = ABCX + ABCX + ABCX + ABCX C = ABCX + ABCX + ABCX + ABCX Z = ABCX + ABCX COC 243 (Computer Architecture) Lecture 5 - equential Logic 30
Detect a Given Input equence X Z ABC Combinatorial Logic Circuit A B C A B C D D D Clock >C >C >C COC 243 (Computer Architecture) Lecture 5 - equential Logic 31
egisters D7 D6 D5 D4 D3 D2 D1 D0 D D D D D D D D >C >C >C >C >C >C >C >C Clock Load Enable 7 6 5 4 3 2 1 0 COC 243 (Computer Architecture) Lecture 5 - equential Logic 32
Tristate Buffer The clock is used to enable flip-flop load The output can be controlled with a 3-state buffer Or a 3-state inverter D Y Input (D) Output (Y) E Output Enable (E) COC 243 (Computer Architecture) Lecture 5 - equential Logic 33
74L374 3-TATE Octal D- Type Transparent Latches and Edge- Triggered Flip-Flops Output Control read line Clock write line COC 243 (Computer Architecture) Lecture 5 - equential Logic 34