NTSC color TV signal encoder

NTSC color TV signal encoder The comprises an RGB signal matrix circuit, balanced modulator circuit (rectangular 2-phase modulation), oscillator circuit (VCXO) for a 3.58MHz subcarrier synchronized with video input burst signals, luminosity and color difference signal mixing circuit, and a high speed switch for selecting composite signals of video input and RGB input. RGB signals, synch signals, BFP (burst flag pulses), PCP (pedestal clamp pulses) are input, and an NTSC composite signal is output. Applications Televisions (Teletext-capable), captain systems, video cameras, personal computers Features ) Allows superimposition of video images (VIDEO IN) and computer images (RGB IN). 2) During superimposition, the subcarrier locked onto the video input burst signal RGB is modulated with the RGB signals by the APC circuit, preventing unnatural color disturbance due to switching. 3) Both the RGB and video input signals are pedestalclamped, maintaining a natural image even during fluctuation in luminosity. Block diagram VIDEO OUT Y IN R-Y IN VC 3 5 4) Using a half down pulse, the video signal can be reduced by 5dB to darken the background and make the superimposed RGB image easier to see. 5) Carrier leak is suppressible to less than 0mVP-P (VOUT = 2VP-P) without adjustment. ) Can be adapted for analog RGB input. ) Compact 24-pin SZIP package minimizes external components. 2 SYNC IN 4 B-Y IN BURST LEVEL ADJUSTMENT 8 VB VA 9 APC PHASE ADJUSTMENT AR 3 VCXO PD 0 2 BFP IN PD 4 AG AB 5 B-Y OUT MATRIX Y OUT GND 9 8 R-Y OUT PCP IN 2 HD 20 VIDEO IN 22 HDP IN P IN 23 24

Input / output circuits 3 2 24 23 22 3.2V 2.2V 4 CLAMP 500Ω 2V 9. 5kΩ 5.kΩ 5kΩ.5kΩ 5kΩ 5kΩ 2 5 2V CLAMP 500Ω 20 V GND 9.8kΩ 3.4V 8 8 2.V.2kΩ 4.3kΩ 5. 9.8kΩ 5kΩ 5kΩ 5. 0 2 3 4 5 Fig. Absolute maximum ratings (Ta = 25 C) Parameter Symbol Limits Unit Power supply voltage.0 V Power dissipation Pd 500 mw Operating temperature Storage temperature Topr Tstg 20 ~ 0 55 ~ 25 C C Reduced by 5.0mW for each increase in Ta of C over 25 C. Recommended operating conditions Parameter Symbol Limits Unit Power supply voltage 4.5 ~ 5.5 V R input level VR 0 ~ 0. VP-P G input level VG 0 ~ 0. VP-P B input level VB 0 ~ 0. VP-P Video input level VIN 0 ~.0 VP-P 2

Electrical characteristics (unless otherwise noted, Ta = 25 C, = 5.0V) Parameter Symbol Min. Typ. Max. Unit Conditions Quiescent current IQ 38 54 ma Video output level VOV. 2.2 2. VP-P VIDEO IN = VP-P Half down level change G 3 5 db DC offset VOF 50 0 mvp-p VIDEO IN = VP-P Crosstalk CT 4 40 db VIDEO IN = VP-P ER-EY output level VR-Y 0.3 0.42 0.55 VP-P VR = 0.VP-P EB-EY output level VB-Y 0.2 0.3 0.42 VP-P VB = 0.VP-P YOUT output level VY.0.4.8 VP-P VR = VG = VB = 0.VP-P Ys switching delay time TD 0 ns SYNC output level VOS 0.4 0.5 0.9 VP-P Burst output level VOB 0.25 0.4 0.8 VP-P RE =.8kΩ Composite output level VOY. 2.2 2. VP-P YIN = 0.VP-P R-Y modulation gain GR-Y 9 3 db IN = 0.3VP-P B-Y modulation gain GB-Y 9 3 db IN = 0.2VP-P (R-Y) / (B-Y) modulation gain differential GR-B 2 db Difference between above gains (R-Y) / (B-Y) orthogonal phase shift R deg () Burst orthogonal phase shift B deg Carrier leak LSC 30 0 mvp-p VOUT = 2VP-P APC capture range fcap ± 00 Hz Burst = 0.VP-P, 2.8µS Carrier phase range φsc ± 30 ± 45 deg Superimposition Video frequency characteristic fv 4.5 MHz 3dB when f = 00kHz Video output DG DG ± 3.5 % VIDEO IN = VP-P Video output DP DP ± 2.5 deg VIDEO IN = VP-P Input impedance (SY, BF, PC, HD) ZT 8 5 kω Input impedance (Ys) ZTY 3.5 kω Threshold level (SY, BF, PC, HD) VT 0.9 2.0 2.8 V Threshold level (Ys) VTY 0.5..8 V 3

Measurement circuit ~ 0.VP-P S S2 S3 S4 SYNC 0µF ICC 0.04µF 3 4 5 2 24 CLAMP db 9 v v ~ ~ 8 MATRIX ER - EY EB - EY Y YOUT v ~ 4 5 S5 YIN 3 a.8kω PCP VIDEO VP-P b 2 20 0 5dB BG BG PD VCXO db 23 2 2.kΩ 0k 0.04µF S BFP 22 HDP 8pF 9 8 TC.2kΩ X'TAL 82pF 40Ω 820Ω Vector scope Oscilloscope Fig. 2 4

Application example.2mh L2 LPF R R G B R R2 R3 C 0.04µF C 0µF C4 33pF C5.2 mh L R C 3 4 SYNC (5V) 5 2 24 C2 33pF C3 CLAMP 9 GND MATRIX db Y YOUT R4 Q 2SC202 8 ER - EY EB - EY DLY (400ns) DL 2SC202 Q2 3kΩ 3kΩ 300Ω VR2 C 300Ω VR3 VR4 C0 Burst LEVEL ADJ 4 5 5kΩ Y YIN 3 23 TRP (3.58M) RGB R5 Video C4 R DLY DL2 R PCP 2 VIDEOIN 20 C9 BFP R5 0 5dB BG BG PD VCXO db VR 2 R2 2.k Cµ APS PHASE ADJ 0.04µF C5 DL, DL2: X503 (SUMIDA) L, L2: RC-85.2mH (SUMIDA) TC: TZ03R200E (MURATA) Q, Q2, Q3: 2SC202 (ROHM) XTAL: HC 43U 359.545kHz (NIKKO DENSHI) HDP 0dB 22 R4 5dB 8pF C8 9 TC 8 R3 X'TAL COMPOSITE.2kΩ OUT 82pF R C (2VP-P) C9 0pF R9 Q3 40Ω R R0 C5 820Ω 2SC202 0.04µF OUT Fig. 3 5

Circuit operation () Matrix circuit The R, G and B inputs are clamped to 3.2V by the clamp circuit and combined into signals EY, ER-EY and EB-EY by the resistance-adding matrix circuit. EY = 0.30ER 0.59EG 0.EB ER EY = 0.0ER 0.59EG 0.EB EB EY = 0.30ER 0.59EG 0.89EB Signal EY is then amplified by the db amplifier (pin ) to compensate for the signal's db attenuation in the delay line. To prevent overmodulation, signal ER-EY is output at /.4 and signal EB-EY at / 2.03 (pins and 8). 2kΩ 5. Y The carrier color signal is mixed with color burst signals and luminosity signals EY' (to which a horizontal synchronization signal is added) to create the NTSC composite signal (EN). EN = EY' ER EY.4 sin2πfst EB EY 2.03 (3) Switch circuit Signal Ys (pin 23) switches between video input and RGB composite signals. Performing this switching at high speeds results in superimposition. RGB COMPOSITE cos2πfst 3 R 4 G 5 B VIDEO IN OUT Fig. 4 (2) Balanced modulator circuit Color difference signals are modulated (rectangular 2- phase balanced modulation) with color subcarriers (3.58MHz) having a 90 phase difference. This is called the carrier color signal. Amplitude 90 θ C carrier color signal (combining of R-Y and B-Y) Time Fig. (4) Color subcarrier oscillator circuit The subcarrier oscillator circuit for RGB input. This circuit is synchronized with the video input color burst signal extracted by BFP (burst flag pulses) during superimposition, preventing any unnatural color disturbance due to switching between RGB and video input. This oscillator circuit generates the RGB color burst signal. An attached variable resistor can be used to change the amplitude of the color burst signal and to adjust its phase relative to the video color burst signal. This oscillator circuit remains in the free-running state when there is no video input. 3.58 90 µs θ R4 C 8pF 9 TC VCXO XT 3.58MHz 8 R3.2kΩ C 82pF RGB COMPOSITE VIDEO IN 5dB OUT HDP (Half Down Pulse) EB - EY 3.58MHz (0 ) ER - EY 3.58MHz (90 ) Balanced modulator Balanced modulator Carrier color signal Fig. Fig. 8 (5) During superimposition, video input can be lowered by about 5dB using an HDP (half-down pulse), darkening the background and making RGB input easier to see. Fig. 5

Input waveform and timing chart VIDEO IN CB VP-P SYNC PCP TTL LEVEL ( ) TTL LEVEL ( ) BFP TTL LEVEL ( ) RGB IN 0.VP-P HDP TTL LEVEL ( ) TTL LEVEL ( 2) COMPOSITE OUT from RGB CB 2VP-P SUPER IMPOSE CB 2VP-P CB: COLOR BURST : 0 ~ 0.8V : 3.0V ~ 2 : 0 ~ 0.4V : 2.0V ~ Fig. 9 Electrical characteristic curves 80 3580.5 f0 = 359.545kHz f0 = 359.545kHz QUIESCENT CURRENT: IQ (ma) 0 0 50 40 30 20 0 FREQUENCY: f (free run) (khz) 3580.0 359.5 359.0 FREQUENCY: f (cap. lock) (Hz) 00 400 200 f0 = 0 200 400 00 VIN = 0.VP-P lock cap cap lock 0 0 2 3 4 5 8 358.5 3 4 5 3 4 5 POWER SUPPLY VOLTAGE: (V) Fig. 0 Quiescent current vs. power supply voltage POWER SUPPLY VOLTAGE: (V) Fig. VCXO free-run frequency vs. power supply voltage POWER SUPPLY VOLTAGE: (V) Fig. 2 Capture range and lock range (!) vs. power supply voltage

FREQUENCY: f (cap. lock) (Hz) Fig. 3 Capture range and lock range (@) vs. input voltage Operation notes () RGB and video inputs should be synchronized. When only RGB is input, connect VIDEO IN (pin 20) to GND with a capacitor, and synchronize PCP and BFP to RGB. (3) Input pins with pedestal clamps cannot be left open and must be grounded with a low impedance. When not used, ground with a capacitor. Input pins with pedestal clamps: YIN (pin 3), B-YIN (pin 4), R-YIN (pin 5), VIDEO IN (pin 20) (2) The VCXO remains in a free-running state except during superimposition. (4) Pin 4 (B-YIN) and pin 5 (R-YIN) have high impedance and are susceptible to the effects of noise and other external factors during pattern generation. For this reason, we recommend adding the circuit in Fig. 5 to lower the input impedance. Adding this circuit can also reduce carrier leakage. 2.8 ± 0.2 2.8 ± 0.2 5.8 ± 0.2 2.0Min. 9.9 ± 0.5 00 400 200 f0 = 0 200 400 00 lock cap cap lock f0 = 359.545kHz = 5V 0 00 200 300 400 500 00 00 800 INPUT VOLTAGE: VIN (mvp-p) Fig. 4 External dimensions (Units: mm) Additional circuit.2mh L C2.2mH L2 C4 33pF 3kΩ 3kΩ 33pF Q2 LPF C3 C5 0.5MHz R R 8 Q C 4 300Ω 300Ω C0 Q, Q2: 2SC202 (ROHM) 5 Fig. 5 0.889 0.5 ± 0. 0. 0.3 0.05 2.54 ± 0.25 23 2 24 SZIP24 8