CPE/EE 427, CPE 527 VLSI esign I Sequential Circuits epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka ) Combinational logic Sequencing output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in CL out CL CL Finite State Machine Pipeline 11/1/2006 VLSI esign I; A. Milenkovic 2 VLSI esign I; A. Milenkovic 1
Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. 11/1/2006 VLSI esign I; A. Milenkovic 3 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 11/1/2006 VLSI esign I; A. Milenkovic 4 VLSI esign I; A. Milenkovic 2
Sequential Logic Inputs Combinational Logic Outputs Current State State Registers Next State clock 11/1/2006 VLSI esign I; A. Milenkovic 5 Timing Metrics In Out clock clock t su t hold time In data stable t c-q time Out output stable output stable time 11/1/2006 VLSI esign I; A. Milenkovic 6 VLSI esign I; A. Milenkovic 3
System Timing Constraints Inputs Combinational Logic Outputs Current State State Registers Next State clock T (clock period) t cdreg + t cdlogic t hold T t c-q + t plogic + t su 11/1/2006 VLSI esign I; A. Milenkovic 7 Sequencing Elements : Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger Flop (latch) (flop) 11/1/2006 VLSI esign I; A. Milenkovic 8 VLSI esign I; A. Milenkovic 4
: Level sensitive Sequencing Elements a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger Flop (latch) (flop) 11/1/2006 VLSI esign I; A. Milenkovic 9 esign Pass Transistor Pros + + Cons 11/1/2006 VLSI esign I; A. Milenkovic 10 VLSI esign I; A. Milenkovic 5
esign Pass Transistor Pros +Tiny + Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s 11/1/2006 VLSI esign I; A. Milenkovic 11 esign Transmission gate + - 11/1/2006 VLSI esign I; A. Milenkovic 12 VLSI esign I; A. Milenkovic 6
esign Transmission gate +No V t drop - Requires inverted clock 11/1/2006 VLSI esign I; A. Milenkovic 13 esign Inverting buffer + + + Fixes either 11/1/2006 VLSI esign I; A. Milenkovic 14 VLSI esign I; A. Milenkovic 7
esign Inverting buffer + Restoring + No backdriving + Fixes either Output noise sensitivity Or diffusion input Inverted output 11/1/2006 VLSI esign I; A. Milenkovic 15 esign Tristate feedback + 11/1/2006 VLSI esign I; A. Milenkovic 16 VLSI esign I; A. Milenkovic 8
esign Tristate feedback + Static Backdriving risk Static latches are now essential 11/1/2006 VLSI esign I; A. Milenkovic 17 esign Buffered input + + 11/1/2006 VLSI esign I; A. Milenkovic 18 VLSI esign I; A. Milenkovic 9
esign Buffered input + Fixes diffusion input + Noninverting 11/1/2006 VLSI esign I; A. Milenkovic 19 esign Buffered output + 11/1/2006 VLSI esign I; A. Milenkovic 20 VLSI esign I; A. Milenkovic 10
esign Buffered output + No backdriving Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading 11/1/2006 VLSI esign I; A. Milenkovic 21 esign atapath latch + - 11/1/2006 VLSI esign I; A. Milenkovic 22 VLSI esign I; A. Milenkovic 11
esign atapath latch + Smaller, faster - unbuffered input 11/1/2006 VLSI esign I; A. Milenkovic 23 Flip-Flop esign Flip-flop is built as pair of back-to-back latches 11/1/2006 VLSI esign I; A. Milenkovic 24 VLSI esign I; A. Milenkovic 12
Enable Enable: ignore clock when en = 0 Mux: increase latch - delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en 1 0 en en en Flop 1 0 en Flop Flop en 11/1/2006 VLSI esign I; A. Milenkovic 25 Reset Force output low when reset asserted Synchronous vs. asynchronous Symbol Flop reset reset Synchronous Reset Asynchronous Reset reset reset reset reset reset reset 11/1/2006 VLSI esign I; A. Milenkovic 26 VLSI esign I; A. Milenkovic 13
Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset set reset reset set 11/1/2006 VLSI esign I; A. Milenkovic 27 Sequencing Methods Flip-flops T c 2-Phase es Pulsed es Flip-Flops Flop Combinational Logic Flop 2-Phase Transparent es Pulsed es 1 2 p 1 2 1 t pw p T c /2 Combinational Logic t nonoverlap Combinational Logic Combinational Logic Half-Cycle 1 Half-Cycle 1 t nonoverlap p 11/1/2006 VLSI esign I; A. Milenkovic 28 VLSI esign I; A. Milenkovic 14
Timing iagrams Contamination and Propagation elays A Combinational Logic Y A Y t cd t pd t pd Logic Prop. elay t cd Logic Cont. elay t setup thold t pcq /Flop Clk- Prop elay Flop t ccq t pdq /Flop Clk- Cont. elay - Prop elay t ccq t pcq t pcq t setup t hold - Cont. elay /Flop Setup Time /Flop Hold Time t ccq t pcq t setup t hold t cdq t pdq 11/1/2006 VLSI esign I; A. Milenkovic 29 Max-elay: Flip-Flops t ( ) pd Tc 1 42443 sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 11/1/2006 VLSI esign I; A. Milenkovic 30 VLSI esign I; A. Milenkovic 15
Max-elay: Flip-Flops ( setup ) tpd Tc t + tpcq 14243 sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 11/1/2006 VLSI esign I; A. Milenkovic 31 Max elay: 2-Phase es ( ) tpd = tpd1+ tpd 2 Tc 1 42443 sequencing overhead 1 2 1 1 1 Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 1 2 T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 11/1/2006 VLSI esign I; A. Milenkovic 32 VLSI esign I; A. Milenkovic 16
Max elay: 2-Phase es ( 2 ) tpd = tpd1+ tpd 2 Tc tpdq 123 sequencing overhead 1 2 1 1 1 Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 1 2 T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 11/1/2006 VLSI esign I; A. Milenkovic 33 Max elay: Pulsed es t pd ( ) Tc max 144 4244443 sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p (b) t pw < t setup 1 2 t pcq T c t pw tpd tsetup 11/1/2006 VLSI esign I; A. Milenkovic 34 VLSI esign I; A. Milenkovic 17
Max elay: Pulsed es ( setup ) tpd Tc max tpdq, tpcq + t tpw 14444244443 sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p (b) t pw < t setup 1 2 t pcq T c t pw tpd tsetup 11/1/2006 VLSI esign I; A. Milenkovic 35 Min-elay: Flip-Flops 1 t CL cd F1 2 F2 1 t ccq t cd 2 t hold 11/1/2006 VLSI esign I; A. Milenkovic 36 VLSI esign I; A. Milenkovic 18
Min-elay: Flip-Flops 1 t t t CL cd hold ccq F1 2 F2 1 t ccq t cd 2 t hold 11/1/2006 VLSI esign I; A. Milenkovic 37 Min-elay: 2-Phase es t t cd1, cd 2 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold 11/1/2006 VLSI esign I; A. Milenkovic 38 VLSI esign I; A. Milenkovic 19
Min-elay: 2-Phase es t t t t t cd1, cd 2 hold ccq nonoverlap 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold 11/1/2006 VLSI esign I; A. Milenkovic 39 Min-elay: Pulsed es p tcd 1 CL L1 Hold time increased by pulse width 2 p L2 p tpw t hold 1 t ccq t cd 2 11/1/2006 VLSI esign I; A. Milenkovic 40 VLSI esign I; A. Milenkovic 20
Min-elay: Pulsed es tcd thold tccq + t 1 pw CL p L1 Hold time increased by pulse width 2 p L2 p tpw t hold 1 t ccq t cd 2 11/1/2006 VLSI esign I; A. Milenkovic 41 Time Borrowing In a flop-based system: ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle 11/1/2006 VLSI esign I; A. Milenkovic 42 VLSI esign I; A. Milenkovic 21
Time Borrowing Example 1 2 1 1 2 (a) Combinational Logic Combinational Logic Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Combinational Logic Combinational Logic Loops may borrow time internally but must complete within the cycle 11/1/2006 VLSI esign I; A. Milenkovic 43 How Much Borrowing? 2-Phase es T borrow c setup + nonoverlap ( ) t t t 2 1 1 2 L1 1 2 Combinational Logic 1 L2 2 1 Pulsed es 2 T c t nonoverlap t t t borrow pw setup T c /2 Nominal Half-Cycle 1 elay t borrow t setup 2 11/1/2006 VLSI esign I; A. Milenkovic 44 VLSI esign I; A. Milenkovic 22
Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing 11/1/2006 VLSI esign I; A. Milenkovic 45 Skew: Flip-Flops ( setup skew ) tpd Tc tpcq + t + t 14 424443 t t t + t cd hold sequencing overhead ccq skew F1 1 t pcq 1 Combinational Logic T c t pdq 2 t setup F2 t skew 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd 11/1/2006 VLSI esign I; A. Milenkovic 46 VLSI esign I; A. Milenkovic 23
Skew: es 2-Phase es ( 2 ) tpd Tc tpdq 123 sequencing overhead t, t t t t + t cd1 cd 2 hold ccq nonoverlap skew T t t + t + t 2 ( ) c borrow setup nonoverlap skew Pulsed es cd hold pw ccq ( setup skew ) tpd Tc max tpdq, tpcq + t tpw + t 1444442444443 t t + t t + t ( ) t t t + t sequencing overhead skew borrow pw setup skew 1 2 1 2 1 1 1 Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 11/1/2006 VLSI esign I; A. Milenkovic 47 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) 11/1/2006 VLSI esign I; A. Milenkovic 48 VLSI esign I; A. Milenkovic 24
Safe Flip-Flop In class, use flip-flop with nonoverlapping clocks Very slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 2 1 2 1 2 1 2 1 11/1/2006 VLSI esign I; A. Milenkovic 49 Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent es: Lots of skew tolerance and time borrowing Pulsed es: Fast, some skew tol & borrow, hold time risk 11/1/2006 VLSI esign I; A. Milenkovic 50 VLSI esign I; A. Milenkovic 25