Chpter 3: Sequentil Logic Design -- Controllers Slides to ccompny the textbook, First Edition, by, John Wiley nd Sons Publishers, 27. http://www.ddvhid.com Copyright 27 Instructors of courses requiring Vhid's textbook (published by John Wiley nd Sons) hve permission to modify nd use these slides for customry course-relted ctivities, subject to keeping Digitl this copyright Design notice in plce nd unmodified. These slides my be posted s unnimted pdf versions on publicly-ccessible course websites.. PowerPoint source (or pdf with nimtions) my not be posted to publicly-ccessible websites, but my be posted for students on internl protected sites or distributed directly to students by other electronic mens. Copyright 26 Instructors my mke printouts of the slides vilble to students for resonble photocopying chrge, without incurring roylties. Any other use requires explicit permission. Instructors my obtin PowerPoint Frnk source Vhid or obtin specil use permissions from Wiley see http://www.ddvhid.com for informtion.
si nsis e z Introduction 3. Sequentil circuit Output depends not just on present inputs (s in combintionl circuit), but on pst sequence of inputs Stores bits, lso known s hving stte Simple exmple: circuit tht counts up in binry In this chpter, we will: Design new building block, flip-flop, tht stores one bit Combine tht block to build multi-bit storge register Describe the sequentil behvior using finite stte mchine Convert finite stte mchine to controller sequentil circuit hving register nd combintionl logic b b Combintionl digitl circuit Sequentil digitl circuit Must know sequence of pst inputs to know output F? F Copyright 26 Note: Slides with nimtion re denoted with smll red "" ner the nimted items 2
Exmple Needing Bit Storge 3.2 Flight ttendnt cll button Press cll: light turns on Stys on fter button relesed Press cncel: light turns off Logic gte circuit to implement this? Cll button Cncel button Bit Storge Blue light. Cll button pressed light turns on Cll button Cncel button Bit Storge Blue light Cll Cncel 2. Cll button relesed light stys on Doesn t work. = when Cll=, but doesn t sty when Cll returns to Need some form of feedbck in the circuit Copyright 26 Cll button Cncel button Bit Storge Blue light 3. Cncel button pressed light turns off 3
4 Copyright 26 First ttempt t Bit Storge We need some sort of feedbck Does circuit on the right do wht we wnt? No: Once becomes (when S=), stys forever no vlue of S cn bring bck to S t t S t S t S t S t S t S
ecl. R Bit Storge Using n SR Ltch Does the circuit to the right, with cross-coupled NOR gtes, do wht we wnt? Yes! How did someone come up with tht circuit? Mybe just tril nd error, bit of insight... S (set) SR ltch S= t S= t S= t S= R (reset) t Recll X R= R= R= R= S R t Copyright 26 5
Exmple Using SR Ltch for Bit Storge SR ltch cn serve s bit storge in previous exmple of flight-ttendnt cll button Cll button Cncel button Bit Storge Blue light Cll= : sets to stys even fter Cll= Cncel= : resets to Cll but ton S But, there s problem... Cncel but ton R Blue light Copyright 26 6
Problem Problem with SR Ltch If S= nd R= simultneously, we don t know wht vlue will tke S= R= t S= R= t S= R= t S R t my oscillte. Then, becuse one pth will be slightly longer thn the other, will eventully settle to or but we don t know which. t Copyright 26 7
Problem with SR Ltch Problem not just one of user pressing two buttons t sme time Cn lso occur even if SR inputs come from circuit tht supposedly never sets S= nd R= t sme time But does, due to different delys of different pths X Arbitrry circuit S SR ltch X Y Y The longer pth from X to R thn to S cuses SR= for short time could be long enough to cuse oscilltion Copyright 26 R S R SR = 8
Copyright 26 Solution: Level-Sensitive SR Ltch Add enble input C s shown Only let S nd R chnge when C= Enure circuit in front of SR never sets SR=, except briefly due to pth delys Chnge C to only fter sufficient time for S nd R to be stble When C becomes, the stble S nd R vlue psses through the two AND gtes to the SR ltch s S R inputs. X Y Clk S C R Level-sensitive SR ltch S R S R C S R S C R Though SR= briefly......sr never = Level-sensitive SR ltch S R S C R 9 Level-sensitive SR ltch symbol
Clock Signls for Ltch How do we know when it s sfe to set C=? Most common solution mke C pulse up/down C=: Sfe to chnge X, Y C=: Must not chnge X, Y We ll see how to ensure tht lter Clock signl -- Pulsing signl used to enble ltches Becuse it ticks like clock Sequentil circuit whose storge components ll use clock signls: synchronous circuit Most common type Asynchronous circuits importnt topic, but left for dvnced course X Y Clk Level-sensitive SR ltch S S C R R Copyright 26
Clocks Clock period: time intervl between pulses Above signl: period = 2 ns Clock cycle: one such time intervl Above signl shows 3.5 clock cycles Clock frequency: /period Above signl: frequency = / 2 ns = 5 MHz Hz = /s Freq GHz GHz GHz MHz MHz Period. ns. ns ns ns ns Copyright 26
Level-Sensitive D Ltch SR ltch requires creful design to ensure SR= never occurs D S D ltch D ltch relieves designer of tht burden Inserted inverter ensures R lwys opposite of S C R D C D C S R D ltch symbol Copyright 26 2
Problem with Level-Sensitive D Ltch D ltch still hs problem (s does SR ltch) When C=, through how mny ltches will signl trvel? Depends on for how long C= Clk_A -- signl my trvel through multiple ltches Clk_B -- signl my trvel through fewer ltches Hrd to pick C tht is just the right length Cn we design bit storge tht only stores vlue on the rising edge of clock signl? rising edges Y D D2 2 D3 3 D4 4 Clk C C2 C3 C4 Clk Clk_A Clk_B Copyright 26 3
D Flip-Flop Flip-flop: Bit storge tht stores on clock edge, not level One design -- mster-servnt Two ltches, output of first goes to input of second, mster ltch hs inverted clock signl So mster loded when C=, then servnt when C= When C chnges from to, mster disbled, servnt loded with vlue tht ws t D just before C chnged -- i.e., vlue t D during rising edge of C D flip-flop Clk rising edges Clk Note: Hundreds of different flipflop designs exist D D ltch Dm m D ltch Ds s D/Dm Cm Cm Cs s m/ds mster servnt Cs Clk s Copyright 26 4
D Flip-Flop The tringle mens clock input, edge triggered D Symbol for rising-edge triggered D flip-flop rising edges Clk D Symbol for flling-edge triggered D flip-flop Clk flling edges Internl design: Just invert servnt clock rther thn mster Copyright 26 5
fli p -flop insidech T w ol t ches D Flip-Flop Solves problem of not knowing through how mny ltches signl trvels when C= In figure below, signl trvels through exctly one flip-flop, for Clk_A or Clk_B Why? Becuse on rising edge of Clk, ll four flip-flops re loded simultneously -- then ll four no longer py ttention to their input, until the next rising edge. Doesn t mtter how long Clk is. Y D D2 2 D3 3 D4 4 Two ltches inside ech flip-flop Clk Clk_A Clk_B Copyright 26 6
D Ltch vs. D Flip-Flop Ltch is level-sensitive: Stores D when C= Flip-flop is edge triggered: Stores D when C chnges from to Sying level-sensitive ltch, or edge-triggered flip-flop, is redundnt Two types of flip-flops -- rising or flling edge triggered. Compring behvior of ltch nd flip-flop: Clk 2 D 3 4 5 6 (D ltch) 7 8 Copyright 26 (D flip-flop) 9 7
Flight-Attendnt Cll Button Using D Flip-Flop D flip-flop will store bit Inputs re Cll, Cncel, nd present vlue of D flip-flop, Truth tble shown below Cll button Cncel button Flight ttendnt cll-button system Blue light Preserve vlue: if =, mke D=; if =, mke D= Circuit derived from truth tble, using Chpter 2 combintionl logic design process Copyright 26 Cncel -- mke Cll but ton D= D Cncel Cncel but ton Clk Cll -- mke D= Let s give priority to Cll -- mke D= Cll Blue light 8
Bit Storge Summry SR ltch S (set) R (reset) Level-sensitive SR ltch S S C R R D C S R D ltch D Clk D ltch Dmm Cm mster D flip-flop D ltch Ds s Cs s servnt Feture: S= sets to, R= resets to. Problem: SR= yield undefined. Feture: S nd R only hve effect when C=. We cn design outside circuit so SR= never hppens when C=. Problem: voiding SR= cn be burden. Feture: SR cn t be if D is stble before nd while C=, nd will be for only brief glitch even if D chnges while C=. Problem: C= too long propgtes new vlues through too mny ltches: too short my not enble store. Feture: Only lods D vlue present t rising clock edge, so vlues cn t propgte to other flip-flops during sme clock cycle. Trdeoff: uses more gtes internlly thn D ltch, nd requires more externl gtes thn SR but gte count is less of n issue tody. We considered incresingly better bit storge until we rrived t the robust D flip-flop bit storge Copyright 26 9
Bsic Register Typiclly, we store multi-bit items e.g., storing 4-bit binry number Register: multiple flip-flops shring clock signl From this point, we ll use registers for bit storge No need to think of ltches or flip-flops But now you know wht s inside register I3 I2 I I 4-bit register D D D D I3 I2 I I reg(4) 3 2 3 2 Copyright 26 2
e r tu r empe t sensor Exmple Using Registers: Temperture Disply Temperture history disply Sensor outputs temperture s 5-bit binry number Timer pulses C every hour Record temperture on ech pulse, disply lst three recorded vlues Present Disply hour go Disply 2 hours go Disply Copyright 26 x4 x3 x2 x x 4 3 2 b4 b3 b2 b b TempertureHistoryStorge c4 c3 c2 c c timer C (In prctice, we would ctully void connecting the timer output C to clock input, insted only connecting n oscilltor output to clock input.) 2
Exmple Using Registers: Temperture Disply Use three 5-bit registers 4 3 2 b4 b3 b2 b b c4 c3 c2 c c C x4 x3 x2 x x I4 I3 I2 I I R 4 3 2 I4 I3 I2 I I Rb 4 3 2 I4 I3 I2 I I Rc 4 3 2 TempertureHistoryStorge x4...x C 5 8 2 2 2 22 24 24 24 25 25 26 26 26 27 27 27 27 R 8 2 24 25 26 27 Rb 8 2 24 25 26 Copyright 26 Rc 8 2 24 25 22
Finite-Stte Mchines (FSMs) nd Controllers 3.3 Wnt sequentil circuit with prticulr behvior over time Exmple: Lser timer Push button: x= for 3 clock cycles How? Let s try three flip-flops b= gets stored in first D flip-flop Then 2nd flip-flop on next cycle, then 3rd flip-flop on next OR the three flip-flop outputs, so x should be for three cycles b b Controller lser x ptient D D D x Copyright 26 23
Need Better Wy to Design Sequentil Circuits Tril nd error is not good design method Will we be ble to guess circuit tht works for other desired behvior? How bout counting up from to 9? Pulsing n output for cycle every cycles? Detecting the sequence 3 5 in binry on 3-bit input? And, circuit built by guessing my hve undesired behvior Lser timer: Wht if press button gin while x=? x then stys one nother 3 cycles. Is tht wht we wnt? Combintionl circuit design process hd two importnt things. A forml wy to describe desired circuit behvior Boolen eqution, or truth tble 2. A well-defined process to convert tht behvior to circuit We need those things for sequence circuit design Copyright 26 24
Describing Behvior of Sequentil Circuit: FSM Finite-Stte Mchine (FSM) A wy to describe desired behvior of sequentil circuit Akin to Boolen equtions for combintionl behvior List sttes, nd trnsitions mong sttes Exmple: Mke x chnge toggle ( to, or to ) every clock cycle Two sttes: Off (x=), nd On (x=) Trnsition from Off to On, or On to Off, on rising clock edge Arrow with no strting stte points to initil stte (when circuit first strts) Copyright 26 stte Outputs: x Outputs: x x= ^ x= Off On ^ Off On Off On Off On Off On cycle cycle 2 cycle 3 cycle 4 Off On Off On 25
FSM Exmple:,,,,repet Wnt,,,,,,,,... Ech vlue for one clock cycle Cn describe s FSM Four sttes Trnsition on rising clock edge to next stte Outputs: x x= ^ x= ^ x= ^ x= Off On On2 On3 ^ Stte Off OnOn2On3 Off OnOn2On3 Off Outputs: x Copyright 26 26
Extend FSM to Three-Cycles High Lser Timer Four sttes Wit in Off stte while b is (b ) When b is (nd rising clock edge), trnsition to On Sets x= On next two clock edges, trnsition to On2, then On3, which lso set x= So x= for three cycles fter button pressed Copyright 26 Inputs: b St t e Outputs: x Inputs: b; Outputs: x x= Off b*^ x= Off On ^ b *^ x= On2 ^ ^ x= On3 Off Off Off Off On On2 On3 Off 27
FSM Simplifiction: Rising Clock Edges Implicit Showing rising clock on every trnsition: cluttered Mke implicit -- ssume every edge hs rising clock, even if not shown Wht if we wnted trnsition without rising edge We don t consider such synchronous FSMs -- less common, nd dvnced topic Only consider synchronous FSMs -- rising edge on every trnsition Inputs: b; Outputs: x x= Off b*^ x= ^ On b *^ x= On2 Inputs: b; Outputs: x x= b Off x= b x= ^ ^ x= On3 x= On On2 On3 Copyright 26 Note: Trnsition with no ssocited condition thus trnsistions to next stte on next clock cycle 28
FSM Definition FSM consists of Set of sttes Ex: {Off, On, On2, On3} Set of inputs, set of outputs Ex: Inputs: {x}, Outputs: {b} Initil stte Ex: Off Set of trnsitions Describes next sttes Ex: Hs 5 trnsitions Set of ctions Sets outputs while in sttes Ex: x=, x=, x=, nd x= Inputs: b; Outputs: x x= b Off x= On x= On2 x= On3 We often drw FSM grphiclly, known s stte digrm Cn lso use tble (stte tble), or textul lnguges b Copyright 26 29
FSM Exmple: Secure Cr Key Mny new cr keys include tiny computer chip When cr strts, cr s computer (under engine hood) requests identifier from key Key trnsmits identifier If not, computer shuts off cr FSM Wit until computer requests ID (=) Trnsmit ID (in this cse, ) r= Inputs: ; Outputs: r Wit K K2 K3 K4 r= r= r= r= Copyright 26 3
FSM Exmple: Secure Cr Key (cont.) Nice feture of FSM Cn evlute output behvior for different input sequence Timing digrms show sttes nd output vlues for different input wveforms Inputs r= Wit Inputs: ; Outputs: r K K2 K3 K4 r= r= r= r= : Determine sttes nd r vlue for given input wveform: Inputs St t e Wit Wit K K2 K3 K4 Wit Wit Stte Wit Wit K K2 K3 K4 Wit K Outputs r Output r Copyright 26 3
Copyright 26 FSM Exmple: Code Detector Unlock door (u=) only when buttons pressed in sequence: strt, then red, blue, green, red Input from ech button: s, r, g, b Also, output indictes tht some colored button pressed FSM Wit for strt (s=) in Wit Once strted ( Strt ) If see red, go to Red Then, if see blue, go to Blue Then, if see green, go to Green Then, if see red, go to Red2 In tht stte, open the door (u=) Wrong button t ny step, return to Wit, without opening door u= s u= r Wit Strt Red u= Strt Red Green Blue s s r g b Code detector r b g r u Door lock Inputs: s,r,g,b,; Outputs: u b Blue g Green r Red2 u= u= u= : Cn you trick this FSM to open the door, without knowing the code? A: Yes, hold ll buttons simultneously 32
Improve FSM for Code Detector u= s Wit s r b g r Inputs: s,r,g,b,; Outputs: u u= r Strt Red u= b Blue g Green r Red2 u= u= u= Note: smll problem still remins; we ll discuss lter New trnsition conditions detect if wrong button pressed, returns to Wit FSM provides forml, concrete mens to ccurtely define desired behvior Copyright 26 33
outputs FSM Stndrd Controller Architecture How implement FSM s sequentil circuit? Use stndrd rchitecture Stte register -- to store the present stte Combintionl logic -- to compute outputs, nd next stte For lser timer FSM 2-bit stte register, cn represent four sttes Input b, output x Known s controller FSM inputs I Combintionl logic O FSM outputs Inputs: b; Outputs: x x= FSM inputs b b Off x= On b x= On2 Combintionl logic s s n n x= On3 x FSM outputs S m m Stte register m-bit stte register Copyright 26 N Generl version 34
Controller Design 3.4 Five step controller design process Copyright 26 35
outputs FSM Controller Design: Lser Timer Exmple Step : Cpture the FSM Alredy done Step 2: Crete rchitecture 2-bit stte register (for 4 sttes) Input b, output x Next stte signls n, n Step 3: Encode the sttes Any encoding with ech stte unique will work Inputs: b; Outputs: x x= Off b FSM inputs b x= x= x= On On2 On3 b Combintionl logic s s n n x FSM outputs Stte register Copyright 26 36
Controller Design: Lser Timer Exmple (cont) Step 4: Crete stte tble Inputs: b; Outputs: x x= Off b b x= x= x= On On2 On3 FSM inputs b Combintionl logic s s n n x FSM outputs Stte register Copyright 26 37
Controller Design: Lser Timer Exmple (cont) Step 5: Implement combintionl logic FSM inputs b Combintionl logic s s n n x FSM outputs Stte register x = s + s (note from the tble tht x= if s = or s = ) n = s sb + s sb + ss b + ss b n = s s + ss n = s s b + ss b + ss b n = s s b + ss Copyright 26 38
FSMinputs FSMoutputs Controller Design: Lser Timer Exmple (cont) Step 5: Implement combintionl logic (cont) b FSM inputs b Combintionl Logic Combintionl logic s s n n x FSM outputs x n Stte register n s s Stte register x = s + s n = s s + ss n = s s b + ss Copyright 26 39
Understnding the Controller s Behvior b x= Off b x= x= x= On On2 On3 b x= Off b x= x= x= On On2 On3 b x= Off b x= x= x= On On2 On3 b s s x n n b s s x n n b s s x n n stte= stte= stte= Inputs: b Outputs: x Copyright 26 4
Controller Exmple: Button Press Synchronizer cycle cycle2 cycle3 cycle4 bi Button press synchronizer controller bo Inputs: bi Outputs: bo Wnt simple sequentil circuit tht converts button press to single cycle durtion, regrdless of length of time tht button ctully pressed We ssumed such n idel button press signl in erlier exmple, like the button in the lser timer controller Copyright 26 4
outputs FSM FSM inputs: bi; FSM outputs: bo bi bi bi A B bi C bi bi bo= bo= bo= Step : FSM Controller Exmple: Button Press Synchronizer (cont) FSM inputs bi Combintionl logic s s Stte register bo n n FSM outputs Step 2: Crete rchitecture n = s sbi + ssbi n = s s bi bo = s sbi + s sbi = ss Combintionl logic bo FSM inputs: bi; FSM outputs: bo bi bi bi bi bi bi bo= bo= bo= Step 3: Encode sttes Copyright 26 A B C unused Combintionl logic Inputs Outputs s s bi n n bo Step 4: Stte tble bi s s Stte register Step 5: Crete combintionl circuit Step 5: Crete combintionl circuit n n 42
FSMoutputs Controller Exmple: Sequence Genertor Wnt generte sequence,,,, (repet) Ech vlue for one clock cycle Common, e.g., to crete pttern in 4 lights, or control mgnets of stepper motor Inputs: none; Outputs: w,x,y,z wxyz= wxyz= A B D C wxyz= wxyz= Step : Crete FSM Combintionl logic s s Stte register n n Step 2: Crete rchitecture w xy z Inputs: none; Outputs: w,x,y,z wxyz= wxyz= A B wxyz= D C wxyz= Step 3: Encode sttes Step 4: Crete stte tble Copyright 26 w = s x = ss y = s s z = s n = s xor s n = s s s Stte register n w x y z n Step 5: Crete combintionl circuit 43
FSM inputs outputs FSM Controller Exmple: Secure Cr Key Step Wit r= Inputs: ; Outputs: r K K2 K3 K4 r= r= r= r= (from erlier exmple) r Step 2 Combintionl logic n2 n n s2 s s Stte register Inputs: ; Outputs: r Step 3 r= r= r= r= r= Copyright 26 We ll omit Step 5 Step 4 44
FSMinputs FSMoutputs Exmple: Seq. Circuit to FSM (Reverse Engineering) x Wht does this circuit do? y z y=s z = ss n=(s xor s)x n=(s *s )x A D Outputs: y, z B C sttes n n A yz= D yz= B yz= C yz= sttes with outputs s s Stte register Work bckwrds x Inputs: x; Outputs:y, z A D yz= x x x B C x yz= yz= Copyright 26 Pick ny stte nmes you wnt yz= x sttes with outputs nd trnsitions 45
Common Pitflls Regrding Trnsition Properties Only one condition should be true For ll trnsitions leving stte Else, which one? One condition must be true For ll trnsitions leving stte Else, where go? b b= next stte? b b b wht if b=? b Copyright 26 46
Verifying Correct Trnsition Properties Cn verify using Boolen lgebr Only one condition true: AND of ech condition pir (for trnsitions leving stte) should equl proves pir cn never simultneously be true One condition true: OR of ll conditions of trnsitions leving stte) should equl proves t lest one condition must be true Exmple b Answer: * b = ( * ) * b = * b = OK! + b = *(+b) + b = + b + b = + (+ )b = + b Fils! Might not be (i.e., =, b=) : For shown trnsitions, prove whether: * Only one condition true (AND of ech pir is lwys ) * One condition true (OR of ll trnsitions is lwys ) Copyright 26 47
Copyright 26 Evidence tht Pitfll is Common Recll code detector FSM We fixed problem with the trnsition conditions Do the trnsitions obey the two required trnsition properties? Consider trnsitions of stte Strt, nd the only one true property Wit u= s u= r Strt Red u= r * * (r +b+g) r * (r +b+g) = (* )r = *r = ( *)*(r +b+g) = *(r +b+g) = (*)*r*(r +b+g) = *r*(r +b+g) = = = rr +rb+rg = + rb+rg = rb + rg = r(b+g) Fils! Mens tht two of Strt s trnsitions could be true s b g r Blue Green Red2 u= u= u= Intuitively: press red nd blue buttons t sme time: conditions r, nd (r +b+g) will both be true. Which one should be tken? : How to solve? A: r should be rb g (likewise for b, g, r) Note: As evidence the pitfll is common, we dmit the mistke ws not intentionl. A reviewer of the book cught it. 48
Simplifying Nottions FSMs Assume unssigned output implicitly ssigned = b= c= = b= c= Sequentil circuits Assume unconnected clock inputs connected to sme externl clock b= c= Copyright 26 49
More on Flip-Flops nd Controllers 3.5 Other flip-flop types SR flip-flop: like SR ltch, but edge triggered JK flip-flop: like SR (S J, R K) But when JK=, toggles, T flip-flop: JK with inputs tied together Toggles on every rising clock edge Previously utilized to minimize logic outside flip-flop Tody, minimizing logic to such extent is not s importnt D flip-flops re thus by fr the most common Copyright 26 5
Non-Idel Flip-Flop Behvior Cn t chnge flip-flop input too close to clock edge Setup time: time tht D must be stble before edge Else, stble vlue not present t internl ltch Hold time: time tht D must be held stble fter edge Else, new vlue doesn t hve time to loop round nd stbilize in internl ltch D C u S R D ltch C D S u R Setup time violtion 2 3 4 7 5 6 D setup time D hold time Leds to oscilltion! Copyright 26 5
Metstbility Violting setup/hold time cn led to bd sitution known s metstble stte Metstble stte: Any flip-flop stte other thn stble or Eventully settles to one or other, but we don t know which For internl circuits, we cn mke sure observe setup time But wht if input comes from externl (synchronous) source, e.g., button press? Prtil solution Insert synchronizer flip-flop for synchronous input Specil flip-flop with very smll setup/hold time Doesn t completely prevent metstbility i i synchronizer D setup time violtion metstble stte Copyright 26 52
Metstbility One flip-flop doesn t completely solve problem How bout dding more synchronizer flip-flops? Helps, but just decreses probbility of metstbility So how solve completely? Cn t! My be unsettling to new designers. But we just cn t gurntee design tht won t ever be metstble. We cn just minimize the men time between filure (MTBF) -- number often given long with circuit Probbility of flip-flop being metstble is low very low very very low incredibly low i Copyright 26 synchronizers 53
Flip-Flop Set nd Reset Inputs Some flip-flops hve dditionl inputs Synchronous reset: clers to on next clock edge Synchronous set: sets to on next clock edge Asynchronous reset: cler to immeditely (not dependent on clock edge) Exmple timing digrm shown Asynchronous set: set to immeditely AR D D D AS R AR cycle cycle 2 cycle 3 cycle 4 D AR Copyright 26 54
Initil Stte of Controller All our FSMs hd initil stte But our sequentil circuit designs did not Cn ccomplish using flip-flops with reset/set inputs Shown circuit initilizes flip-flops to Designer must ensure reset input is during power up of circuit By electronic circuit design Inputs: x; Outputs: b x= b b Off x= On s Stte register b x= On2 Combintionl logic s D D x n n x= On3 reset R S Copyright 26 55
Glitching Glitch: Temporry vlues on outputs tht pper soon fter input chnges, before stble new output vlues Designer must determine whether glitching outputs my pose problem If so, my consider dding flip-flops to outputs Delys output by one clock cycle, but my be OK Copyright 26 56
Active Low Inputs We ve ssumed input ction occur when input is Some inputs re insted ctive when input is -- ctive low Shown with inversion bubble So to reset the shown flip-flop, set R=. Else, keep R=. D R Copyright 26 57
Sequentil circuits Hve stte Chpter Summry Creted robust bit-storge device: D flip-flop Put severl together to build register, which we used to hold stte Defined FSM forml model to describe sequentil behvior Using solid mthemticl models -- Boolen equtions for combintionl circuit, nd FSMs for sequentil circuits -- is very importnt. Defined 5-step process to convert FSM to sequentil circuit Controller So now we know how to build the clss of sequentil circuits known s controllers Copyright 26 58